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[66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.05.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:05:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=7ck5Yi11H9+7Tr2R/vReXNRigmwOrQ9XQ3CLVljTrXQ=; b=g/B1gL53GLumr0V9Uo0I9I3gbC7VhL7i/tYYRUT/0pe7kuYv6BJHA+MStg8RV3Vrh2 rd8Stc1O8SVkir2PN9hSA18j7H96N5ug4pqPzN6JIvu5kuHzXTwxH9i0SF3HPNk92dI9 eLOPoRNtozR9bF0PxTzV7rw6yxVHOpe3KsSj8zFBfTCHl9qpJu+UqJ1kjRgTBXnITrPP RqSZeLTsxxRifLMpWG+rhziE8UdtDtXZ5xVySmxx/DTNX3t6t1QeZxyGDNpKB+iJ6EUq 4AvhxGYnLvoReCuKoFuABtzG236XcE/7YNRAgn8rGQvB9TuAtdjbNdwc/laBNF721XTg T1fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=7ck5Yi11H9+7Tr2R/vReXNRigmwOrQ9XQ3CLVljTrXQ=; b=Ir85uXlLnP0aeD2tpFIbm1keXXDxWmMDGth76xyqv8EwYEWKhrY5T7Qk9oyaEpqpj2 25Nvh4uRTe5CvxatGZ8I715iMfLjxDljV2Or1uMp/JYcRg3Cr/SsjrYlGtc0M5jNgkeK bTvJnY9nhiEO7CALKTPFjIVYSe/M8V9fCxPMri4nr19m/LnwWMVfDoUEmHFxYcjsgASB vC0kwrTWwKgryRBZNwdOykRsPnSW0rDRwtOW4+5RjYX/MuXjLzu0EbecAtaevFEk5ZrC +imXLgP0nKTyRljQFTaHqwUsTwr3YuhfrZknH75D5hQx7iOtUfvaEmRHp1MbD6ZKX+P4 Z6EA== X-Gm-Message-State: APjAAAUo4b2evD04DvcHN90b6rnMPsCeVjBIxYMV+bJlR+EHtvtL+ooo JjtU3G01i7sDZLgNaYJy0O8Y2HSB644= X-Google-Smtp-Source: APXvYqxo8JRavHeQh6gOWSeLBIzlbXYpRWuft/44SyUVjURHjkcy28nsVj0NVFqudMihyDDU3KVKfQ== X-Received: by 2002:a63:4e57:: with SMTP id o23mr40211352pgl.368.1553814303704; Thu, 28 Mar 2019 16:05:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:04:02 -1000 Message-Id: <20190328230404.12909-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PATCH for-4.1 v2 34/36] cpu: Remove CPU_COMMON X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This macro is now always empty, so remove it. This leaves the entire contents of CPUArchState under the control of the guest architecture. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/exec/cpu-defs.h | 2 -- target/alpha/cpu.h | 3 --- target/arm/cpu.h | 4 +--- target/cris/cpu.h | 2 -- target/hppa/cpu.h | 3 --- target/i386/cpu.h | 4 +--- target/lm32/cpu.h | 2 -- target/m68k/cpu.h | 2 -- target/microblaze/cpu.h | 2 -- target/mips/cpu.h | 2 -- target/moxie/cpu.h | 3 --- target/nios2/cpu.h | 2 -- target/openrisc/cpu.h | 2 -- target/ppc/cpu.h | 2 -- target/riscv/cpu.h | 4 ---- target/s390x/cpu.h | 2 -- target/sh4/cpu.h | 2 -- target/sparc/cpu.h | 2 -- target/tilegx/cpu.h | 2 -- target/tricore/cpu.h | 2 -- target/unicore32/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- 22 files changed, 2 insertions(+), 51 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 4cde7d611c..1f75a97701 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -233,8 +233,6 @@ typedef struct CPUTLB { } CPUTLB; =20 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 -#define CPU_COMMON /* Nothing */ - /* * This structure must be placed in ArchCPU immedately * before CPUArchState, as a field named "neg". diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index c63fa929f6..3b2751a45c 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -246,9 +246,6 @@ struct CPUAlphaState { /* This alarm doesn't exist in real hardware; we wish it did. */ uint64_t alarm_expire; =20 - /* Those resources are used only in QEMU core */ - CPU_COMMON - int error_code; =20 uint32_t features; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cae0f509fc..d7a444a5ff 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -635,9 +635,7 @@ typedef struct CPUARMState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - - /* Fields after CPU_COMMON are preserved across CPU reset. */ + /* Fields after this point are preserved across CPU reset. */ =20 /* Internal CPU feature flags. */ uint64_t features; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 9191553cd7..d63d5c29f6 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -163,8 +163,6 @@ typedef struct CPUCRISState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Members from load_info on are preserved across resets. */ void *load_info; } CPUCRISState; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 21395c115c..93e64414a0 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -197,9 +197,6 @@ struct CPUHPPAState { target_ureg cr_back[2]; /* back of cr17/cr18 */ target_ureg shadow[7]; /* shadow registers */ =20 - /* Those resources are used only in QEMU core */ - CPU_COMMON - /* ??? The number of entries isn't specified by the architecture. */ /* ??? Implement a unified itlb/dtlb for the moment. */ /* ??? We should use a more intelligent data structure. */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 239f907f76..8e167dc2a8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1286,9 +1286,7 @@ typedef struct CPUX86State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - - /* Fields after CPU_COMMON are preserved across CPU reset. */ + /* Fields after this point are preserved across CPU reset. */ =20 /* processor features (e.g. for CPUID insn) */ /* Minimum level/xlevel/xlevel2, based on CPU model + features */ diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index ff5c6893bc..473809257b 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -159,8 +159,6 @@ struct CPULM32State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t eba; /* exception base address */ uint32_t deba; /* debug exception base address */ diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 087e73f9e2..3efd038df9 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -143,8 +143,6 @@ typedef struct CPUM68KState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t features; } CPUM68KState; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 618fc8ff1f..aa84480913 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -266,8 +266,6 @@ struct CPUMBState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* These fields are preserved on reset. */ =20 struct { diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 0cb8c94be5..f2bf81f4ee 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1021,8 +1021,6 @@ struct CPUMIPSState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 9be228c383..ac35507db6 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -45,9 +45,6 @@ typedef struct CPUMoxieState { =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - - CPU_COMMON - } CPUMoxieState; =20 #include "qom/cpu.h" diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 875daa2d55..326ce16a9b 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -166,8 +166,6 @@ struct CPUNios2State { =20 uint32_t irq_pending; #endif - - CPU_COMMON }; =20 /** diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 20bc673dda..963c3be65e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -286,8 +286,6 @@ typedef struct CPUOpenRISCState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t cpucfgr; /* CPU configure register */ =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f2f5a498a4..55099564db 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -993,8 +993,6 @@ struct CPUPPCState { int access_type; /* when a memory exception occurs, the access type is stored here */ =20 - CPU_COMMON - /* MMU context - only relevant for full system emulation */ #if !defined(CONFIG_USER_ONLY) #if defined(TARGET_PPC64) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dd5d6a59ee..b3800daed6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -169,10 +169,6 @@ struct CPURISCVState { =20 float_status fp_status; =20 - /* QEMU */ - CPU_COMMON - - /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ }; =20 diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 6020de558e..a543acffa8 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -114,8 +114,6 @@ struct CPUS390XState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - #if !defined(CONFIG_USER_ONLY) uint32_t core_id; /* PoP "CPU address", same as cpu_index */ uint64_t cpuid; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 249b11bda2..a67efb83b5 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -179,8 +179,6 @@ typedef struct CPUSH4State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved over CPU reset. */ int id; /* CPU model */ =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 3c2b849b5a..c085d5e8f1 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -446,8 +446,6 @@ struct CPUSPARCState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ target_ulong version; uint32_t nwindows; diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index deb3e836ea..c2acb43c2b 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -93,8 +93,6 @@ typedef struct CPUTLGState { =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - - CPU_COMMON } CPUTLGState; =20 #include "qom/cpu.h" diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 8106c4be37..5ceb801a11 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -184,8 +184,6 @@ struct CPUTriCoreState { int error_code; uint32_t hflags; /* CPU State */ =20 - CPU_COMMON - /* Internal CPU feature flags. */ uint64_t features; =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 83f9f36058..046d4fedb4 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -55,8 +55,6 @@ typedef struct CPUUniCore32State { float_status fp_status; } ucf64; =20 - CPU_COMMON - /* Internal CPU feature flags. */ uint32_t features; =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 8cb041c93d..52ee31a53d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -511,8 +511,6 @@ typedef struct CPUXtensaState { =20 /* Watchpoints for DBREAK registers */ struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; - - CPU_COMMON } CPUXtensaState; =20 /** --=20 2.17.1