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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH for-4.1 v2 21/36] target/riscv: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 ----- linux-user/riscv/cpu_loop.c | 2 +- target/riscv/cpu_helper.c | 4 ++-- target/riscv/csr.c | 12 ++++++------ target/riscv/op_helper.c | 8 ++++---- 5 files changed, 13 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e97f6c4889..c18dd5eb24 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -211,11 +211,6 @@ typedef struct RISCVCPU { CPURISCVState env; } RISCVCPU; =20 -static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env) -{ - return container_of(env, RISCVCPU, env); -} - static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { return (env->misa & ext) !=3D 0; diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 31700f75d0..c1134597fd 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -25,7 +25,7 @@ =20 void cpu_loop(CPURISCVState *env) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, signum, sigcode; target_ulong sigaddr; target_ulong ret; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b17f169681..72f82c1ccf 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -191,7 +191,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } } =20 - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int va_bits =3D PGSHIFT + levels * ptidxbits; target_ulong mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; target_ulong masked_msbs =3D (addr >> (va_bits - 1)) & mask; @@ -320,7 +320,7 @@ restart: static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int page_fault_exceptions =3D (env->priv_ver >=3D PRIV_VERSION_1_10_0) && get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e1d91b6c60..97a4e10e3e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -296,7 +296,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -307,7 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -382,7 +382,7 @@ static int write_misa(CPURISCVState *env, int csrno, ta= rget_ulong val) =20 /* flush translation cache */ if (val !=3D env->misa) { - tb_flush(CPU(riscv_env_get_cpu(env))); + tb_flush(env_cpu(env)); } =20 env->misa =3D val; @@ -549,7 +549,7 @@ static int write_mbadaddr(CPURISCVState *env, int csrno= , target_ulong val) static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - RISCVCPU *cpu =3D riscv_env_get_cpu(env); + RISCVCPU *cpu =3D env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardw= are */ target_ulong mask =3D write_mask & delegable_ints & ~env->miclaim; uint32_t old_mip; @@ -712,7 +712,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) return 0; } if (env->priv_ver <=3D PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); env->sptbr =3D val & (((target_ulong) 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); } @@ -723,7 +723,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { return -1; } else { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); env->satp =3D val; } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index b7dc18a41e..f078bafbe6 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -28,7 +28,7 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); cs->exception_index =3D exception; cpu_loop_exit_restore(cs, pc); @@ -128,7 +128,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) =20 void helper_wfi(CPURISCVState *env) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && @@ -143,8 +143,8 @@ void helper_wfi(CPURISCVState *env) =20 void helper_tlb_flush(CPURISCVState *env) { - RISCVCPU *cpu =3D riscv_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + if (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && get_field(env->mstatus, MSTATUS_TVM)) { --=20 2.17.1