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[66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=YsmSnuJWj+biwy991xDGs7HYRR660tOeQWELArClkTg=; b=tsu6C5rN1eW6YqLDiQpyncivto8pAzt5e8gcrjgzUp8bMSM2giERneb190tpdABYnO 0pP0Yu6mnKIRaL39Gu9K0pfHAPMBhwlYYVZtr+uaf195W+TndYuIYP34p4Y1ELB5GCqZ UDeyPpUcXeuMFXercrgQCNG1HdjIO5wRjwKeE78YXA78SBZPAVqIhAODfLdR2H7Qkfkd L3KkGehPMah/2grX8xRbYYpmHfOfHpHRfXCgZQqmEoZOK5LwALA3nqAjBKp5qdn09gW6 VZ/yYZG1eW77NrPC04xXFWS/GylBUzM97fnq1wZffvCbD4JIjEoL44e1MRurMRrTFv5w vW2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=YsmSnuJWj+biwy991xDGs7HYRR660tOeQWELArClkTg=; b=Kyfih8fat2JvA/BY32bTqROcivqcStS0ya9CtOYXXi4r2neet3wV9K4vx4wrks3qcw DANPImecQqlev58i5AkH7HB358QNNFMzn2Q+w5mOK2xiOiOZIzDYn7FNdcLCPJ7wqeFN AYWXwZiZJUnY16MDkmv5b0e22WR1iWJFnnHt04H3Z29mAcpqgP5w0Fu7SQfmacRGTI74 rARqC1RoNhUR7RoW78kPrt3VfkeoedtTg0iO2CGxkbdO0AxkQj63OeDv3yztTSefT3kP PPTQYL1N8+mbgBXgCXkETj/MfCbpK6iTRhngBBff4TLfAL6NUx59cHdG+yRO9jt38J7v i96Q== X-Gm-Message-State: APjAAAUOl5AOG1yoECCVHDYknLFZI8DK2izspkyK20Cb5tt9g5DOeKQY xJbJUs9MgLkTW/5dKNdoiUgBCXF/YnY= X-Google-Smtp-Source: APXvYqywNdP12mtnVxeVymQB2/RQDmOnuGWEtccMLHEzdTTeovjgck9hF7SOB3KHP3+O9af+ZHflBg== X-Received: by 2002:aa7:8289:: with SMTP id s9mr30825607pfm.208.1553814274577; Thu, 28 Mar 2019 16:04:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:44 -1000 Message-Id: <20190328230404.12909-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH for-4.1 v2 16/36] target/mips: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 5 ----- hw/intc/mips_gic.c | 2 +- hw/mips/mips_int.c | 2 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/helper.c | 15 +++++---------- target/mips/op_helper.c | 25 +++++++++++-------------- target/mips/translate.c | 3 +-- target/mips/translate_init.inc.c | 4 +--- 8 files changed, 21 insertions(+), 37 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e7ad81becb..914cc26c21 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1051,11 +1051,6 @@ struct MIPSCPU { CPUMIPSState env; }; =20 -static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) -{ - return container_of(env, MIPSCPU, env); -} - #define ENV_OFFSET offsetof(MIPSCPU, env) =20 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index 15e6e40f9f..8f509493ea 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -44,7 +44,7 @@ static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp= , int pin) GIC_VP_MASK_CMP_SHF; } if (kvm_enabled()) { - kvm_mips_set_ipi_interrupt(mips_env_get_cpu(gic->vps[vp].env), + kvm_mips_set_ipi_interrupt(env_archcpu(gic->vps[vp].env), pin + GIC_CPU_PIN_OFFSET, ored_level); } else { diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 5ddeb15848..f899f6ceb3 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -76,7 +76,7 @@ void cpu_mips_irq_init_cpu(MIPSCPU *cpu) qemu_irq *qi; int i; =20 - qi =3D qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env),= 8); + qi =3D qemu_allocate_irqs(cpu_mips_irq_request, env_archcpu(env), 8); for (i =3D 0; i < 8; i++) { env->irq[i] =3D qi[i]; } diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 828137cd84..ac6c6d1504 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -425,7 +425,7 @@ static int do_break(CPUMIPSState *env, target_siginfo_t= *info, =20 void cpu_loop(CPUMIPSState *env) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_siginfo_t info; int trapnr; abi_long ret; diff --git a/target/mips/helper.c b/target/mips/helper.c index c44cdca3b5..1fc0a4ce4b 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -336,10 +336,8 @@ static int get_physical_address (CPUMIPSState *env, hw= addr *physical, =20 void cpu_mips_tlb_flush(CPUMIPSState *env) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - /* Flush qemu's TLB and discard all shadowed entries. */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); env->tlb->tlb_in_use =3D env->tlb->nb_tlb; } =20 @@ -401,7 +399,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ul= ong val) #if defined(TARGET_MIPS64) if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { /* Access to at least one of the 64-bit segments has been disabled= */ - tlb_flush(CPU(mips_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } #endif if (env->CP0_Config3 & (1 << CP0C3_MT)) { @@ -446,7 +444,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val) static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, int rw, int tlb_error) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int exception =3D 0, error_code =3D 0; =20 if (rw =3D=3D MMU_INST_FETCH) { @@ -1400,8 +1398,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - CPUState *cs; + CPUState *cs =3D env_cpu(env); r4k_tlb_t *tlb; target_ulong addr; target_ulong end; @@ -1427,7 +1424,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, = int use_extra) /* 1k pages are not supported. */ mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); if (tlb->V0) { - cs =3D CPU(cpu); addr =3D tlb->VPN & ~mask; #if defined(TARGET_MIPS64) if (addr >=3D (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -1441,7 +1437,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, = int use_extra) } } if (tlb->V1) { - cs =3D CPU(cpu); addr =3D (tlb->VPN & ~mask) | ((mask >> 1) + 1); #if defined(TARGET_MIPS64) if (addr >=3D (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -1462,7 +1457,7 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSStat= e *env, int error_code, uintptr_t pc) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", __func__, exception, error_code); diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0f272a5b93..0705e8c686 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -350,7 +350,7 @@ static inline hwaddr do_translate_address(CPUMIPSState = *env, int rw, uintptr_t re= taddr) { hwaddr paddr; - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 paddr =3D cpu_mips_translate_address(env, address, rw); =20 @@ -699,7 +699,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env,= int *tc) return env; } =20 - cs =3D CPU(mips_env_get_cpu(env)); + cs =3D env_cpu(env); vpe_idx =3D tc_idx / cs->nr_threads; *tc =3D tc_idx % cs->nr_threads; other_cs =3D qemu_get_cpu(vpe_idx); @@ -1298,7 +1298,7 @@ void helper_mttc0_tcrestart(CPUMIPSState *env, target= _ulong arg1) =20 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); + MIPSCPU *cpu =3D env_archcpu(env); =20 env->active_tc.CP0_TCHalt =3D arg1 & 0x1; =20 @@ -1314,7 +1314,7 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ul= ong arg1) { int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - MIPSCPU *other_cpu =3D mips_env_get_cpu(other); + MIPSCPU *other_cpu =3D env_archcpu(other); =20 // TODO: Halt TC / Restart (if allocated+active) TC. =20 @@ -1427,7 +1427,7 @@ void helper_mtc0_pagegrain(CPUMIPSState *env, target_= ulong arg1) =20 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->CP0_SegCtl0 =3D arg1 & CP0SC0_MASK; tlb_flush(cs); @@ -1435,7 +1435,7 @@ void helper_mtc0_segctl0(CPUMIPSState *env, target_ul= ong arg1) =20 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->CP0_SegCtl1 =3D arg1 & CP0SC1_MASK; tlb_flush(cs); @@ -1443,7 +1443,7 @@ void helper_mtc0_segctl1(CPUMIPSState *env, target_ul= ong arg1) =20 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->CP0_SegCtl2 =3D arg1 & CP0SC2_MASK; tlb_flush(cs); @@ -1666,7 +1666,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ul= ong arg1) /* If the ASID changes, flush qemu's TLB. */ if ((old & env->CP0_EntryHi_ASID_mask) !=3D (val & env->CP0_EntryHi_ASID_mask)) { - tlb_flush(CPU(mips_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } } =20 @@ -1686,7 +1686,6 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ul= ong arg1) =20 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); uint32_t val, old; =20 old =3D env->CP0_Status; @@ -1706,7 +1705,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulo= ng arg1) case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; default: - cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; } } @@ -2485,8 +2484,6 @@ static void debug_pre_eret(CPUMIPSState *env) =20 static void debug_post_eret(CPUMIPSState *env) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); @@ -2502,7 +2499,7 @@ static void debug_post_eret(CPUMIPSState *env) case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; default: - cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; } } @@ -2633,7 +2630,7 @@ void helper_pmon(CPUMIPSState *env, int function) =20 void helper_wait(CPUMIPSState *env) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->halted =3D 1; cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); diff --git a/target/mips/translate.c b/target/mips/translate.c index 364bd6dc4f..7ace8c3b96 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29911,8 +29911,7 @@ void cpu_set_exception_base(int vp_index, target_ul= ong address) =20 void cpu_state_reset(CPUMIPSState *env) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 /* Reset registers to their default values */ env->CP0_PRid =3D env->cpu_model->CP0_PRid; diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index bf559aff08..50586a01a2 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -872,8 +872,6 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips= _def_t *def) =20 static void mmu_init (CPUMIPSState *env, const mips_def_t *def) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - env->tlb =3D g_malloc0(sizeof(CPUMIPSTLBContext)); =20 switch (def->mmu_type) { @@ -890,7 +888,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def= _t *def) case MMU_TYPE_R6000: case MMU_TYPE_R8000: default: - cpu_abort(CPU(cpu), "MMU type not supported\n"); + cpu_abort(env_cpu(env), "MMU type not supported\n"); } } #endif /* CONFIG_USER_ONLY */ --=20 2.17.1