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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH for-4.1 v2 01/36] tcg: Fold CPUTLBWindow into CPUTLBDesc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/exec/cpu-defs.h | 17 ++++------------- accel/tcg/cputlb.c | 24 ++++++++++++------------ 2 files changed, 16 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 8f2a848bf5..52d150aaf1 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -127,18 +127,6 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; =20 -/** - * struct CPUTLBWindow - * @begin_ns: host time (in ns) at the beginning of the time window - * @max_entries: maximum number of entries observed in the window - * - * See also: tlb_mmu_resize_locked() - */ -typedef struct CPUTLBWindow { - int64_t begin_ns; - size_t max_entries; -} CPUTLBWindow; - typedef struct CPUTLBDesc { /* * Describe a region covering all of the large pages allocated @@ -148,9 +136,12 @@ typedef struct CPUTLBDesc { */ target_ulong large_page_addr; target_ulong large_page_mask; + /* host time (in ns) at the beginning of the time window */ + int64_t window_begin_ns; + /* maximum number of entries observed in the window */ + size_t window_max_entries; /* The next index to use in the tlb victim table. */ size_t vindex; - CPUTLBWindow window; size_t n_used_entries; } CPUTLBDesc; =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 88cc8389e9..23586f9974 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -79,11 +79,11 @@ static inline size_t sizeof_tlb(CPUArchState *env, uint= ptr_t mmu_idx) return env->tlb_mask[mmu_idx] + (1 << CPU_TLB_ENTRY_BITS); } =20 -static void tlb_window_reset(CPUTLBWindow *window, int64_t ns, +static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, size_t max_entries) { - window->begin_ns =3D ns; - window->max_entries =3D max_entries; + desc->window_begin_ns =3D ns; + desc->window_max_entries =3D max_entries; } =20 static void tlb_dyn_init(CPUArchState *env) @@ -94,7 +94,7 @@ static void tlb_dyn_init(CPUArchState *env) CPUTLBDesc *desc =3D &env->tlb_d[i]; size_t n_entries =3D 1 << CPU_TLB_DYN_DEFAULT_BITS; =20 - tlb_window_reset(&desc->window, get_clock_realtime(), 0); + tlb_window_reset(desc, get_clock_realtime(), 0); desc->n_used_entries =3D 0; env->tlb_mask[i] =3D (n_entries - 1) << CPU_TLB_ENTRY_BITS; env->tlb_table[i] =3D g_new(CPUTLBEntry, n_entries); @@ -151,18 +151,18 @@ static void tlb_mmu_resize_locked(CPUArchState *env, = int mmu_idx) int64_t now =3D get_clock_realtime(); int64_t window_len_ms =3D 100; int64_t window_len_ns =3D window_len_ms * 1000 * 1000; - bool window_expired =3D now > desc->window.begin_ns + window_len_ns; + bool window_expired =3D now > desc->window_begin_ns + window_len_ns; =20 - if (desc->n_used_entries > desc->window.max_entries) { - desc->window.max_entries =3D desc->n_used_entries; + if (desc->n_used_entries > desc->window_max_entries) { + desc->window_max_entries =3D desc->n_used_entries; } - rate =3D desc->window.max_entries * 100 / old_size; + rate =3D desc->window_max_entries * 100 / old_size; =20 if (rate > 70) { new_size =3D MIN(old_size << 1, 1 << CPU_TLB_DYN_MAX_BITS); } else if (rate < 30 && window_expired) { - size_t ceil =3D pow2ceil(desc->window.max_entries); - size_t expected_rate =3D desc->window.max_entries * 100 / ceil; + size_t ceil =3D pow2ceil(desc->window_max_entries); + size_t expected_rate =3D desc->window_max_entries * 100 / ceil; =20 /* * Avoid undersizing when the max number of entries seen is just b= elow @@ -182,7 +182,7 @@ static void tlb_mmu_resize_locked(CPUArchState *env, in= t mmu_idx) =20 if (new_size =3D=3D old_size) { if (window_expired) { - tlb_window_reset(&desc->window, now, desc->n_used_entries); + tlb_window_reset(desc, now, desc->n_used_entries); } return; } @@ -190,7 +190,7 @@ static void tlb_mmu_resize_locked(CPUArchState *env, in= t mmu_idx) g_free(env->tlb_table[mmu_idx]); g_free(env->iotlb[mmu_idx]); =20 - tlb_window_reset(&desc->window, now, 0); + tlb_window_reset(desc, now, 0); /* desc->n_used_entries is cleared by the caller */ env->tlb_mask[mmu_idx] =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; env->tlb_table[mmu_idx] =3D g_try_new(CPUTLBEntry, new_size); --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816413152194.61047973123777; Thu, 28 Mar 2019 16:40:13 -0700 (PDT) Received: from localhost ([127.0.0.1]:43434 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9ecz-00023Z-Ck for importer@patchew.org; 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH for-4.1 v2 02/36] tcg: Split out target/arch/cpu-param.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Acked-by: Alistair Francis Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/exec/cpu-defs.h | 22 +++++++++++++++++++++- target/alpha/cpu-param.h | 19 +++++++++++++++++++ target/alpha/cpu.h | 23 +---------------------- target/arm/cpu-param.h | 22 ++++++++++++++++++++++ target/arm/cpu.h | 33 +++------------------------------ target/cris/cpu-param.h | 5 +++++ target/cris/cpu.h | 11 +---------- target/hppa/cpu-param.h | 22 ++++++++++++++++++++++ target/hppa/cpu.h | 24 +----------------------- target/i386/cpu-param.h | 14 ++++++++++++++ target/i386/cpu.h | 21 --------------------- target/lm32/cpu-param.h | 5 +++++ target/lm32/cpu.h | 12 +++--------- target/m68k/cpu-param.h | 9 +++++++++ target/m68k/cpu.h | 16 ++-------------- target/microblaze/cpu-param.h | 6 ++++++ target/microblaze/cpu.h | 14 ++------------ target/mips/cpu-param.h | 18 ++++++++++++++++++ target/mips/cpu.h | 3 +-- target/mips/mips-defs.h | 15 --------------- target/moxie/cpu-param.h | 5 +++++ target/moxie/cpu.h | 12 +----------- target/nios2/cpu-param.h | 9 +++++++++ target/nios2/cpu.h | 17 ++--------------- target/openrisc/cpu-param.h | 5 +++++ target/openrisc/cpu.h | 14 +++----------- target/ppc/cpu-param.h | 25 +++++++++++++++++++++++++ target/ppc/cpu.h | 35 ++--------------------------------- target/riscv/cpu-param.h | 11 +++++++++++ target/riscv/cpu.h | 21 ++++----------------- target/s390x/cpu-param.h | 5 +++++ target/s390x/cpu.h | 11 +---------- target/sh4/cpu-param.h | 9 +++++++++ target/sh4/cpu.h | 14 +------------- target/sparc/cpu-param.h | 17 +++++++++++++++++ target/sparc/cpu.h | 20 ++------------------ target/tilegx/cpu-param.h | 5 +++++ target/tilegx/cpu.h | 9 +-------- target/tricore/cpu-param.h | 5 +++++ target/tricore/cpu.h | 4 +--- target/tricore/tricore-defs.h | 5 ----- target/unicore32/cpu-param.h | 5 +++++ target/unicore32/cpu.h | 10 +--------- target/xtensa/cpu-param.h | 9 +++++++++ target/xtensa/cpu.h | 21 +++++---------------- 45 files changed, 289 insertions(+), 328 deletions(-) create mode 100644 target/alpha/cpu-param.h create mode 100644 target/arm/cpu-param.h create mode 100644 target/cris/cpu-param.h create mode 100644 target/hppa/cpu-param.h create mode 100644 target/i386/cpu-param.h create mode 100644 target/lm32/cpu-param.h create mode 100644 target/m68k/cpu-param.h create mode 100644 target/microblaze/cpu-param.h create mode 100644 target/mips/cpu-param.h create mode 100644 target/moxie/cpu-param.h create mode 100644 target/nios2/cpu-param.h create mode 100644 target/openrisc/cpu-param.h create mode 100644 target/ppc/cpu-param.h create mode 100644 target/riscv/cpu-param.h create mode 100644 target/s390x/cpu-param.h create mode 100644 target/sh4/cpu-param.h create mode 100644 target/sparc/cpu-param.h create mode 100644 target/tilegx/cpu-param.h create mode 100644 target/tricore/cpu-param.h create mode 100644 target/unicore32/cpu-param.h create mode 100644 target/xtensa/cpu-param.h diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 52d150aaf1..2694481769 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -34,8 +34,28 @@ #endif #include "exec/memattrs.h" =20 +#include "cpu-param.h" + #ifndef TARGET_LONG_BITS -#error TARGET_LONG_BITS must be defined before including this header +# error TARGET_LONG_BITS must be defined in cpu-param.h +#endif +#ifndef NB_MMU_MODES +# error NB_MMU_MODES must be defined in cpu-param.h +#endif +#ifndef TARGET_PHYS_ADDR_SPACE_BITS +# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h +#endif +#ifndef TARGET_VIRT_ADDR_SPACE_BITS +# error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h +#endif +#ifndef TARGET_PAGE_BITS +# ifdef TARGET_PAGE_BITS_VARY +# ifndef TARGET_PAGE_BITS_MIN +# error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h +# endif +# else +# error TARGET_PAGE_BITS must be defined in cpu-param.h +# endif #endif =20 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h new file mode 100644 index 0000000000..6e76e740e2 --- /dev/null +++ b/target/alpha/cpu-param.h @@ -0,0 +1,19 @@ +#define TARGET_LONG_BITS 64 +#define TARGET_PAGE_BITS 13 +#ifdef CONFIG_USER_ONLY +/* + * ??? The kernel likes to give addresses in high memory. If the host has + * more virtual address space than the guest, this can lead to impossible + * allocations. Honor the long-standing assumption that only kernel addrs + * are negative, but otherwise allow allocations anywhere. This could lead + * to tricky emulation problems for programs doing tagged addressing, but + * that's far fewer than encounter the impossible allocation problem. + */ +#define TARGET_PHYS_ADDR_SPACE_BITS 63 +#define TARGET_VIRT_ADDR_SPACE_BITS 63 +#else +/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ +#define TARGET_PHYS_ADDR_SPACE_BITS 44 +#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) +#endif +#define NB_MMU_MODES 3 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 7b50be785d..e4aacbe5a3 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -22,8 +22,8 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" =20 -#define TARGET_LONG_BITS 64 #define ALIGNED_ONLY =20 #define CPUArchState struct CPUAlphaState @@ -31,28 +31,9 @@ /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 -#include "exec/cpu-defs.h" - #define ICACHE_LINE_SIZE 32 #define DCACHE_LINE_SIZE 32 =20 -#define TARGET_PAGE_BITS 13 - -#ifdef CONFIG_USER_ONLY -/* ??? The kernel likes to give addresses in high memory. If the host has - more virtual address space than the guest, this can lead to impossible - allocations. Honor the long-standing assumption that only kernel addrs - are negative, but otherwise allow allocations anywhere. This could lead - to tricky emulation problems for programs doing tagged addressing, but - that's far fewer than encounter the impossible allocation problem. */ -#define TARGET_PHYS_ADDR_SPACE_BITS 63 -#define TARGET_VIRT_ADDR_SPACE_BITS 63 -#else -/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ -#define TARGET_PHYS_ADDR_SPACE_BITS 44 -#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) -#endif - /* Alpha major type */ enum { ALPHA_EV3 =3D 1, @@ -215,8 +196,6 @@ enum { PALcode cheats and usees the KSEG mapping for its code+data rather than physical addresses. */ =20 -#define NB_MMU_MODES 3 - #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user #define MMU_KERNEL_IDX 0 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h new file mode 100644 index 0000000000..e4021e5690 --- /dev/null +++ b/target/arm/cpu-param.h @@ -0,0 +1,22 @@ +#ifdef TARGET_AARCH64 +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 48 +# define TARGET_VIRT_ADDR_SPACE_BITS 48 +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 40 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif + +#ifdef CONFIG_USER_ONLY +#define TARGET_PAGE_BITS 12 +#else +/* + * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 + * have to support 1K tiny pages. + */ +# define TARGET_PAGE_BITS_VARY +# define TARGET_PAGE_BITS_MIN 10 +#endif + +#define NB_MMU_MODES 8 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d4d2836923..12af124159 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -22,23 +22,15 @@ =20 #include "kvm-consts.h" #include "hw/registerfields.h" - -#if defined(TARGET_AARCH64) - /* AArch64 definitions */ -# define TARGET_LONG_BITS 64 -#else -# define TARGET_LONG_BITS 32 -#endif +#include "qemu-common.h" +#include "cpu-qom.h" +#include "exec/cpu-defs.h" =20 /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 #define CPUArchState struct CPUARMState =20 -#include "qemu-common.h" -#include "cpu-qom.h" -#include "exec/cpu-defs.h" - #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 @@ -111,7 +103,6 @@ enum { #define ARM_CPU_VIRQ 2 #define ARM_CPU_VFIQ 3 =20 -#define NB_MMU_MODES 8 /* ARM-specific extra insn start words: * 1: Conditional execution bits * 2: Partial exception syndrome for data aborts @@ -2564,24 +2555,6 @@ bool write_cpustate_to_list(ARMCPU *cpu); #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 =20 -#if defined(CONFIG_USER_ONLY) -#define TARGET_PAGE_BITS 12 -#else -/* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 - * have to support 1K tiny pages. - */ -#define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 10 -#endif - -#if defined(TARGET_AARCH64) -# define TARGET_PHYS_ADDR_SPACE_BITS 48 -# define TARGET_VIRT_ADDR_SPACE_BITS 48 -#else -# define TARGET_PHYS_ADDR_SPACE_BITS 40 -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el) { diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h new file mode 100644 index 0000000000..1da781a22f --- /dev/null +++ b/target/cris/cpu-param.h @@ -0,0 +1,5 @@ +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 13 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 2 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 8bb1dbc989..832796d457 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -23,13 +23,10 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" - -#define TARGET_LONG_BITS 32 +#include "exec/cpu-defs.h" =20 #define CPUArchState struct CPUCRISState =20 -#include "exec/cpu-defs.h" - #define EXCP_NMI 1 #define EXCP_GURU 2 #define EXCP_BUSFAULT 3 @@ -105,8 +102,6 @@ #define CC_A 14 #define CC_P 15 =20 -#define NB_MMU_MODES 2 - typedef struct { uint32_t hi; uint32_t lo; @@ -261,12 +256,8 @@ enum { }; =20 /* CRIS uses 8k pages. */ -#define TARGET_PAGE_BITS 13 #define MMAP_SHIFT TARGET_PAGE_BITS =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h new file mode 100644 index 0000000000..64fd828c39 --- /dev/null +++ b/target/hppa/cpu-param.h @@ -0,0 +1,22 @@ +#ifdef TARGET_HPPA64 +# define TARGET_LONG_BITS 64 +# define TARGET_REGISTER_BITS 64 +# define TARGET_VIRT_ADDR_SPACE_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 64 +#elif defined(CONFIG_USER_ONLY) +# define TARGET_LONG_BITS 32 +# define TARGET_REGISTER_BITS 32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 32 +#else +/* + * In order to form the GVA from space:offset, + * we need a 64-bit virtual address space. + */ +# define TARGET_LONG_BITS 64 +# define TARGET_REGISTER_BITS 32 +# define TARGET_VIRT_ADDR_SPACE_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 32 +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 5 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c062c7969c..fe97786de1 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -22,25 +22,8 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" =20 -#ifdef TARGET_HPPA64 -#define TARGET_LONG_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 -#define TARGET_REGISTER_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 64 -#elif defined(CONFIG_USER_ONLY) -#define TARGET_LONG_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 -#define TARGET_REGISTER_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#else -/* In order to form the GVA from space:offset, - we need a 64-bit virtual address space. */ -#define TARGET_LONG_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 -#define TARGET_REGISTER_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#endif =20 /* PA-RISC 1.x processors have a strong memory model. */ /* ??? While we do not yet implement PA-RISC 2.0, those processors have @@ -50,12 +33,7 @@ =20 #define CPUArchState struct CPUHPPAState =20 -#include "exec/cpu-defs.h" - -#define TARGET_PAGE_BITS 12 - #define ALIGNED_ONLY -#define NB_MMU_MODES 5 #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 3 #define MMU_PHYS_IDX 4 diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h new file mode 100644 index 0000000000..4f2f7457d2 --- /dev/null +++ b/target/i386/cpu-param.h @@ -0,0 +1,14 @@ +#ifdef TARGET_X86_64 +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 52 +/* ??? This is really 48 bits, sign-extended, but the only thing + accessible to userland with bit 48 set is the VSYSCALL, and that + is handled via other mechanisms. */ +# define TARGET_VIRT_ADDR_SPACE_BITS 47 +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 36 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 3 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 83fb522554..6716958276 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -24,13 +24,6 @@ #include "qemu-common.h" #include "cpu-qom.h" #include "hyperv-proto.h" - -#ifdef TARGET_X86_64 -#define TARGET_LONG_BITS 64 -#else -#define TARGET_LONG_BITS 32 -#endif - #include "exec/cpu-defs.h" =20 /* The x86 has a strong memory model with some store-after-load re-orderin= g */ @@ -953,7 +946,6 @@ typedef struct { #define MAX_FIXED_COUNTERS 3 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) =20 -#define NB_MMU_MODES 3 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 #define NB_OPMASK_REGS 8 @@ -1692,19 +1684,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t n= ew_dr7); /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); =20 -#define TARGET_PAGE_BITS 12 - -#ifdef TARGET_X86_64 -#define TARGET_PHYS_ADDR_SPACE_BITS 52 -/* ??? This is really 48 bits, sign-extended, but the only thing - accessible to userland with bit 48 set is the VSYSCALL, and that - is handled via other mechanisms. */ -#define TARGET_VIRT_ADDR_SPACE_BITS 47 -#else -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - /* XXX: This value should match the one returned by CPUID * and in exec.c */ # if defined(TARGET_X86_64) diff --git a/target/lm32/cpu-param.h b/target/lm32/cpu-param.h new file mode 100644 index 0000000000..5262ca5dc6 --- /dev/null +++ b/target/lm32/cpu-param.h @@ -0,0 +1,5 @@ +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 1 diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 66157eefe9..3c9c8a904c 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -20,26 +20,20 @@ #ifndef LM32_CPU_H #define LM32_CPU_H =20 -#define TARGET_LONG_BITS 32 - -#define CPUArchState struct CPULM32State - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" + +#define CPUArchState struct CPULM32State + struct CPULM32State; typedef struct CPULM32State CPULM32State; =20 -#define NB_MMU_MODES 1 -#define TARGET_PAGE_BITS 12 static inline int cpu_mmu_index(CPULM32State *env, bool ifetch) { return 0; } =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - /* Exceptions indices */ enum { EXCP_RESET =3D 0, diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h new file mode 100644 index 0000000000..76a6a7ccd3 --- /dev/null +++ b/target/m68k/cpu-param.h @@ -0,0 +1,9 @@ +#define TARGET_LONG_BITS 32 +/* Coldfire Linux uses 8k pages + * and m68k linux uses 4k pages + * use the smallest one + */ +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 2 diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index f154565117..6bf44604b5 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -21,14 +21,12 @@ #ifndef M68K_CPU_H #define M68K_CPU_H =20 -#define TARGET_LONG_BITS 32 - -#define CPUArchState struct CPUM68KState - #include "qemu-common.h" #include "exec/cpu-defs.h" #include "cpu-qom.h" =20 +#define CPUArchState struct CPUM68KState + #define OS_BYTE 0 #define OS_WORD 1 #define OS_LONG 2 @@ -82,7 +80,6 @@ #define M68K_MAX_TTR 2 #define TTR(type, index) ttr[((type & ACCESS_CODE) =3D=3D ACCESS_CODE) * 2= + index] =20 -#define NB_MMU_MODES 2 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 typedef CPU_LDoubleU FPReg; @@ -503,12 +500,6 @@ void m68k_cpu_list(FILE *f, fprintf_function cpu_fprin= tf); =20 void register_m68k_insns (CPUM68KState *env); =20 -/* Coldfire Linux uses 8k pages - * and m68k linux uses 4k pages - * use the smallest one - */ -#define TARGET_PAGE_BITS 12 - enum { /* 1 bit to define user level / supervisor access */ ACCESS_SUPER =3D 0x01, @@ -523,9 +514,6 @@ enum { ACCESS_DATA =3D 0x20, /* Data load/store access */ }; =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h new file mode 100644 index 0000000000..20e7a68a32 --- /dev/null +++ b/target/microblaze/cpu-param.h @@ -0,0 +1,6 @@ +#define TARGET_LONG_BITS 64 +#define TARGET_PHYS_ADDR_SPACE_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 3 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 792bbc97c7..c8a9d4b146 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -22,13 +22,11 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" - -#define TARGET_LONG_BITS 64 +#include "exec/cpu-defs.h" +#include "fpu/softfloat-types.h" =20 #define CPUArchState struct CPUMBState =20 -#include "exec/cpu-defs.h" -#include "fpu/softfloat-types.h" struct CPUMBState; typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) @@ -228,8 +226,6 @@ typedef struct CPUMBState CPUMBState; #define CC_NE 1 #define CC_EQ 0 =20 -#define NB_MMU_MODES 3 - #define STREAM_EXCEPTION (1 << 0) #define STREAM_ATOMIC (1 << 1) #define STREAM_TEST (1 << 2) @@ -341,12 +337,6 @@ void mb_tcg_init(void); int cpu_mb_signal_handler(int host_signum, void *pinfo, void *puc); =20 -/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 - #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU =20 #define cpu_signal_handler cpu_mb_signal_handler diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h new file mode 100644 index 0000000000..72769a04f8 --- /dev/null +++ b/target/mips/cpu-param.h @@ -0,0 +1,18 @@ +#ifdef TARGET_MIPS64 +# define TARGET_LONG_BITS 64 +#else +# define TARGET_LONG_BITS 32 +#endif +#ifdef TARGET_MIPS64 +#define TARGET_PHYS_ADDR_SPACE_BITS 48 +#define TARGET_VIRT_ADDR_SPACE_BITS 48 +#else +#define TARGET_PHYS_ADDR_SPACE_BITS 40 +# ifdef CONFIG_USER_ONLY +# define TARGET_VIRT_ADDR_SPACE_BITS 31 +# else +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 4 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a10eeb0de3..1cd59e31f7 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -7,9 +7,9 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" -#include "mips-defs.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" +#include "mips-defs.h" =20 #define TCG_GUEST_DEFAULT_MO (0) =20 @@ -89,7 +89,6 @@ struct CPUMIPSFPUContext { #define FP_UNIMPLEMENTED 32 }; =20 -#define NB_MMU_MODES 4 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index dbdb4b2b2d..bbf056a548 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -5,23 +5,8 @@ //#define USE_HOST_FLOAT_REGS =20 /* Real pages are variable size... */ -#define TARGET_PAGE_BITS 12 #define MIPS_TLB_MAX 128 =20 -#if defined(TARGET_MIPS64) -#define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 48 -#define TARGET_VIRT_ADDR_SPACE_BITS 48 -#else -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 40 -# ifdef CONFIG_USER_ONLY -# define TARGET_VIRT_ADDR_SPACE_BITS 31 -# else -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif -#endif - /* * bit definitions for insn_flags (ISAs/ASEs flags) * ------------------------------------------------ diff --git a/target/moxie/cpu-param.h b/target/moxie/cpu-param.h new file mode 100644 index 0000000000..0ff0fc72b4 --- /dev/null +++ b/target/moxie/cpu-param.h @@ -0,0 +1,5 @@ +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 /* 4k */ +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 1 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 080df4ee6f..b060c69e38 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -21,8 +21,7 @@ #define MOXIE_CPU_H =20 #include "qemu-common.h" - -#define TARGET_LONG_BITS 32 +#include "exec/cpu-defs.h" =20 #define CPUArchState struct CPUMoxieState =20 @@ -33,15 +32,6 @@ #define MOXIE_EX_MMU_MISS 4 #define MOXIE_EX_BREAK 16 =20 -#include "exec/cpu-defs.h" - -#define TARGET_PAGE_BITS 12 /* 4k */ - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - -#define NB_MMU_MODES 1 - typedef struct CPUMoxieState { =20 uint32_t flags; /* general execution flags */ diff --git a/target/nios2/cpu-param.h b/target/nios2/cpu-param.h new file mode 100644 index 0000000000..fb21e8f202 --- /dev/null +++ b/target/nios2/cpu-param.h @@ -0,0 +1,9 @@ +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#ifdef CONFIG_USER_ONLY +# define TARGET_VIRT_ADDR_SPACE_BITS 31 +#else +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define NB_MMU_MODES 2 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 047f3764b7..50fb5fef46 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -21,13 +21,11 @@ #define CPU_NIOS2_H =20 #include "qemu-common.h" - -#define TARGET_LONG_BITS 32 +#include "exec/cpu-defs.h" +#include "qom/cpu.h" =20 #define CPUArchState struct CPUNios2State =20 -#include "exec/cpu-defs.h" -#include "qom/cpu.h" struct CPUNios2State; typedef struct CPUNios2State CPUNios2State; #if !defined(CONFIG_USER_ONLY) @@ -163,8 +161,6 @@ typedef struct Nios2CPUClass { =20 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 =20 -#define NB_MMU_MODES 2 - struct CPUNios2State { uint32_t regs[NUM_CORE_REGS]; =20 @@ -223,13 +219,6 @@ void nios2_cpu_do_unaligned_access(CPUState *cpu, vadd= r addr, qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu); void nios2_check_interrupts(CPUNios2State *env); =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#ifdef CONFIG_USER_ONLY -# define TARGET_VIRT_ADDR_SPACE_BITS 31 -#else -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU =20 #define cpu_gen_code cpu_nios2_gen_code @@ -237,8 +226,6 @@ void nios2_check_interrupts(CPUNios2State *env); =20 #define CPU_SAVE_VERSION 1 =20 -#define TARGET_PAGE_BITS 12 - /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h new file mode 100644 index 0000000000..c0cbdb424f --- /dev/null +++ b/target/openrisc/cpu-param.h @@ -0,0 +1,5 @@ +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 13 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 3 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index f1b31bc24a..9bd137d9a2 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -20,17 +20,15 @@ #ifndef OPENRISC_CPU_H #define OPENRISC_CPU_H =20 -#define TARGET_LONG_BITS 32 +#include "qemu-common.h" +#include "exec/cpu-defs.h" +#include "qom/cpu.h" =20 #define CPUArchState struct CPUOpenRISCState =20 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ struct OpenRISCCPU; =20 -#include "qemu-common.h" -#include "exec/cpu-defs.h" -#include "qom/cpu.h" - #define TYPE_OPENRISC_CPU "or1k-cpu" =20 #define OPENRISC_CPU_CLASS(klass) \ @@ -56,7 +54,6 @@ typedef struct OpenRISCCPUClass { void (*parent_reset)(CPUState *cpu); } OpenRISCCPUClass; =20 -#define NB_MMU_MODES 3 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 enum { @@ -65,11 +62,6 @@ enum { MMU_USER_IDX =3D 2, }; =20 -#define TARGET_PAGE_BITS 13 - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define SET_FP_CAUSE(reg, v) do {\ (reg) =3D ((reg) & ~(0x3f << 12)) | \ ((v & 0x3f) << 12);\ diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h new file mode 100644 index 0000000000..6679d81394 --- /dev/null +++ b/target/ppc/cpu-param.h @@ -0,0 +1,25 @@ +#ifdef TARGET_PPC64 +# define TARGET_LONG_BITS 64 +/* + * Note that the official physical address space bits is 62-M where M + * is implementation dependent. I've not looked up M for the set of + * cpus we emulate at the system level. + */ +#define TARGET_PHYS_ADDR_SPACE_BITS 62 +/* + * Note that the PPC environment architecture talks about 80 bit virtual + * addresses, with segmentation. Obviously that's not all visible to a + * single process, which is all we're concerned with here. + */ +# ifdef TARGET_ABI32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# else +# define TARGET_VIRT_ADDR_SPACE_BITS 64 +# endif +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 36 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 10 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index fc12b4688e..1867215b0f 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -22,48 +22,18 @@ =20 #include "qemu-common.h" #include "qemu/int128.h" +#include "exec/cpu-defs.h" +#include "cpu-qom.h" =20 //#define PPC_EMULATE_32BITS_HYPV =20 -#if defined (TARGET_PPC64) -/* PowerPC 64 definitions */ -#define TARGET_LONG_BITS 64 -#define TARGET_PAGE_BITS 12 - #define TCG_GUEST_DEFAULT_MO 0 =20 -/* Note that the official physical address space bits is 62-M where M - is implementation dependent. I've not looked up M for the set of - cpus we emulate at the system level. */ -#define TARGET_PHYS_ADDR_SPACE_BITS 62 - -/* Note that the PPC environment architecture talks about 80 bit virtual - addresses, with segmentation. Obviously that's not all visible to a - single process, which is all we're concerned with here. */ -#ifdef TARGET_ABI32 -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#else -# define TARGET_VIRT_ADDR_SPACE_BITS 64 -#endif - #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 =20 -#else /* defined (TARGET_PPC64) */ -/* PowerPC 32 definitions */ -#define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - -#endif /* defined (TARGET_PPC64) */ - #define CPUArchState struct CPUPPCState =20 -#include "exec/cpu-defs.h" -#include "cpu-qom.h" - #if defined (TARGET_PPC64) #define PPC_ELF_MACHINE EM_PPC64 #else @@ -966,7 +936,6 @@ struct ppc_radix_page_info { * real/paged mode combinations. The other two modes are for external PID * load/store. */ -#define NB_MMU_MODES 10 #define MMU_MODE8_SUFFIX _epl #define MMU_MODE9_SUFFIX _eps #define PPC_TLB_EPID_LOAD 8 diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h new file mode 100644 index 0000000000..5e38540c27 --- /dev/null +++ b/target/riscv/cpu-param.h @@ -0,0 +1,11 @@ +#if defined(TARGET_RISCV64) +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ +# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ +#elif defined(TARGET_RISCV32) +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ +# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ +#endif +#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ +#define NB_MMU_MODES 4 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 20bce8742e..7d9b07ebc0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -20,27 +20,15 @@ #ifndef RISCV_CPU_H #define RISCV_CPU_H =20 -/* QEMU addressing/paging config */ -#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ -#if defined(TARGET_RISCV64) -#define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ -#define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ -#elif defined(TARGET_RISCV32) -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ -#define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ -#endif - -#define TCG_GUEST_DEFAULT_MO 0 - -#define CPUArchState struct CPURISCVState - #include "qemu-common.h" #include "qom/cpu.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" =20 +#define TCG_GUEST_DEFAULT_MO 0 + +#define CPUArchState struct CPURISCVState + #define TYPE_RISCV_CPU "riscv-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -96,7 +84,6 @@ enum { =20 #define TRANSLATE_FAIL 1 #define TRANSLATE_SUCCESS 0 -#define NB_MMU_MODES 4 #define MMU_USER_IDX 3 =20 #define MAX_RISCV_PMPS (16) diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h new file mode 100644 index 0000000000..0ba05b0f2a --- /dev/null +++ b/target/s390x/cpu-param.h @@ -0,0 +1,5 @@ +#define TARGET_LONG_BITS 64 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define NB_MMU_MODES 4 diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index cb6d77053a..2ef3134177 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -24,26 +24,17 @@ #include "qemu-common.h" #include "cpu-qom.h" #include "cpu_models.h" - -#define TARGET_LONG_BITS 64 +#include "exec/cpu-defs.h" =20 #define ELF_MACHINE_UNAME "S390X" =20 #define CPUArchState struct CPUS390XState =20 -#include "exec/cpu-defs.h" - /* The z/Architecture has a strong memory model with some store-after-load= re-ordering */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 - #include "exec/cpu-all.h" =20 -#define NB_MMU_MODES 4 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 #define MMU_MODE0_SUFFIX _primary diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h new file mode 100644 index 0000000000..83f170ba21 --- /dev/null +++ b/target/sh4/cpu-param.h @@ -0,0 +1,9 @@ +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 /* 4k */ +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#ifdef CONFIG_USER_ONLY +# define TARGET_VIRT_ADDR_SPACE_BITS 31 +#else +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define NB_MMU_MODES 2 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 775b5743bf..894b6c6df9 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -22,8 +22,8 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" =20 -#define TARGET_LONG_BITS 32 #define ALIGNED_ONLY =20 /* CPU Subtypes */ @@ -38,17 +38,6 @@ =20 #define CPUArchState struct CPUSH4State =20 -#include "exec/cpu-defs.h" - -#define TARGET_PAGE_BITS 12 /* 4k XXXXX */ - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#ifdef CONFIG_USER_ONLY -# define TARGET_VIRT_ADDR_SPACE_BITS 31 -#else -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - #define SR_MD 30 #define SR_RB 29 #define SR_BL 28 @@ -132,7 +121,6 @@ typedef struct tlb_t { #define UTLB_SIZE 64 #define ITLB_SIZE 4 =20 -#define NB_MMU_MODES 2 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 enum sh_features { diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h new file mode 100644 index 0000000000..224876220a --- /dev/null +++ b/target/sparc/cpu-param.h @@ -0,0 +1,17 @@ +#ifdef TARGET_SPARC64 +# define TARGET_LONG_BITS 64 +# define TARGET_PAGE_BITS 13 /* 8k */ +# define TARGET_PHYS_ADDR_SPACE_BITS 41 +# ifdef TARGET_ABI32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# else +# define TARGET_VIRT_ADDR_SPACE_BITS 44 +# endif +# define NB_MMU_MODES 6 +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PAGE_BITS 12 /* 4k */ +# define TARGET_PHYS_ADDR_SPACE_BITS 36 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# define NB_MMU_MODES 3 +#endif diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4972ebcfd4..a2975928d5 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -4,31 +4,18 @@ #include "qemu-common.h" #include "qemu/bswap.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" =20 #define ALIGNED_ONLY =20 #if !defined(TARGET_SPARC64) -#define TARGET_LONG_BITS 32 #define TARGET_DPREGS 16 -#define TARGET_PAGE_BITS 12 /* 4k */ -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 #else -#define TARGET_LONG_BITS 64 #define TARGET_DPREGS 32 -#define TARGET_PAGE_BITS 13 /* 8k */ -#define TARGET_PHYS_ADDR_SPACE_BITS 41 -# ifdef TARGET_ABI32 -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -# else -# define TARGET_VIRT_ADDR_SPACE_BITS 44 -# endif #endif =20 #define CPUArchState struct CPUSPARCState =20 -#include "exec/cpu-defs.h" - /*#define EXCP_INTERRUPT 0x100*/ =20 /* trap definitions */ @@ -225,10 +212,7 @@ enum { #define MIN_NWINDOWS 3 #define MAX_NWINDOWS 32 =20 -#if !defined(TARGET_SPARC64) -#define NB_MMU_MODES 3 -#else -#define NB_MMU_MODES 6 +#ifdef TARGET_SPARC64 typedef struct trap_state { uint64_t tpc; uint64_t tnpc; diff --git a/target/tilegx/cpu-param.h b/target/tilegx/cpu-param.h new file mode 100644 index 0000000000..16e3497dae --- /dev/null +++ b/target/tilegx/cpu-param.h @@ -0,0 +1,5 @@ +#define TARGET_LONG_BITS 64 +#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */ +#define TARGET_PHYS_ADDR_SPACE_BITS 42 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define NB_MMU_MODES 1 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 238f8d36d7..429a6c6b43 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -21,13 +21,9 @@ #define TILEGX_CPU_H =20 #include "qemu-common.h" - -#define TARGET_LONG_BITS 64 - -#define CPUArchState struct CPUTLGState - #include "exec/cpu-defs.h" =20 +#define CPUArchState struct CPUTLGState =20 /* TILE-Gx common register alias */ #define TILEGX_R_RE 0 /* 0 register, for function/syscall return val= ue */ @@ -154,9 +150,6 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState= *env) #define ENV_OFFSET offsetof(TileGXCPU, env) =20 /* TILE-Gx memory attributes */ -#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */ -#define TARGET_PHYS_ADDR_SPACE_BITS 42 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ =20 #include "exec/cpu-all.h" diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h new file mode 100644 index 0000000000..60bd5a715a --- /dev/null +++ b/target/tricore/cpu-param.h @@ -0,0 +1,5 @@ +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 14 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 3 diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 00e69dc154..67dc3b6272 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -20,10 +20,10 @@ #ifndef TRICORE_CPU_H #define TRICORE_CPU_H =20 -#include "tricore-defs.h" #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "tricore-defs.h" =20 #define CPUArchState struct CPUTriCoreState =20 @@ -31,8 +31,6 @@ struct CPUTriCoreState; =20 struct tricore_boot_info; =20 -#define NB_MMU_MODES 3 - typedef struct tricore_def_t tricore_def_t; =20 typedef struct CPUTriCoreState CPUTriCoreState; diff --git a/target/tricore/tricore-defs.h b/target/tricore/tricore-defs.h index e871aa1c6b..f5e0a0bed8 100644 --- a/target/tricore/tricore-defs.h +++ b/target/tricore/tricore-defs.h @@ -18,11 +18,6 @@ #ifndef QEMU_TRICORE_DEFS_H #define QEMU_TRICORE_DEFS_H =20 -#define TARGET_PAGE_BITS 14 -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define TRICORE_TLB_MAX 128 =20 #endif /* QEMU_TRICORE_DEFS_H */ diff --git a/target/unicore32/cpu-param.h b/target/unicore32/cpu-param.h new file mode 100644 index 0000000000..86d0976713 --- /dev/null +++ b/target/unicore32/cpu-param.h @@ -0,0 +1,5 @@ +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 2 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 735d3ae9dc..9ee7798465 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -12,19 +12,11 @@ #ifndef UNICORE32_CPU_H #define UNICORE32_CPU_H =20 -#define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - -#define CPUArchState struct CPUUniCore32State - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define NB_MMU_MODES 2 +#define CPUArchState struct CPUUniCore32State =20 typedef struct CPUUniCore32State { /* Regs for current mode. */ diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h new file mode 100644 index 0000000000..000e6026c0 --- /dev/null +++ b/target/xtensa/cpu-param.h @@ -0,0 +1,9 @@ +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#ifdef CONFIG_USER_ONLY +#define TARGET_VIRT_ADDR_SPACE_BITS 30 +#else +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define NB_MMU_MODES 4 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 4d8152682f..93440357b0 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -28,28 +28,17 @@ #ifndef XTENSA_CPU_H #define XTENSA_CPU_H =20 -#define ALIGNED_ONLY -#define TARGET_LONG_BITS 32 - -/* Xtensa processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - -#define CPUArchState struct CPUXtensaState - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "xtensa-isa.h" =20 -#define NB_MMU_MODES 4 +#define ALIGNED_ONLY =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#ifdef CONFIG_USER_ONLY -#define TARGET_VIRT_ADDR_SPACE_BITS 30 -#else -#define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif -#define TARGET_PAGE_BITS 12 +/* Xtensa processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + +#define CPUArchState struct CPUXtensaState =20 enum { /* Additional instructions */ --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553817192662464.2743118614553; Thu, 28 Mar 2019 16:53:12 -0700 (PDT) Received: from localhost ([127.0.0.1]:43648 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9epS-0004tY-Jx for importer@patchew.org; Thu, 28 Mar 2019 19:53:02 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42458) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKw-0001my-Fh for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4G-0002w6-96 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:20 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:45249) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4F-0002uF-QI for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:16 -0400 Received: by mail-pg1-x542.google.com with SMTP id y3so214207pgk.12 for ; Thu, 28 Mar 2019 16:04:15 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. [66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.12 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=Fb5A9XYyOzc3rPYAOzYPcsFMuag9eOD/o4V7O3wHv+I=; b=k9YzPN8P3Uyfn6k8kAt3OfBC2HBA/JYu7Sr1Fx1Trsg1V6oAiD47PKjJ55xfpO54uh +6FNEtF1z4no9azIc74H/mpvB7FHTSXOhg5mvC+3705gVeLBXf9i0LDifrmmC+1tZCwe xh5h36+ITyDZS5FR48g5V7VoQSJXQNbWnvdpycsew46b+ol26IvOY1WhO7weh3OV4Q5b 8x/qCBZNtq3epye231NWgYfoCkGLwMBgL2vwMtGeliI5XH0TjTR9CpMG3URXcspz3pB+ Im/iHu71xveyunH/439wgtAzd7SSyn62ZVernuFBo9do0XidhHuhbXKCrIJN6l5Wb2Q4 7ejQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Fb5A9XYyOzc3rPYAOzYPcsFMuag9eOD/o4V7O3wHv+I=; b=h9h3bbbawg9av47JGoK+hOQZD1XcIRqlI1u397SLbX7BKBwzMZiWEsmIw+k/3cX9UD YqmakDLe2GYuSnAp1Kv6jBnfFbxtcYbJec+h2bzhkGx0CXvvt1aUtPkvR1KLT45SWvat 70GAGeNRKjNw9MKkqNpOl6EKql9RTpJi3nFoqvqCk9Utqo1Ns817hTxH1OLNUj53IPKT 37Vg/ITtJz+YQXxDBvgnl9N8R90DW2gG4wT+LFEeZn4up+6uEz4aJhzCNbRSEGdjB99v ZQN/rqvRIS/u/VFRh7REFZ1tm8igktYy6pdDeG64Hny+2U/7r/9uCJn24M/u/6fMKKvS C2Yw== X-Gm-Message-State: APjAAAV4I679I6ijLgfV3mtYtfKFA0vdPkgnPsjuaQo616/8h1LhCvKp rIRHiFZ+VR6O2rcQpt6vjrQR5/+QIxA= X-Google-Smtp-Source: APXvYqwYtTiuI6yuSlnHZUseSZON4L4R3o9hsRBxCt+BeSVqd7RzXUcFi1KJBxjLrKNIgdNWi7d3Vg== X-Received: by 2002:a65:4844:: with SMTP id i4mr41480162pgs.347.1553814253975; Thu, 28 Mar 2019 16:04:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:31 -1000 Message-Id: <20190328230404.12909-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH for-4.1 v2 03/36] tcg: Create struct CPUTLB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move all softmmu tlb data into this structure. Arrange the members so that we are able to place mask+table together and at a smaller absolute offset from ENV. Acked-by: Alistair Francis Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- accel/tcg/softmmu_template.h | 4 +- include/exec/cpu-defs.h | 61 ++++++++------- include/exec/cpu_ldst.h | 6 +- accel/tcg/cputlb.c | 147 ++++++++++++++++++----------------- target/arm/translate-a64.c | 2 +- tcg/aarch64/tcg-target.inc.c | 10 +-- tcg/arm/tcg-target.inc.c | 10 +-- tcg/i386/tcg-target.inc.c | 4 +- tcg/mips/tcg-target.inc.c | 12 +-- tcg/ppc/tcg-target.inc.c | 8 +- tcg/riscv/tcg-target.inc.c | 12 +-- tcg/s390/tcg-target.inc.c | 8 +- tcg/sparc/tcg-target.inc.c | 12 +-- 13 files changed, 135 insertions(+), 161 deletions(-) diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h index e970a8b378..fc6371aed1 100644 --- a/accel/tcg/softmmu_template.h +++ b/accel/tcg/softmmu_template.h @@ -102,7 +102,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchSt= ate *env, bool recheck, MMUAccessType access_type) { - CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; + CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, recheck, access_type, DATA_SIZE); } @@ -273,7 +273,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState = *env, uintptr_t retaddr, bool recheck) { - CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; + CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, recheck, DATA_SIZE); } diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 2694481769..fbe8945606 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -78,6 +78,7 @@ typedef uint64_t target_ulong; #endif =20 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) + /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 =20 @@ -147,6 +148,10 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; =20 +/* + * Data elements that are per MMU mode, minus the bits accessed by + * the TCG fast path. + */ typedef struct CPUTLBDesc { /* * Describe a region covering all of the large pages allocated @@ -160,16 +165,31 @@ typedef struct CPUTLBDesc { int64_t window_begin_ns; /* maximum number of entries observed in the window */ size_t window_max_entries; + size_t n_used_entries; /* The next index to use in the tlb victim table. */ size_t vindex; - size_t n_used_entries; + /* The tlb victim table, in two parts. */ + CPUTLBEntry vtable[CPU_VTLB_SIZE]; + CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; + /* The iotlb. */ + CPUIOTLBEntry *iotlb; } CPUTLBDesc; =20 +/* + * Data elements that are per MMU mode, accessed by the fast path. + */ +typedef struct CPUTLBDescFast { + /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ + uintptr_t mask; + /* The array of tlb entries itself. */ + CPUTLBEntry *table; +} CPUTLBDescFast; + /* * Data elements that are shared between all MMU modes. */ typedef struct CPUTLBCommon { - /* Serialize updates to tlb_table and tlb_v_table, and others as noted= . */ + /* Serialize updates to tlb_table and vtable, and others as noted. */ QemuSpin lock; /* * Within dirty, for each bit N, modifications have been made to @@ -187,35 +207,24 @@ typedef struct CPUTLBCommon { size_t elide_flush_count; } CPUTLBCommon; =20 -# define CPU_TLB \ - /* tlb_mask[i] contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ \ - uintptr_t tlb_mask[NB_MMU_MODES]; \ - CPUTLBEntry *tlb_table[NB_MMU_MODES]; -# define CPU_IOTLB \ - CPUIOTLBEntry *iotlb[NB_MMU_MODES]; - /* + * The entire softmmu tlb, for all MMU modes. * The meaning of each of the MMU modes is defined in the target code. - * Note that NB_MMU_MODES is not yet defined; we can only reference it - * within preprocessor defines that will be expanded later. */ -#define CPU_COMMON_TLB \ - CPUTLBCommon tlb_c; \ - CPUTLBDesc tlb_d[NB_MMU_MODES]; \ - CPU_TLB \ - CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ - CPU_IOTLB \ - CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; +typedef struct CPUTLB { + CPUTLBDescFast f[NB_MMU_MODES]; + CPUTLBDesc d[NB_MMU_MODES]; + CPUTLBCommon c; +} CPUTLB; + +/* There are target-specific members named "tlb". This is temporary. */ +#define CPU_COMMON CPUTLB tlb_; +#define env_tlb(ENV) (&(ENV)->tlb_) =20 #else =20 -#define CPU_COMMON_TLB - -#endif - - -#define CPU_COMMON \ - /* soft mmu support */ \ - CPU_COMMON_TLB \ +#define CPU_COMMON /* Nothing */ + +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 #endif diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index d78041d7a0..09abd95008 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -139,21 +139,21 @@ static inline target_ulong tlb_addr_write(const CPUTL= BEntry *entry) static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, target_ulong addr) { - uintptr_t size_mask =3D env->tlb_mask[mmu_idx] >> CPU_TLB_ENTRY_BITS; + uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; =20 return (addr >> TARGET_PAGE_BITS) & size_mask; } =20 static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx) { - return (env->tlb_mask[mmu_idx] >> CPU_TLB_ENTRY_BITS) + 1; + return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1; } =20 /* Find the TLB entry corresponding to the mmu_idx + address pair. */ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, target_ulong addr) { - return &env->tlb_table[mmu_idx][tlb_index(env, mmu_idx, addr)]; + return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; } =20 #ifdef MMU_MODE0_SUFFIX diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 23586f9974..c28b6b6328 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -76,7 +76,7 @@ QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); =20 static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx) { - return env->tlb_mask[mmu_idx] + (1 << CPU_TLB_ENTRY_BITS); + return env_tlb(env)->f[mmu_idx].mask + (1 << CPU_TLB_ENTRY_BITS); } =20 static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, @@ -91,14 +91,14 @@ static void tlb_dyn_init(CPUArchState *env) int i; =20 for (i =3D 0; i < NB_MMU_MODES; i++) { - CPUTLBDesc *desc =3D &env->tlb_d[i]; + CPUTLBDesc *desc =3D &env_tlb(env)->d[i]; size_t n_entries =3D 1 << CPU_TLB_DYN_DEFAULT_BITS; =20 tlb_window_reset(desc, get_clock_realtime(), 0); desc->n_used_entries =3D 0; - env->tlb_mask[i] =3D (n_entries - 1) << CPU_TLB_ENTRY_BITS; - env->tlb_table[i] =3D g_new(CPUTLBEntry, n_entries); - env->iotlb[i] =3D g_new(CPUIOTLBEntry, n_entries); + env_tlb(env)->f[i].mask =3D (n_entries - 1) << CPU_TLB_ENTRY_BITS; + env_tlb(env)->f[i].table =3D g_new(CPUTLBEntry, n_entries); + env_tlb(env)->d[i].iotlb =3D g_new(CPUIOTLBEntry, n_entries); } } =20 @@ -144,7 +144,7 @@ static void tlb_dyn_init(CPUArchState *env) */ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx) { - CPUTLBDesc *desc =3D &env->tlb_d[mmu_idx]; + CPUTLBDesc *desc =3D &env_tlb(env)->d[mmu_idx]; size_t old_size =3D tlb_n_entries(env, mmu_idx); size_t rate; size_t new_size =3D old_size; @@ -187,14 +187,14 @@ static void tlb_mmu_resize_locked(CPUArchState *env, = int mmu_idx) return; } =20 - g_free(env->tlb_table[mmu_idx]); - g_free(env->iotlb[mmu_idx]); + g_free(env_tlb(env)->f[mmu_idx].table); + g_free(env_tlb(env)->d[mmu_idx].iotlb); =20 tlb_window_reset(desc, now, 0); /* desc->n_used_entries is cleared by the caller */ - env->tlb_mask[mmu_idx] =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; - env->tlb_table[mmu_idx] =3D g_try_new(CPUTLBEntry, new_size); - env->iotlb[mmu_idx] =3D g_try_new(CPUIOTLBEntry, new_size); + env_tlb(env)->f[mmu_idx].mask =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; + env_tlb(env)->f[mmu_idx].table =3D g_try_new(CPUTLBEntry, new_size); + env_tlb(env)->d[mmu_idx].iotlb =3D g_try_new(CPUIOTLBEntry, new_size); /* * If the allocations fail, try smaller sizes. We just freed some * memory, so going back to half of new_size has a good chance of work= ing. @@ -202,46 +202,47 @@ static void tlb_mmu_resize_locked(CPUArchState *env, = int mmu_idx) * allocations to fail though, so we progressively reduce the allocati= on * size, aborting if we cannot even allocate the smallest TLB we suppo= rt. */ - while (env->tlb_table[mmu_idx] =3D=3D NULL || env->iotlb[mmu_idx] =3D= =3D NULL) { + while (env_tlb(env)->f[mmu_idx].table =3D=3D NULL || + env_tlb(env)->d[mmu_idx].iotlb =3D=3D NULL) { if (new_size =3D=3D (1 << CPU_TLB_DYN_MIN_BITS)) { error_report("%s: %s", __func__, strerror(errno)); abort(); } new_size =3D MAX(new_size >> 1, 1 << CPU_TLB_DYN_MIN_BITS); - env->tlb_mask[mmu_idx] =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; + env_tlb(env)->f[mmu_idx].mask =3D (new_size - 1) << CPU_TLB_ENTRY_= BITS; =20 - g_free(env->tlb_table[mmu_idx]); - g_free(env->iotlb[mmu_idx]); - env->tlb_table[mmu_idx] =3D g_try_new(CPUTLBEntry, new_size); - env->iotlb[mmu_idx] =3D g_try_new(CPUIOTLBEntry, new_size); + g_free(env_tlb(env)->f[mmu_idx].table); + g_free(env_tlb(env)->d[mmu_idx].iotlb); + env_tlb(env)->f[mmu_idx].table =3D g_try_new(CPUTLBEntry, new_size= ); + env_tlb(env)->d[mmu_idx].iotlb =3D g_try_new(CPUIOTLBEntry, new_si= ze); } } =20 static inline void tlb_table_flush_by_mmuidx(CPUArchState *env, int mmu_id= x) { tlb_mmu_resize_locked(env, mmu_idx); - memset(env->tlb_table[mmu_idx], -1, sizeof_tlb(env, mmu_idx)); - env->tlb_d[mmu_idx].n_used_entries =3D 0; + memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx)); + env_tlb(env)->d[mmu_idx].n_used_entries =3D 0; } =20 static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu= _idx) { - env->tlb_d[mmu_idx].n_used_entries++; + env_tlb(env)->d[mmu_idx].n_used_entries++; } =20 static inline void tlb_n_used_entries_dec(CPUArchState *env, uintptr_t mmu= _idx) { - env->tlb_d[mmu_idx].n_used_entries--; + env_tlb(env)->d[mmu_idx].n_used_entries--; } =20 void tlb_init(CPUState *cpu) { CPUArchState *env =3D cpu->env_ptr; =20 - qemu_spin_init(&env->tlb_c.lock); + qemu_spin_init(&env_tlb(env)->c.lock); =20 /* Ensure that cpu_reset performs a full flush. */ - env->tlb_c.dirty =3D ALL_MMUIDX_BITS; + env_tlb(env)->c.dirty =3D ALL_MMUIDX_BITS; =20 tlb_dyn_init(env); } @@ -273,9 +274,9 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, siz= e_t *pelide) CPU_FOREACH(cpu) { CPUArchState *env =3D cpu->env_ptr; =20 - full +=3D atomic_read(&env->tlb_c.full_flush_count); - part +=3D atomic_read(&env->tlb_c.part_flush_count); - elide +=3D atomic_read(&env->tlb_c.elide_flush_count); + full +=3D atomic_read(&env_tlb(env)->c.full_flush_count); + part +=3D atomic_read(&env_tlb(env)->c.part_flush_count); + elide +=3D atomic_read(&env_tlb(env)->c.elide_flush_count); } *pfull =3D full; *ppart =3D part; @@ -285,10 +286,11 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, s= ize_t *pelide) static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx) { tlb_table_flush_by_mmuidx(env, mmu_idx); - memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0])); - env->tlb_d[mmu_idx].large_page_addr =3D -1; - env->tlb_d[mmu_idx].large_page_mask =3D -1; - env->tlb_d[mmu_idx].vindex =3D 0; + env_tlb(env)->d[mmu_idx].large_page_addr =3D -1; + env_tlb(env)->d[mmu_idx].large_page_mask =3D -1; + env_tlb(env)->d[mmu_idx].vindex =3D 0; + memset(env_tlb(env)->d[mmu_idx].vtable, -1, + sizeof(env_tlb(env)->d[0].vtable)); } =20 static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data = data) @@ -301,31 +303,31 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *= cpu, run_on_cpu_data data) =20 tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked); =20 - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); =20 - all_dirty =3D env->tlb_c.dirty; + all_dirty =3D env_tlb(env)->c.dirty; to_clean =3D asked & all_dirty; all_dirty &=3D ~to_clean; - env->tlb_c.dirty =3D all_dirty; + env_tlb(env)->c.dirty =3D all_dirty; =20 for (work =3D to_clean; work !=3D 0; work &=3D work - 1) { int mmu_idx =3D ctz32(work); tlb_flush_one_mmuidx_locked(env, mmu_idx); } =20 - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); =20 cpu_tb_jmp_cache_clear(cpu); =20 if (to_clean =3D=3D ALL_MMUIDX_BITS) { - atomic_set(&env->tlb_c.full_flush_count, - env->tlb_c.full_flush_count + 1); + atomic_set(&env_tlb(env)->c.full_flush_count, + env_tlb(env)->c.full_flush_count + 1); } else { - atomic_set(&env->tlb_c.part_flush_count, - env->tlb_c.part_flush_count + ctpop16(to_clean)); + atomic_set(&env_tlb(env)->c.part_flush_count, + env_tlb(env)->c.part_flush_count + ctpop16(to_clean)); if (to_clean !=3D asked) { - atomic_set(&env->tlb_c.elide_flush_count, - env->tlb_c.elide_flush_count + + atomic_set(&env_tlb(env)->c.elide_flush_count, + env_tlb(env)->c.elide_flush_count + ctpop16(asked & ~to_clean)); } } @@ -410,11 +412,12 @@ static inline bool tlb_flush_entry_locked(CPUTLBEntry= *tlb_entry, static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_i= dx, target_ulong page) { + CPUTLBDesc *d =3D &env_tlb(env)->d[mmu_idx]; int k; =20 assert_cpu_is_self(ENV_GET_CPU(env)); for (k =3D 0; k < CPU_VTLB_SIZE; k++) { - if (tlb_flush_entry_locked(&env->tlb_v_table[mmu_idx][k], page)) { + if (tlb_flush_entry_locked(&d->vtable[k], page)) { tlb_n_used_entries_dec(env, mmu_idx); } } @@ -423,8 +426,8 @@ static inline void tlb_flush_vtlb_page_locked(CPUArchSt= ate *env, int mmu_idx, static void tlb_flush_page_locked(CPUArchState *env, int midx, target_ulong page) { - target_ulong lp_addr =3D env->tlb_d[midx].large_page_addr; - target_ulong lp_mask =3D env->tlb_d[midx].large_page_mask; + target_ulong lp_addr =3D env_tlb(env)->d[midx].large_page_addr; + target_ulong lp_mask =3D env_tlb(env)->d[midx].large_page_mask; =20 /* Check if we need to flush due to large pages. */ if ((page & lp_mask) =3D=3D lp_addr) { @@ -459,13 +462,13 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUSt= ate *cpu, tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n", addr, mmu_idx_bitmap); =20 - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { tlb_flush_page_locked(env, mmu_idx, addr); } } - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); =20 tb_flush_jmp_cache(cpu, addr); } @@ -609,22 +612,22 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1= , ram_addr_t length) int mmu_idx; =20 env =3D cpu->env_ptr; - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; unsigned int n =3D tlb_n_entries(env, mmu_idx); =20 for (i =3D 0; i < n; i++) { - tlb_reset_dirty_range_locked(&env->tlb_table[mmu_idx][i], star= t1, - length); + tlb_reset_dirty_range_locked(&env_tlb(env)->f[mmu_idx].table[i= ], + start1, length); } =20 for (i =3D 0; i < CPU_VTLB_SIZE; i++) { - tlb_reset_dirty_range_locked(&env->tlb_v_table[mmu_idx][i], st= art1, - length); + tlb_reset_dirty_range_locked(&env_tlb(env)->d[mmu_idx].vtable[= i], + start1, length); } } - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); } =20 /* Called with tlb_c.lock held */ @@ -646,7 +649,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) assert_cpu_is_self(cpu); =20 vaddr &=3D TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, vaddr), vaddr); } @@ -654,10 +657,10 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { int k; for (k =3D 0; k < CPU_VTLB_SIZE; k++) { - tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr); + tlb_set_dirty1_locked(&env_tlb(env)->d[mmu_idx].vtable[k], vad= dr); } } - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); } =20 /* Our TLB does not support large pages, so remember the area covered by @@ -665,7 +668,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) static void tlb_add_large_page(CPUArchState *env, int mmu_idx, target_ulong vaddr, target_ulong size) { - target_ulong lp_addr =3D env->tlb_d[mmu_idx].large_page_addr; + target_ulong lp_addr =3D env_tlb(env)->d[mmu_idx].large_page_addr; target_ulong lp_mask =3D ~(size - 1); =20 if (lp_addr =3D=3D (target_ulong)-1) { @@ -675,13 +678,13 @@ static void tlb_add_large_page(CPUArchState *env, int= mmu_idx, /* Extend the existing region to include the new page. This is a compromise between unnecessary flushes and the cost of maintaining a full variable size TLB. */ - lp_mask &=3D env->tlb_d[mmu_idx].large_page_mask; + lp_mask &=3D env_tlb(env)->d[mmu_idx].large_page_mask; while (((lp_addr ^ vaddr) & lp_mask) !=3D 0) { lp_mask <<=3D 1; } } - env->tlb_d[mmu_idx].large_page_addr =3D lp_addr & lp_mask; - env->tlb_d[mmu_idx].large_page_mask =3D lp_mask; + env_tlb(env)->d[mmu_idx].large_page_addr =3D lp_addr & lp_mask; + env_tlb(env)->d[mmu_idx].large_page_mask =3D lp_mask; } =20 /* Add a new TLB entry. At most one entry for a given virtual address @@ -757,10 +760,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, * a longer critical section, but this is not a concern since the TLB = lock * is unlikely to be contended. */ - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); =20 /* Note that the tlb is no longer clean. */ - env->tlb_c.dirty |=3D 1 << mmu_idx; + env_tlb(env)->c.dirty |=3D 1 << mmu_idx; =20 /* Make sure there's no cached translation for the new page. */ tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); @@ -770,12 +773,12 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, * different page; otherwise just overwrite the stale data. */ if (!tlb_hit_page_anyprot(te, vaddr_page) && !tlb_entry_is_empty(te)) { - unsigned vidx =3D env->tlb_d[mmu_idx].vindex++ % CPU_VTLB_SIZE; - CPUTLBEntry *tv =3D &env->tlb_v_table[mmu_idx][vidx]; + unsigned vidx =3D env_tlb(env)->d[mmu_idx].vindex++ % CPU_VTLB_SIZ= E; + CPUTLBEntry *tv =3D &env_tlb(env)->d[mmu_idx].vtable[vidx]; =20 /* Evict the old entry into the victim tlb. */ copy_tlb_helper_locked(tv, te); - env->iotlb_v[mmu_idx][vidx] =3D env->iotlb[mmu_idx][index]; + env_tlb(env)->d[mmu_idx].viotlb[vidx] =3D env_tlb(env)->d[mmu_idx]= .iotlb[index]; tlb_n_used_entries_dec(env, mmu_idx); } =20 @@ -792,8 +795,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ - env->iotlb[mmu_idx][index].addr =3D iotlb - vaddr_page; - env->iotlb[mmu_idx][index].attrs =3D attrs; + env_tlb(env)->d[mmu_idx].iotlb[index].addr =3D iotlb - vaddr_page; + env_tlb(env)->d[mmu_idx].iotlb[index].attrs =3D attrs; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -829,7 +832,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, =20 copy_tlb_helper_locked(te, &tn); tlb_n_used_entries_inc(env, mmu_idx); - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); } =20 /* Add a new TLB entry, but without specifying the memory @@ -996,7 +999,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mm= u_idx, size_t index, =20 assert_cpu_is_self(ENV_GET_CPU(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { - CPUTLBEntry *vtlb =3D &env->tlb_v_table[mmu_idx][vidx]; + CPUTLBEntry *vtlb =3D &env_tlb(env)->d[mmu_idx].vtable[vidx]; target_ulong cmp; =20 /* elt_ofs might correspond to .addr_write, so use atomic_read */ @@ -1008,16 +1011,16 @@ static bool victim_tlb_hit(CPUArchState *env, size_= t mmu_idx, size_t index, =20 if (cmp =3D=3D page) { /* Found entry in victim tlb, swap tlb and iotlb. */ - CPUTLBEntry tmptlb, *tlb =3D &env->tlb_table[mmu_idx][index]; + CPUTLBEntry tmptlb, *tlb =3D &env_tlb(env)->f[mmu_idx].table[i= ndex]; =20 - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); copy_tlb_helper_locked(&tmptlb, tlb); copy_tlb_helper_locked(tlb, vtlb); copy_tlb_helper_locked(vtlb, &tmptlb); - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); =20 - CPUIOTLBEntry tmpio, *io =3D &env->iotlb[mmu_idx][index]; - CPUIOTLBEntry *vio =3D &env->iotlb_v[mmu_idx][vidx]; + CPUIOTLBEntry tmpio, *io =3D &env_tlb(env)->d[mmu_idx].iotlb[i= ndex]; + CPUIOTLBEntry *vio =3D &env_tlb(env)->d[mmu_idx].viotlb[vidx]; tmpio =3D *io; *io =3D *vio; *vio =3D tmpio; return true; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index dcdeb80176..dfa90a9db2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14163,7 +14163,7 @@ static bool is_guarded_page(CPUARMState *env, Disas= Context *s) * table entry even for that case. */ return (tlb_hit(entry->addr_code, addr) && - env->iotlb[mmu_idx][index].attrs.target_tlb_bit0); + env_tlb(env)->d[mmu_idx].iotlb[index].attrs.target_tlb_bit0); #endif } =20 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index d57f9e500f..5e6af10faf 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1451,12 +1451,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool = is_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr; } =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - /* We expect to use a 24-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1]) +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) > 0xffffff); =20 /* Load and compare a TLB entry, emitting the conditional jump to the @@ -1467,8 +1463,8 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg ad= dr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int mask_ofs =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_ofs =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_ofs =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_ofs =3D offsetof(CPUArchState, tlb_.f[mem_index].table); unsigned a_bits =3D get_alignment_bits(opc); unsigned s_bits =3D opc & MO_SIZE; unsigned a_mask =3D (1u << a_bits) - 1; diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 2245a8aeb9..04c2eebb41 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1235,12 +1235,8 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGRe= g argreg, =20 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - /* We expect to use a 20-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1]) +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) > 0xfffff); =20 /* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter @@ -1251,8 +1247,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addrlo, TCGReg addrhi, { int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index e0670e5098..1bd33389c9 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1654,10 +1654,10 @@ static inline void tcg_out_tlb_load(TCGContext *s, = TCGReg addrlo, TCGReg addrhi, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); =20 tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_mask[mem_index])); + offsetof(CPUArchState, tlb_.f[mem_index].mask)); =20 tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_table[mem_index])); + offsetof(CPUArchState, tlb_.f[mem_index].table)); =20 /* If the required alignment is at least as large as the access, simply copy the address and mask. For lesser alignments, check that we do= n't diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 8a92e916dd..b827579317 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1201,14 +1201,6 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int= i, TCGReg al, TCGReg ah) return i; } =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - -/* We expect tlb_mask to be "near" tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) - - offsetof(CPUArchState, tlb_mask) >=3D 0x8000); - /* * Perform the tlb comparison operation. * The complete host address is placed in BASE. @@ -1222,8 +1214,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg ba= se, TCGReg addrl, unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); int mem_index =3D get_mmuidx(oi); - int mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); int add_off =3D offsetof(CPUTLBEntry, addend); int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 773690f1d9..1f717745c1 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1505,10 +1505,6 @@ static void * const qemu_st_helpers[16] =3D { [MO_BEQ] =3D helper_be_stq_mmu, }; =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - /* Perform the TLB load and compare. Places the result of the comparison in CR7, loads the addend of the TLB into R3, and returns the register containing the guest address (zero-extended into R4). Clobbers R0 and = R2. */ @@ -1521,8 +1517,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemO= p opc, =3D (is_read ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index b785f4acb7..c1f9c784bc 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -961,14 +961,6 @@ static void * const qemu_st_helpers[16] =3D { /* We don't support oversize guests */ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - -/* We expect tlb_mask to be "near" tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) - - offsetof(CPUArchState, tlb_mask) >=3D 0x800); - static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) @@ -981,8 +973,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addr= l, int mask_off, table_off; TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; =20 - mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); if (table_off > 0x7ff) { int mask_hi =3D mask_off - sextreg(mask_off, 0, 12); int table_hi =3D table_off - sextreg(table_off, 0, 12); diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 7db90b3bae..3a8794d9bd 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1538,9 +1538,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= MemOp opc, TCGReg data, #include "tcg-ldst.inc.c" =20 /* We're expecting to use a 20-bit signed offset on the tlb memory ops. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_mask[NB_MMU_MODES - 1]) - > 0x7ffff); -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1]) +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) > 0x7ffff); =20 /* Load and compare a TLB entry, leaving the flags set. Loads the TLB @@ -1552,8 +1550,8 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg = addr_reg, TCGMemOp opc, unsigned a_bits =3D get_alignment_bits(opc); unsigned s_mask =3D (1 << s_bits) - 1; unsigned a_mask =3D (1 << a_bits) - 1; - int mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); int ofs, a_off; uint64_t tlb_mask; =20 diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 7a61839dc1..be10124e11 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1074,19 +1074,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int = count) The result of the TLB comparison is in %[ix]cc. The sanitized address is in the returned register, maybe %o0. The TLB addend is in %o1. */ =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - -/* We expect tlb_mask to be "near" tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) - - offsetof(CPUArchState, tlb_mask) >=3D (1 << 13)); - static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, TCGMemOp opc, int which) { - int mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); TCGReg base =3D TCG_AREG0; const TCGReg r0 =3D TCG_REG_O0; const TCGReg r1 =3D TCG_REG_O1; --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816140623993.2791586981666; Thu, 28 Mar 2019 16:35:40 -0700 (PDT) Received: from localhost ([127.0.0.1]:43359 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eYU-0006ur-BP for importer@patchew.org; Thu, 28 Mar 2019 19:35:30 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42393) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKw-0001jU-Mi for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4H-0002wb-HH for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:20 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:36787) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4H-0002wI-4Z for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:17 -0400 Received: by mail-pl1-x644.google.com with SMTP id k2so68244plt.3 for ; Thu, 28 Mar 2019 16:04:16 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH for-4.1 v2 04/36] cpu: Define CPUArchState with typedef X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For all targets, do this just before including exec/cpu-all.h. Acked-by: Alistair Francis Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/alpha/cpu.h | 4 ++-- target/arm/cpu.h | 4 ++-- target/cris/cpu.h | 4 ++-- target/hppa/cpu.h | 4 ++-- target/i386/cpu.h | 5 ++--- target/lm32/cpu.h | 5 ++--- target/m68k/cpu.h | 4 ++-- target/microblaze/cpu.h | 5 ++--- target/mips/cpu.h | 6 ++---- target/moxie/cpu.h | 4 ++-- target/nios2/cpu.h | 5 ++--- target/openrisc/cpu.h | 4 ++-- target/ppc/cpu.h | 4 ++-- target/riscv/cpu.h | 4 ++-- target/s390x/cpu.h | 8 ++++---- target/sh4/cpu.h | 4 ++-- target/sparc/cpu.h | 4 ++-- target/tilegx/cpu.h | 4 ++-- target/tricore/cpu.h | 6 +----- target/unicore32/cpu.h | 4 ++-- target/xtensa/cpu.h | 4 ++-- 21 files changed, 43 insertions(+), 53 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e4aacbe5a3..fac622aa02 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -26,8 +26,6 @@ =20 #define ALIGNED_ONLY =20 -#define CPUArchState struct CPUAlphaState - /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 @@ -302,6 +300,8 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, #define cpu_list alpha_cpu_list #define cpu_signal_handler cpu_alpha_signal_handler =20 +typedef CPUAlphaState CPUArchState; + #include "exec/cpu-all.h" =20 enum { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12af124159..e043fd3f97 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -29,8 +29,6 @@ /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 -#define CPUArchState struct CPUARMState - #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 @@ -3045,6 +3043,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMS= tate *env) } } =20 +typedef CPUARMState CPUArchState; + #include "exec/cpu-all.h" =20 /* Bit usage in the TB flags field: bit 31 indicates whether we are diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 832796d457..95662c36b2 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -25,8 +25,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUCRISState - #define EXCP_NMI 1 #define EXCP_GURU 2 #define EXCP_BUSFAULT 3 @@ -286,6 +284,8 @@ int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int size, int rw, #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 =20 +typedef CPUCRISState CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *p= c, diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fe97786de1..7c1d1e0a0e 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -31,8 +31,6 @@ basis. It's probably easier to fall back to a strong memory model. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL =20 -#define CPUArchState struct CPUHPPAState - #define ALIGNED_ONLY #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 3 @@ -232,6 +230,8 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *e= nv) #define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e)) #define ENV_OFFSET offsetof(HPPACPU, env) =20 +typedef CPUHPPAState CPUArchState; + #include "exec/cpu-all.h" =20 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6716958276..84ca69ea1a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1,4 +1,3 @@ - /* * i386 virtual CPU header * @@ -44,8 +43,6 @@ #define ELF_MACHINE_UNAME "i686" #endif =20 -#define CPUArchState struct CPUX86State - enum { R_EAX =3D 0, R_ECX =3D 1, @@ -1752,6 +1749,8 @@ static inline target_long lshift(target_long x, int n) /* translate.c */ void tcg_x86_init(void); =20 +typedef CPUX86State CPUArchState; + #include "exec/cpu-all.h" #include "svm.h" =20 diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 3c9c8a904c..5b24cfcc1f 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -24,9 +24,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPULM32State - -struct CPULM32State; typedef struct CPULM32State CPULM32State; =20 static inline int cpu_mmu_index(CPULM32State *env, bool ifetch) @@ -259,6 +256,8 @@ bool lm32_cpu_do_semihosting(CPUState *cs); int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, int mmu_idx); =20 +typedef CPULM32State CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *p= c, diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 6bf44604b5..48c051c7d2 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -25,8 +25,6 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" =20 -#define CPUArchState struct CPUM68KState - #define OS_BYTE 0 #define OS_WORD 1 #define OS_LONG 2 @@ -537,6 +535,8 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr ad= dr, bool is_write, bool is_exec, int is_asi, unsigned size); =20 +typedef CPUM68KState CPUArchState; + #include "exec/cpu-all.h" =20 /* TB flags */ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c8a9d4b146..dddd58e165 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -25,9 +25,6 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" =20 -#define CPUArchState struct CPUMBState - -struct CPUMBState; typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" @@ -368,6 +365,8 @@ static inline int cpu_mmu_index (CPUMBState *env, bool = ifetch) int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); =20 +typedef CPUMBState CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1cd59e31f7..608ae23289 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -3,8 +3,6 @@ =20 #define ALIGNED_ONLY =20 -#define CPUArchState struct CPUMIPSState - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" @@ -13,8 +11,6 @@ =20 #define TCG_GUEST_DEFAULT_MO (0) =20 -struct CPUMIPSState; - typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; =20 /* MSA Context */ @@ -1094,6 +1090,8 @@ static inline int cpu_mmu_index (CPUMIPSState *env, b= ool ifetch) return hflags_mmu_index(env->hflags); } =20 +typedef CPUMIPSState CPUArchState; + #include "exec/cpu-all.h" =20 /* Memory access type : diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index b060c69e38..10ba6aa7be 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -23,8 +23,6 @@ #include "qemu-common.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUMoxieState - #define MOXIE_EX_DIV0 0 #define MOXIE_EX_BAD 1 #define MOXIE_EX_IRQ 2 @@ -120,6 +118,8 @@ static inline int cpu_mmu_index(CPUMoxieState *env, boo= l ifetch) return 0; } =20 +typedef CPUMoxieState CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *= pc, diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 50fb5fef46..2b4bd25d65 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -24,9 +24,6 @@ #include "exec/cpu-defs.h" #include "qom/cpu.h" =20 -#define CPUArchState struct CPUNios2State - -struct CPUNios2State; typedef struct CPUNios2State CPUNios2State; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" @@ -246,6 +243,8 @@ static inline int cpu_interrupts_enabled(CPUNios2State = *env) return env->regs[CR_STATUS] & CR_STATUS_PIE; } =20 +typedef CPUNios2State CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *= pc, diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 9bd137d9a2..9bd583f13a 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -24,8 +24,6 @@ #include "exec/cpu-defs.h" #include "qom/cpu.h" =20 -#define CPUArchState struct CPUOpenRISCState - /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ struct OpenRISCCPU; =20 @@ -365,6 +363,8 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU =20 +typedef CPUOpenRISCState CPUArchState; + #include "exec/cpu-all.h" =20 #define TB_FLAGS_SM SR_SM diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1867215b0f..18825ebafc 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -32,8 +32,6 @@ #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 =20 -#define CPUArchState struct CPUPPCState - #if defined (TARGET_PPC64) #define PPC_ELF_MACHINE EM_PPC64 #else @@ -1366,6 +1364,8 @@ void ppc_compat_add_property(Object *obj, const char = *name, Error **errp); #endif /* defined(TARGET_PPC64) */ =20 +typedef CPUPPCState CPUArchState; + #include "exec/cpu-all.h" =20 /*************************************************************************= ****/ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d9b07ebc0..df71872a82 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,8 +27,6 @@ =20 #define TCG_GUEST_DEFAULT_MO 0 =20 -#define CPUArchState struct CPURISCVState - #define TYPE_RISCV_CPU "riscv-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -325,6 +323,8 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations = *ops); =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 +typedef CPURISCVState CPUArchState; + #include "exec/cpu-all.h" =20 #endif /* RISCV_CPU_H */ diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 2ef3134177..00b9e6d3b8 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -28,13 +28,9 @@ =20 #define ELF_MACHINE_UNAME "S390X" =20 -#define CPUArchState struct CPUS390XState - /* The z/Architecture has a strong memory model with some store-after-load= re-ordering */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 -#include "exec/cpu-all.h" - #define TARGET_INSN_START_EXTRA_WORDS 1 =20 #define MMU_MODE0_SUFFIX _primary @@ -796,4 +792,8 @@ void s390_init_sigp(void); /* outside of target/s390x/ */ S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); =20 +typedef CPUS390XState CPUArchState; + +#include "exec/cpu-all.h" + #endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 894b6c6df9..788de6e22a 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -36,8 +36,6 @@ #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) =20 -#define CPUArchState struct CPUSH4State - #define SR_MD 30 #define SR_RB 29 #define SR_BL 28 @@ -282,6 +280,8 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool= ifetch) } } =20 +typedef CPUSH4State CPUArchState; + #include "exec/cpu-all.h" =20 /* Memory access type */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index a2975928d5..41c39578c2 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -14,8 +14,6 @@ #define TARGET_DPREGS 32 #endif =20 -#define CPUArchState struct CPUSPARCState - /*#define EXCP_INTERRUPT 0x100*/ =20 /* trap definitions */ @@ -731,6 +729,8 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, = int pil) #endif } =20 +typedef CPUSPARCState CPUArchState; + #include "exec/cpu-all.h" =20 #ifdef TARGET_SPARC64 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 429a6c6b43..2fbf14d508 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -23,8 +23,6 @@ #include "qemu-common.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUTLGState - /* TILE-Gx common register alias */ #define TILEGX_R_RE 0 /* 0 register, for function/syscall return val= ue */ #define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */ @@ -152,6 +150,8 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState= *env) /* TILE-Gx memory attributes */ #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ =20 +typedef CPUTLGState CPUArchState; + #include "exec/cpu-all.h" =20 void tilegx_tcg_init(void); diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 67dc3b6272..c958deedd9 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -25,10 +25,6 @@ #include "exec/cpu-defs.h" #include "tricore-defs.h" =20 -#define CPUArchState struct CPUTriCoreState - -struct CPUTriCoreState; - struct tricore_boot_info; =20 typedef struct tricore_def_t tricore_def_t; @@ -383,7 +379,7 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, b= ool ifetch) return 0; } =20 - +typedef CPUTriCoreState CPUArchState; =20 #include "exec/cpu-all.h" =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 9ee7798465..68323b9541 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -16,8 +16,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUUniCore32State - typedef struct CPUUniCore32State { /* Regs for current mode. */ uint32_t regs[32]; @@ -154,6 +152,8 @@ static inline int cpu_mmu_index(CPUUniCore32State *env,= bool ifetch) return (env->uncached_asr & ASR_M) =3D=3D ASR_MODE_USER ? 1 : 0; } =20 +typedef CPUUniCore32State CPUArchState; + #include "exec/cpu-all.h" =20 #define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 93440357b0..40e4f1f568 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -38,8 +38,6 @@ /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 -#define CPUArchState struct CPUXtensaState - enum { /* Additional instructions */ XTENSA_OPTION_CODE_DENSITY, @@ -789,6 +787,8 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState = *env, target_ulong *pc, } } =20 +typedef CPUXtensaState CPUArchState; + #include "exec/cpu-all.h" =20 #endif --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816864568452.328842281093; Thu, 28 Mar 2019 16:47:44 -0700 (PDT) Received: from localhost ([127.0.0.1]:43578 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9ekD-0000YS-Eu for importer@patchew.org; Thu, 28 Mar 2019 19:47:37 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42735) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKv-000226-Ut for qemu-devel@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PATCH for-4.1 v2 05/36] cpu: Define ArchCPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For all targets, do this just before including exec/cpu-all.h. Acked-by: Alistair Francis Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/alpha/cpu.h | 1 + target/arm/cpu.h | 1 + target/cris/cpu.h | 1 + target/hppa/cpu.h | 1 + target/i386/cpu.h | 1 + target/lm32/cpu.h | 1 + target/m68k/cpu.h | 1 + target/microblaze/cpu.h | 1 + target/mips/cpu.h | 1 + target/moxie/cpu.h | 1 + target/nios2/cpu.h | 1 + target/openrisc/cpu.h | 1 + target/ppc/cpu.h | 1 + target/riscv/cpu.h | 1 + target/s390x/cpu.h | 1 + target/sh4/cpu.h | 1 + target/sparc/cpu.h | 1 + target/tilegx/cpu.h | 1 + target/tricore/cpu.h | 1 + target/unicore32/cpu.h | 1 + target/xtensa/cpu.h | 1 + 21 files changed, 21 insertions(+) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index fac622aa02..6629b869d2 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -301,6 +301,7 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, #define cpu_signal_handler cpu_alpha_signal_handler =20 typedef CPUAlphaState CPUArchState; +typedef AlphaCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e043fd3f97..30776ce15f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3044,6 +3044,7 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMS= tate *env) } =20 typedef CPUARMState CPUArchState; +typedef ARMCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 95662c36b2..bcd17bf88b 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -285,6 +285,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int size, int rw, #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 =20 typedef CPUCRISState CPUArchState; +typedef CRISCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7c1d1e0a0e..f90b11dd0b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -231,6 +231,7 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *e= nv) #define ENV_OFFSET offsetof(HPPACPU, env) =20 typedef CPUHPPAState CPUArchState; +typedef HPPACPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 84ca69ea1a..bb1464d451 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1750,6 +1750,7 @@ static inline target_long lshift(target_long x, int n) void tcg_x86_init(void); =20 typedef CPUX86State CPUArchState; +typedef X86CPU ArchCPU; =20 #include "exec/cpu-all.h" #include "svm.h" diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 5b24cfcc1f..5eef4ccfc5 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -257,6 +257,7 @@ int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int size, int rw, int mmu_idx); =20 typedef CPULM32State CPUArchState; +typedef LM32CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 48c051c7d2..5db18909cc 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -536,6 +536,7 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr ad= dr, unsigned size); =20 typedef CPUM68KState CPUArchState; +typedef M68kCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index dddd58e165..d7c1846e49 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -366,6 +366,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr addres= s, int size, int rw, int mmu_idx); =20 typedef CPUMBState CPUArchState; +typedef MicroBlazeCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 608ae23289..8c5a40b5ad 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1091,6 +1091,7 @@ static inline int cpu_mmu_index (CPUMIPSState *env, b= ool ifetch) } =20 typedef CPUMIPSState CPUArchState; +typedef MIPSCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 10ba6aa7be..4bc5e07af9 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -119,6 +119,7 @@ static inline int cpu_mmu_index(CPUMoxieState *env, boo= l ifetch) } =20 typedef CPUMoxieState CPUArchState; +typedef MoxieCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2b4bd25d65..272ab10e67 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -244,6 +244,7 @@ static inline int cpu_interrupts_enabled(CPUNios2State = *env) } =20 typedef CPUNios2State CPUArchState; +typedef Nios2CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 9bd583f13a..20ea1ca973 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -364,6 +364,7 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU =20 typedef CPUOpenRISCState CPUArchState; +typedef OpenRISCCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 18825ebafc..c5ea29a949 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1365,6 +1365,7 @@ void ppc_compat_add_property(Object *obj, const char = *name, #endif /* defined(TARGET_PPC64) */ =20 typedef CPUPPCState CPUArchState; +typedef PowerPCCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index df71872a82..1fdac0c8d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -324,6 +324,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations = *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 typedef CPURISCVState CPUArchState; +typedef RISCVCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 00b9e6d3b8..762184c62d 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -793,6 +793,7 @@ void s390_init_sigp(void); S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); =20 typedef CPUS390XState CPUArchState; +typedef S390CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 788de6e22a..926cf63825 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -281,6 +281,7 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool= ifetch) } =20 typedef CPUSH4State CPUArchState; +typedef SuperHCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 41c39578c2..55c0004887 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -730,6 +730,7 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, = int pil) } =20 typedef CPUSPARCState CPUArchState; +typedef SPARCCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 2fbf14d508..042a7a0c71 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -151,6 +151,7 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState= *env) #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ =20 typedef CPUTLGState CPUArchState; +typedef TileGXCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index c958deedd9..dc4bcea955 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -380,6 +380,7 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, b= ool ifetch) } =20 typedef CPUTriCoreState CPUArchState; +typedef TriCoreCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 68323b9541..968154e6fa 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -153,6 +153,7 @@ static inline int cpu_mmu_index(CPUUniCore32State *env,= bool ifetch) } =20 typedef CPUUniCore32State CPUArchState; +typedef UniCore32CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 40e4f1f568..6f9721bc28 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -788,6 +788,7 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState = *env, target_ulong *pc, } =20 typedef CPUXtensaState CPUArchState; +typedef XtensaCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816522558488.89738864184324; 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[66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.17 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=KPYkjUd9kRyWIwoR6PCqd81REdLPKdsAJ5B38rb9oSE=; b=H7QJW5qFsxnzAu68JPEmoJV/Zin6HY7oQzfZly9hMCccQWbfFJGeOUXeu4sz9TVE0b aw2sK4nPVWPw8AXkns4BGMoaO5+6rF2KJDULSpZ8C26Pxa3a7KWk/Pwq5TV8j0TyAI5x wCGEVw9SvPtEzFTkFdjurpt4hLJJFjx2Fke/dNcFttISpqW7X6aev2x9UfO5E5tdQI/d BrJ4yjoP/zJEkXuck6Cs6sxdqxnrxhelaf1L0AkYyIV0b8FGFEgz2da7XI0HhVYK/T+t /Hng1ABYADbyPtAkEqAJpyzXxybM3tAGwCHqSyld9kiG3Sink73GDHpind23AZeMxPu/ JEVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=KPYkjUd9kRyWIwoR6PCqd81REdLPKdsAJ5B38rb9oSE=; b=bS4rip0puxztDxjsEI9ufGl3HamUQvEjakm2PzesoLC/HKR0URpk5FGOBgHTZkRjy5 2p1of5ta2IbMZBMp4q1A2UliSiSownF3etGSqP/GV5fi3QQNpvbGMuGukpLlEVlW2EqS c6RjZfsdJ7AJFb8D6I/GzLymyDD3ER/eZ6Rep5l6+BTiLYoDGSxUSLaZzmjRnt35qgZ7 fzp8GpZQ9195QgEcc96SbGk+rP8MS1q+On0K0+KsOrQvMyrh62Hx3elIiXtneje9bQLe WeBXxDiccCKDbekU5owi0iX46h/+F4j7x3mXyac4Ewww5kcfOdB2c6Q+UtHbKRZmdiGt ZN9A== X-Gm-Message-State: APjAAAVe+EM6n5a+L0PEEu/hbWYwCbBxBi++VqsYGW/3QHQrCWAlo9xA 5L2qeieARQ2bFxp1q40EboL15LskrIo= X-Google-Smtp-Source: APXvYqzv2FK6+3Q1hB3Dc8DQEZszPef77pHye/gOJyFy6eYModzp2LTMBowX/ViS/RS1Kebhhwz+Ag== X-Received: by 2002:a63:5b4b:: with SMTP id l11mr42363871pgm.82.1553814258940; Thu, 28 Mar 2019 16:04:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:34 -1000 Message-Id: <20190328230404.12909-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.1 v2 06/36] cpu: Replace ENV_GET_CPU with env_cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Acked-by: Alistair Francis Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- accel/tcg/atomic_template.h | 8 +-- accel/tcg/softmmu_template.h | 20 ++++---- include/exec/cpu-all.h | 12 +++++ include/exec/cpu_ldst_template.h | 6 +-- include/exec/cpu_ldst_useronly_template.h | 6 +-- include/exec/softmmu-semi.h | 16 +++--- linux-user/cpu_loop-common.h | 2 +- target/alpha/cpu.h | 2 - target/arm/cpu.h | 2 - target/cris/cpu.h | 2 - target/hppa/cpu.h | 1 - target/i386/cpu.h | 2 - target/lm32/cpu.h | 2 - target/m68k/cpu.h | 2 - target/microblaze/cpu.h | 2 - target/mips/cpu.h | 2 - target/moxie/cpu.h | 2 - target/nios2/cpu.h | 2 - target/openrisc/cpu.h | 2 - target/ppc/cpu.h | 2 - target/riscv/cpu.h | 1 - target/s390x/cpu.h | 2 - target/sh4/cpu.h | 2 - target/sparc/cpu.h | 2 - target/tilegx/cpu.h | 2 - target/tricore/cpu.h | 2 - target/unicore32/cpu.h | 2 - target/xtensa/cpu.h | 2 - accel/tcg/cputlb.c | 22 ++++----- accel/tcg/tcg-runtime.c | 4 +- accel/tcg/translate-all.c | 2 +- accel/tcg/user-exec.c | 2 +- bsd-user/syscall.c | 6 +-- linux-user/arm/cpu_loop.c | 2 +- linux-user/cris/cpu_loop.c | 2 +- linux-user/elfload.c | 6 +-- linux-user/m68k/cpu_loop.c | 2 +- linux-user/main.c | 2 +- linux-user/mips/cpu_loop.c | 2 +- linux-user/nios2/cpu_loop.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- linux-user/signal.c | 8 +-- linux-user/syscall.c | 18 +++---- linux-user/uname.c | 2 +- target/arm/helper.c | 42 ++++++++-------- target/hppa/op_helper.c | 2 +- target/i386/hax-all.c | 6 +-- target/i386/hvf/x86_decode.c | 22 ++++----- target/i386/hvf/x86_emu.c | 60 +++++++++++++---------- target/i386/mem_helper.c | 4 +- target/m68k/op_helper.c | 2 +- target/nios2/mmu.c | 4 +- target/nios2/op_helper.c | 2 +- target/ppc/mmu_helper.c | 2 +- target/s390x/gdbstub.c | 24 ++++----- target/s390x/mem_helper.c | 2 +- target/sh4/op_helper.c | 2 +- docs/devel/tracing.txt | 4 +- scripts/tracetool/format/tcg_helper_c.py | 2 +- 59 files changed, 176 insertions(+), 198 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 685602b076..5aaf186253 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -62,21 +62,21 @@ #define ATOMIC_TRACE_RMW do { \ uint8_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, fal= se); \ \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, \ + trace_guest_mem_before_exec(env_cpu(env), addr, info); \ + trace_guest_mem_before_exec(env_cpu(env), addr, \ info | TRACE_MEM_ST); \ } while (0) =20 #define ATOMIC_TRACE_LD do { \ uint8_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, fal= se); \ \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \ + trace_guest_mem_before_exec(env_cpu(env), addr, info); \ } while (0) =20 # define ATOMIC_TRACE_ST do { \ uint8_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, tru= e); \ \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \ + trace_guest_mem_before_exec(env_cpu(env), addr, info); \ } while (0) =20 /* Define host-endian atomic operations. Note that END is used within diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h index fc6371aed1..efd4d4e743 100644 --- a/accel/tcg/softmmu_template.h +++ b/accel/tcg/softmmu_template.h @@ -120,14 +120,14 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target= _ulong addr, DATA_TYPE res; =20 if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, + cpu_unaligned_access(env_cpu(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } =20 /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, + tlb_fill(env_cpu(env), addr, DATA_SIZE, READ_ACCESS_TYPE, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); @@ -191,14 +191,14 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target= _ulong addr, DATA_TYPE res; =20 if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, + cpu_unaligned_access(env_cpu(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } =20 /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, + tlb_fill(env_cpu(env), addr, DATA_SIZE, READ_ACCESS_TYPE, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); @@ -289,14 +289,14 @@ void helper_le_st_name(CPUArchState *env, target_ulon= g addr, DATA_TYPE val, uintptr_t haddr; =20 if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); } =20 /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); @@ -333,7 +333,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, entry2 =3D tlb_entry(env, mmu_idx, page2); if (!tlb_hit_page(tlb_addr_write(entry2), page2) && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, + tlb_fill(env_cpu(env), page2, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); } =20 @@ -369,14 +369,14 @@ void helper_be_st_name(CPUArchState *env, target_ulon= g addr, DATA_TYPE val, uintptr_t haddr; =20 if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); } =20 /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); @@ -413,7 +413,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, entry2 =3D tlb_entry(env, mmu_idx, page2); if (!tlb_hit_page(tlb_addr_write(entry2), page2) && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, + tlb_fill(env_cpu(env), page2, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); } =20 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b16c9ec513..9fb3f57684 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -371,4 +371,16 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong ad= dr, =20 int cpu_exec(CPUState *cpu); =20 +/** + * env_cpu(env) + * @env: The architecture environment + * + * Return the CPUState associated with the environment. + */ +static inline CPUState *env_cpu(CPUArchState *env) +{ + ArchCPU *arch_cpu =3D container_of(env, ArchCPU, env); + return &arch_cpu->parent_obj; +} + #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_templ= ate.h index 0f061d47ef..af7e0b49f2 100644 --- a/include/exec/cpu_ldst_template.h +++ b/include/exec/cpu_ldst_template.h @@ -89,7 +89,7 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArch= State *env, =20 #if !defined(SOFTMMU_CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, false)); #endif =20 @@ -128,7 +128,7 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUAr= chState *env, =20 #if !defined(SOFTMMU_CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, true, MO_TE, false)); #endif =20 @@ -170,7 +170,7 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArc= hState *env, =20 #if !defined(SOFTMMU_CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, true)); #endif =20 diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_l= dst_useronly_template.h index 0fd6019af0..bc45e2b8d4 100644 --- a/include/exec/cpu_ldst_useronly_template.h +++ b/include/exec/cpu_ldst_useronly_template.h @@ -66,7 +66,7 @@ glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env,= abi_ptr ptr) { #if !defined(CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, false)); #endif return glue(glue(ld, USUFFIX), _p)(g2h(ptr)); @@ -90,7 +90,7 @@ glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env,= abi_ptr ptr) { #if !defined(CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, true, MO_TE, false)); #endif return glue(glue(lds, SUFFIX), _p)(g2h(ptr)); @@ -116,7 +116,7 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env= , abi_ptr ptr, { #if !defined(CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, true)); #endif glue(glue(st, SUFFIX), _p)(g2h(ptr), v); diff --git a/include/exec/softmmu-semi.h b/include/exec/softmmu-semi.h index 7eefad8f39..970837992e 100644 --- a/include/exec/softmmu-semi.h +++ b/include/exec/softmmu-semi.h @@ -14,7 +14,7 @@ static inline uint64_t softmmu_tget64(CPUArchState *env, = target_ulong addr) { uint64_t val; =20 - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 0); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 8, 0); return tswap64(val); } =20 @@ -22,7 +22,7 @@ static inline uint32_t softmmu_tget32(CPUArchState *env, = target_ulong addr) { uint32_t val; =20 - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 4, 0); return tswap32(val); } =20 @@ -30,7 +30,7 @@ static inline uint32_t softmmu_tget8(CPUArchState *env, t= arget_ulong addr) { uint8_t val; =20 - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, 0); + cpu_memory_rw_debug(env_cpu(env), addr, &val, 1, 0); return val; } =20 @@ -43,14 +43,14 @@ static inline void softmmu_tput64(CPUArchState *env, target_ulong addr, uint64_t val) { val =3D tswap64(val); - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 1); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 8, 1); } =20 static inline void softmmu_tput32(CPUArchState *env, target_ulong addr, uint32_t val) { val =3D tswap32(val); - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 4, 1); } #define put_user_u64(arg, p) ({ softmmu_tput64(env, p, arg) ; 0; }) #define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; }) @@ -63,7 +63,7 @@ static void *softmmu_lock_user(CPUArchState *env, /* TODO: Make this something that isn't fixed size. */ p =3D malloc(len); if (p && copy) { - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 0); + cpu_memory_rw_debug(env_cpu(env), addr, p, len, 0); } return p; } @@ -79,7 +79,7 @@ static char *softmmu_lock_user_string(CPUArchState *env, = target_ulong addr) return NULL; } do { - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, 0); + cpu_memory_rw_debug(env_cpu(env), addr, &c, 1, 0); addr++; *(p++) =3D c; } while (c); @@ -90,7 +90,7 @@ static void softmmu_unlock_user(CPUArchState *env, void *= p, target_ulong addr, target_ulong len) { if (len) { - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 1); + cpu_memory_rw_debug(env_cpu(env), addr, p, len, 1); } free(p); } diff --git a/linux-user/cpu_loop-common.h b/linux-user/cpu_loop-common.h index ffe3fe9ad5..cb98494ecb 100644 --- a/linux-user/cpu_loop-common.h +++ b/linux-user/cpu_loop-common.h @@ -24,7 +24,7 @@ =20 #define EXCP_DUMP(env, fmt, ...) \ do { \ - CPUState *cs =3D ENV_GET_CPU(env); \ + CPUState *cs =3D env_cpu(env); \ fprintf(stderr, fmt , ## __VA_ARGS__); \ cpu_dump_state(cs, stderr, fprintf, 0); \ if (qemu_log_separate()) { \ diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 6629b869d2..788edd5cb3 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -278,8 +278,6 @@ static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState= *env) return container_of(env, AlphaCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(alpha_env_get_cpu(e)) - #define ENV_OFFSET offsetof(AlphaCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 30776ce15f..b6bd34f5b5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -912,8 +912,6 @@ void arm_cpu_post_init(Object *obj); =20 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); =20 -#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) - #define ENV_OFFSET offsetof(ARMCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/cris/cpu.h b/target/cris/cpu.h index bcd17bf88b..632ebf84b0 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -188,8 +188,6 @@ static inline CRISCPU *cris_env_get_cpu(CPUCRISState *e= nv) return container_of(env, CRISCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e)) - #define ENV_OFFSET offsetof(CRISCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f90b11dd0b..6ae73e24e4 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -227,7 +227,6 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *e= nv) return container_of(env, HPPACPU, env); } =20 -#define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e)) #define ENV_OFFSET offsetof(HPPACPU, env) =20 typedef CPUHPPAState CPUArchState; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index bb1464d451..450842185a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1482,8 +1482,6 @@ static inline X86CPU *x86_env_get_cpu(CPUX86State *en= v) return container_of(env, X86CPU, env); } =20 -#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) - #define ENV_OFFSET offsetof(X86CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 5eef4ccfc5..258f2b4266 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -200,8 +200,6 @@ static inline LM32CPU *lm32_env_get_cpu(CPULM32State *e= nv) return container_of(env, LM32CPU, env); } =20 -#define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e)) - #define ENV_OFFSET offsetof(LM32CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 5db18909cc..b216be33b4 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -168,8 +168,6 @@ static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *e= nv) return container_of(env, M68kCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) - #define ENV_OFFSET offsetof(M68kCPU, env) =20 void m68k_cpu_do_interrupt(CPUState *cpu); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d7c1846e49..3ca5d21451 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -315,8 +315,6 @@ static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState = *env) return container_of(env, MicroBlazeCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e)) - #define ENV_OFFSET offsetof(MicroBlazeCPU, env) =20 void mb_cpu_do_interrupt(CPUState *cs); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 8c5a40b5ad..e7ad81becb 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1056,8 +1056,6 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState = *env) return container_of(env, MIPSCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) - #define ENV_OFFSET offsetof(MIPSCPU, env) =20 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 4bc5e07af9..c050d6e15d 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -95,8 +95,6 @@ static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *= env) return container_of(env, MoxieCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(moxie_env_get_cpu(e)) - #define ENV_OFFSET offsetof(MoxieCPU, env) =20 void moxie_cpu_do_interrupt(CPUState *cs); diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 272ab10e67..e0e12a910e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -198,8 +198,6 @@ static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State= *env) return NIOS2_CPU(container_of(env, Nios2CPU, env)); } =20 -#define ENV_GET_CPU(e) CPU(nios2_env_get_cpu(e)) - #define ENV_OFFSET offsetof(Nios2CPU, env) =20 void nios2_tcg_init(void); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 20ea1ca973..3eda7957cf 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -322,8 +322,6 @@ static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpen= RISCState *env) return container_of(env, OpenRISCCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e)) - #define ENV_OFFSET offsetof(OpenRISCCPU, env) =20 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c5ea29a949..a5d44d1b1f 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1196,8 +1196,6 @@ static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState= *env) return container_of(env, PowerPCCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e)) - #define ENV_OFFSET offsetof(PowerPCCPU, env) =20 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1fdac0c8d5..e97f6c4889 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -234,7 +234,6 @@ extern const char * const riscv_fpr_regnames[]; extern const char * const riscv_excp_names[]; extern const char * const riscv_intr_names[]; =20 -#define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e)) #define ENV_OFFSET offsetof(RISCVCPU, env) =20 void riscv_cpu_do_interrupt(CPUState *cpu); diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 762184c62d..3dd60c5346 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -168,8 +168,6 @@ static inline S390CPU *s390_env_get_cpu(CPUS390XState *= env) return container_of(env, S390CPU, env); } =20 -#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e)) - #define ENV_OFFSET offsetof(S390CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 926cf63825..95094a517a 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -212,8 +212,6 @@ static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *en= v) return container_of(env, SuperHCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e)) - #define ENV_OFFSET offsetof(SuperHCPU, env) =20 void superh_cpu_do_interrupt(CPUState *cpu); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 55c0004887..77dec0d865 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -537,8 +537,6 @@ static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState= *env) return container_of(env, SPARCCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e)) - #define ENV_OFFSET offsetof(SPARCCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 042a7a0c71..135df63523 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -143,8 +143,6 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState= *env) return container_of(env, TileGXCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e)) - #define ENV_OFFSET offsetof(TileGXCPU, env) =20 /* TILE-Gx memory attributes */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index dc4bcea955..ed32622388 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -213,8 +213,6 @@ static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCor= eState *env) return TRICORE_CPU(container_of(env, TriCoreCPU, env)); } =20 -#define ENV_GET_CPU(e) CPU(tricore_env_get_cpu(e)) - #define ENV_OFFSET offsetof(TriCoreCPU, env) =20 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 968154e6fa..162e33257d 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -81,8 +81,6 @@ static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32= State *env) return container_of(env, UniCore32CPU, env); } =20 -#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e)) - #define ENV_OFFSET offsetof(UniCore32CPU, env) =20 void uc32_cpu_do_interrupt(CPUState *cpu); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 6f9721bc28..e6f57e0b64 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -534,8 +534,6 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXt= ensaState *env) return container_of(env, XtensaCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e)) - #define ENV_OFFSET offsetof(XtensaCPU, env) =20 =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c28b6b6328..abc6cbf27e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -415,7 +415,7 @@ static inline void tlb_flush_vtlb_page_locked(CPUArchSt= ate *env, int mmu_idx, CPUTLBDesc *d =3D &env_tlb(env)->d[mmu_idx]; int k; =20 - assert_cpu_is_self(ENV_GET_CPU(env)); + assert_cpu_is_self(env_cpu(env)); for (k =3D 0; k < CPU_VTLB_SIZE; k++) { if (tlb_flush_entry_locked(&d->vtable[k], page)) { tlb_n_used_entries_dec(env, mmu_idx); @@ -863,7 +863,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, target_ulong addr, uintptr_t retaddr, bool recheck, MMUAccessType access_type, int size) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; MemoryRegionSection *section; MemoryRegion *mr; @@ -931,7 +931,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry = *iotlbentry, uint64_t val, target_ulong addr, uintptr_t retaddr, bool recheck, int size) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; MemoryRegionSection *section; MemoryRegion *mr; @@ -997,7 +997,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mm= u_idx, size_t index, { size_t vidx; =20 - assert_cpu_is_self(ENV_GET_CPU(env)); + assert_cpu_is_self(env_cpu(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb =3D &env_tlb(env)->d[mmu_idx].vtable[vidx]; target_ulong cmp; @@ -1047,7 +1047,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, = target_ulong addr) =20 if (unlikely(!tlb_hit(entry->addr_code, addr))) { if (!VICTIM_TLB_HIT(addr_code, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0= ); + tlb_fill(env_cpu(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); } @@ -1085,7 +1085,7 @@ void probe_write(CPUArchState *env, target_ulong addr= , int size, int mmu_idx, if (!tlb_hit(tlb_addr_write(entry), addr)) { /* TLB entry is for a different page */ if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); } } @@ -1112,7 +1112,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, /* Enforce guest required alignment. */ if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) { /* ??? Maybe indicate atomic op to cpu_unaligned_access */ - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); } =20 @@ -1128,7 +1128,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, /* Check TLB entry and enforce page permissions. */ if (!tlb_hit(tlb_addr, addr)) { if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_STORE, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); tlbe =3D tlb_entry(env, mmu_idx, addr); @@ -1145,7 +1145,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, =20 /* Let the guest notice RMW on a write-only page. */ if (unlikely(tlbe->addr_read !=3D (tlb_addr & ~TLB_NOTDIRTY))) { - tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_LOAD, + tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_LOAD, mmu_idx, retaddr); /* Since we don't support reads and writes to different addresses, and we do have the proper page loaded for write, this shouldn't @@ -1158,7 +1158,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, ndi->active =3D false; if (unlikely(tlb_addr & TLB_NOTDIRTY)) { ndi->active =3D true; - memory_notdirty_write_prepare(ndi, ENV_GET_CPU(env), addr, + memory_notdirty_write_prepare(ndi, env_cpu(env), addr, qemu_ram_addr_from_host_nofail(hosta= ddr), 1 << s_bits); } @@ -1166,7 +1166,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, return hostaddr; =20 stop_the_world: - cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr); + cpu_loop_exit_atomic(env_cpu(env), retaddr); } =20 #ifdef TARGET_WORDS_BIGENDIAN diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index d0d4484406..8a1e408e31 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -146,7 +146,7 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg) =20 void *HELPER(lookup_tb_ptr)(CPUArchState *env) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; @@ -165,5 +165,5 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) =20 void HELPER(exit_atomic)(CPUArchState *env) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC()); + cpu_loop_exit_atomic(env_cpu(env), GETPC()); } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8f593b926f..2cc5d3c59f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1719,7 +1719,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 tcg_func_start(tcg_ctx); =20 - tcg_ctx->cpu =3D ENV_GET_CPU(env); + tcg_ctx->cpu =3D env_cpu(env); gen_intermediate_code(cpu, tb); tcg_ctx->cpu =3D NULL; =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0789984fe6..a6d6b06f30 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -698,7 +698,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, targe= t_ulong addr, { /* Enforce qemu required alignment. */ if (unlikely(addr & (size - 1))) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr); + cpu_loop_exit_atomic(env_cpu(env), retaddr); } helper_retaddr =3D retaddr; return g2h(addr); diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c index 66492aaf5d..1ee6195d9f 100644 --- a/bsd-user/syscall.c +++ b/bsd-user/syscall.c @@ -315,7 +315,7 @@ abi_long do_freebsd_syscall(void *cpu_env, int num, abi= _long arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_long ret; void *p; =20 @@ -413,7 +413,7 @@ abi_long do_netbsd_syscall(void *cpu_env, int num, abi_= long arg1, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_long ret; void *p; =20 @@ -488,7 +488,7 @@ abi_long do_openbsd_syscall(void *cpu_env, int num, abi= _long arg1, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_long ret; void *p; =20 diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index ee68aa60bf..b7e7a6323c 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -423,7 +423,7 @@ void cpu_loop(CPUARMState *env) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; struct image_info *info =3D ts->info; int i; diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index dacf604c7d..d012e70a7a 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -83,7 +83,7 @@ void cpu_loop(CPUCRISState *env) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; struct image_info *info =3D ts->info; =20 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c1a26021f8..a8a89997b1 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -3335,7 +3335,7 @@ static int write_note(struct memelfnote *men, int fd) =20 static void fill_thread_info(struct elf_note_info *info, const CPUArchStat= e *env) { - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)env); + CPUState *cpu =3D env_cpu((CPUArchState *)env); TaskState *ts =3D (TaskState *)cpu->opaque; struct elf_thread_status *ets; =20 @@ -3365,7 +3365,7 @@ static int fill_note_info(struct elf_note_info *info, long signr, const CPUArchState *env) { #define NUMNOTES 3 - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)env); + CPUState *cpu =3D env_cpu((CPUArchState *)env); TaskState *ts =3D (TaskState *)cpu->opaque; int i; =20 @@ -3489,7 +3489,7 @@ static int write_note_info(struct elf_note_info *info= , int fd) */ static int elf_core_dump(int signr, const CPUArchState *env) { - const CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)env); + const CPUState *cpu =3D env_cpu((CPUArchState *)env); const TaskState *ts =3D (const TaskState *)cpu->opaque; struct vm_area_struct *vma =3D NULL; char corefile[PATH_MAX]; diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index bfb41bbcc5..42d8d841ea 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -130,7 +130,7 @@ void cpu_loop(CPUM68KState *env) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; struct image_info *info =3D ts->info; =20 diff --git a/linux-user/main.c b/linux-user/main.c index a0aba9cb1e..01ae581b01 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -176,7 +176,7 @@ void init_task_state(TaskState *ts) =20 CPUArchState *cpu_copy(CPUArchState *env) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); CPUState *new_cpu =3D cpu_create(cpu_type); CPUArchState *new_env =3D new_cpu->env_ptr; CPUBreakpoint *bp; diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 61dc90d51c..828137cd84 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -654,7 +654,7 @@ error: =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; struct image_info *info =3D ts->info; int i; diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 5aa1eca740..9869083fa1 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUNios2State *env) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); Nios2CPU *cpu =3D NIOS2_CPU(cs); target_siginfo_t info; int trapnr, ret; diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index a9bac4ca79..31700f75d0 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -116,7 +116,7 @@ void cpu_loop(CPURISCVState *env) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; struct image_info *info =3D ts->info; =20 diff --git a/linux-user/signal.c b/linux-user/signal.c index e2c0b37173..1b0ae7fce1 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -621,7 +621,7 @@ static void QEMU_NORETURN dump_core_and_abort(int targe= t_sig) int queue_signal(CPUArchState *env, int sig, int si_type, target_siginfo_t *info) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; =20 trace_user_queue_signal(env, sig); @@ -646,7 +646,7 @@ static void host_signal_handler(int host_signum, siginf= o_t *info, void *puc) { CPUArchState *env =3D thread_cpu->env_ptr; - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; =20 int sig; @@ -837,7 +837,7 @@ int do_sigaction(int sig, const struct target_sigaction= *act, static void handle_pending_signal(CPUArchState *cpu_env, int sig, struct emulated_sigtable *k) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_ulong handler; sigset_t set; target_sigset_t target_old_set; @@ -922,7 +922,7 @@ static void handle_pending_signal(CPUArchState *cpu_env= , int sig, =20 void process_pending_signals(CPUArchState *cpu_env) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); int sig; TaskState *ts =3D cpu->opaque; sigset_t set; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 208fd1813d..e2fc01ad6c 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -5439,7 +5439,7 @@ static void *clone_func(void *arg) rcu_register_thread(); tcg_register_thread(); env =3D info->env; - cpu =3D ENV_GET_CPU(env); + cpu =3D env_cpu(env); thread_cpu =3D cpu; ts =3D (TaskState *)cpu->opaque; info->tid =3D gettid(); @@ -5468,7 +5468,7 @@ static int do_fork(CPUArchState *env, unsigned int fl= ags, abi_ulong newsp, abi_ulong parent_tidptr, target_ulong newtls, abi_ulong child_tidptr) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); int ret; TaskState *ts; CPUState *new_cpu; @@ -5501,7 +5501,7 @@ static int do_fork(CPUArchState *env, unsigned int fl= ags, abi_ulong newsp, new_env =3D cpu_copy(env); /* Init regs that differ from the parent. */ cpu_clone_regs(new_env, newsp); - new_cpu =3D ENV_GET_CPU(new_env); + new_cpu =3D env_cpu(new_env); new_cpu->opaque =3D ts; ts->bprm =3D parent_ts->bprm; ts->info =3D parent_ts->info; @@ -6597,7 +6597,7 @@ int host_to_target_waitstatus(int status) =20 static int open_self_cmdline(void *cpu_env, int fd) { - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu =3D env_cpu((CPUArchState *)cpu_env); struct linux_binprm *bprm =3D ((TaskState *)cpu->opaque)->bprm; int i; =20 @@ -6614,7 +6614,7 @@ static int open_self_cmdline(void *cpu_env, int fd) =20 static int open_self_maps(void *cpu_env, int fd) { - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu =3D env_cpu((CPUArchState *)cpu_env); TaskState *ts =3D cpu->opaque; FILE *fp; char *line =3D NULL; @@ -6663,7 +6663,7 @@ static int open_self_maps(void *cpu_env, int fd) =20 static int open_self_stat(void *cpu_env, int fd) { - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu =3D env_cpu((CPUArchState *)cpu_env); TaskState *ts =3D cpu->opaque; abi_ulong start_stack =3D ts->info->start_stack; int i; @@ -6700,7 +6700,7 @@ static int open_self_stat(void *cpu_env, int fd) =20 static int open_self_auxv(void *cpu_env, int fd) { - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu =3D env_cpu((CPUArchState *)cpu_env); TaskState *ts =3D cpu->opaque; abi_ulong auxv =3D ts->info->saved_auxv; abi_ulong len =3D ts->info->auxv_len; @@ -6960,7 +6960,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_long ret; #if defined(TARGET_NR_stat) || defined(TARGET_NR_stat64) \ || defined(TARGET_NR_lstat) || defined(TARGET_NR_lstat64) \ @@ -11599,7 +11599,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_long ret; =20 #ifdef DEBUG_ERESTARTSYS diff --git a/linux-user/uname.c b/linux-user/uname.c index 313b79dbad..54bb7e9278 100644 --- a/linux-user/uname.c +++ b/linux-user/uname.c @@ -54,7 +54,7 @@ const char *cpu_to_uname_machine(void *cpu_env) return "armv5te" utsname_suffix; #elif defined(TARGET_I386) && !defined(TARGET_X86_64) /* see arch/x86/kernel/cpu/bugs.c: check_bugs(), 386, 486, 586, 686 */ - CPUState *cpu =3D ENV_GET_CPU((CPUX86State *)cpu_env); + CPUState *cpu =3D env_cpu((CPUX86State *)cpu_env); int family =3D object_property_get_int(OBJECT(cpu), "family", NULL); if (family =3D=3D 4) { return "i486"; diff --git a/target/arm/helper.c b/target/arm/helper.c index a36f4b3d69..430a769457 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -560,7 +560,7 @@ static void contextidr_write(CPUARMState *env, const AR= MCPRegInfo *ri, static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_all_cpus_synced(cs); } @@ -568,7 +568,7 @@ static void tlbiall_is_write(CPUARMState *env, const AR= MCPRegInfo *ri, static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_all_cpus_synced(cs); } @@ -576,7 +576,7 @@ static void tlbiasid_is_write(CPUARMState *env, const A= RMCPRegInfo *ri, static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); } @@ -584,7 +584,7 @@ static void tlbimva_is_write(CPUARMState *env, const AR= MCPRegInfo *ri, static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); } @@ -659,7 +659,7 @@ static void tlbimvaa_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S12NSE1 | @@ -670,7 +670,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S12NSE1 | @@ -687,7 +687,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARM= CPRegInfo *ri, * translation information. * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. */ - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr; =20 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { @@ -702,7 +702,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARM= CPRegInfo *ri, static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr; =20 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { @@ -718,7 +718,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); } @@ -726,7 +726,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); } @@ -734,7 +734,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); @@ -743,7 +743,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, @@ -1894,7 +1894,7 @@ static void csselr_write(CPUARMState *env, const ARMC= PRegInfo *ri, =20 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); uint64_t ret =3D 0; =20 @@ -3746,7 +3746,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState= *env, static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); bool sec =3D arm_is_secure_below_el3(env); =20 if (sec) { @@ -3763,7 +3763,7 @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *en= v, const ARMCPRegInfo *ri, static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { tlbi_aa64_vmalle1is_write(env, NULL, value); @@ -3834,7 +3834,7 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env,= const ARMCPRegInfo *ri, * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); bool sec =3D arm_is_secure_below_el3(env); bool has_el2 =3D arm_feature(env, ARM_FEATURE_EL2); =20 @@ -3857,7 +3857,7 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); } @@ -3865,7 +3865,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); } @@ -3948,7 +3948,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, @@ -3958,7 +3958,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, @@ -3990,7 +3990,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr; =20 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a55a5dfc02..952e97a7d7 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -77,7 +77,7 @@ static void atomic_store_3(CPUHPPAState *env, target_ulon= g addr, uint32_t val, } #else /* FIXME -- we can do better. */ - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); #endif } =20 diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c index b978a9b821..8634c26180 100644 --- a/target/i386/hax-all.c +++ b/target/i386/hax-all.c @@ -67,7 +67,7 @@ int valid_hax_tunnel_size(uint16_t size) =20 hax_fd hax_vcpu_get_fd(CPUArchState *env) { - struct hax_vcpu_state *vcpu =3D ENV_GET_CPU(env)->hax_vcpu; + struct hax_vcpu_state *vcpu =3D env_cpu(env)->hax_vcpu; if (!vcpu) { return HAX_INVALID_FD; } @@ -409,7 +409,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df= , uint16_t port, =20 static int hax_vcpu_interrupt(CPUArchState *env) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; struct hax_tunnel *ht =3D vcpu->tunnel; =20 @@ -461,7 +461,7 @@ void hax_raise_event(CPUState *cpu) static int hax_vcpu_hax_exec(CPUArchState *env) { int ret =3D 0; - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); X86CPU *x86_cpu =3D X86_CPU(cpu); struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; struct hax_tunnel *ht =3D vcpu->tunnel; diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c index 9ef7d7513f..822fa1866e 100644 --- a/target/i386/hvf/x86_decode.c +++ b/target/i386/hvf/x86_decode.c @@ -75,8 +75,8 @@ static inline uint64_t decode_bytes(CPUX86State *env, str= uct x86_decode *decode, VM_PANIC_EX("%s invalid size %d\n", __func__, size); break; } - target_ulong va =3D linear_rip(ENV_GET_CPU(env), RIP(env)) + decode->= len; - vmx_read_mem(ENV_GET_CPU(env), &val, va, size); + target_ulong va =3D linear_rip(env_cpu(env), RIP(env)) + decode->len; + vmx_read_mem(env_cpu(env), &val, va, size); decode->len +=3D size; =20 return val; @@ -1772,7 +1772,7 @@ void calc_modrm_operand32(CPUX86State *env, struct x8= 6_decode *decode, if (4 =3D=3D decode->modrm.rm) { ptr +=3D get_sib_val(env, decode, &seg); } else if (!decode->modrm.mod && 5 =3D=3D decode->modrm.rm) { - if (x86_is_long_mode(ENV_GET_CPU(env))) { + if (x86_is_long_mode(env_cpu(env))) { ptr +=3D RIP(env) + decode->len; } else { ptr =3D decode->displacement; @@ -1877,7 +1877,7 @@ static void decode_prefix(CPUX86State *env, struct x8= 6_decode *decode) decode->addr_size_override =3D byte; break; case PREFIX_REX ... (PREFIX_REX + 0xf): - if (x86_is_long_mode(ENV_GET_CPU(env))) { + if (x86_is_long_mode(env_cpu(env))) { decode->rex.rex =3D byte; break; } @@ -1892,16 +1892,16 @@ static void decode_prefix(CPUX86State *env, struct = x86_decode *decode) void set_addressing_size(CPUX86State *env, struct x86_decode *decode) { decode->addressing_size =3D -1; - if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) { + if (x86_is_real(env_cpu(env)) || x86_is_v8086(env_cpu(env))) { if (decode->addr_size_override) { decode->addressing_size =3D 4; } else { decode->addressing_size =3D 2; } - } else if (!x86_is_long_mode(ENV_GET_CPU(env))) { + } else if (!x86_is_long_mode(env_cpu(env))) { /* protected */ struct vmx_segment cs; - vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS); + vmx_read_segment_descriptor(env_cpu(env), &cs, R_CS); /* check db */ if ((cs.ar >> 14) & 1) { if (decode->addr_size_override) { @@ -1929,16 +1929,16 @@ void set_addressing_size(CPUX86State *env, struct x= 86_decode *decode) void set_operand_size(CPUX86State *env, struct x86_decode *decode) { decode->operand_size =3D -1; - if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) { + if (x86_is_real(env_cpu(env)) || x86_is_v8086(env_cpu(env))) { if (decode->op_size_override) { decode->operand_size =3D 4; } else { decode->operand_size =3D 2; } - } else if (!x86_is_long_mode(ENV_GET_CPU(env))) { + } else if (!x86_is_long_mode(env_cpu(env))) { /* protected */ struct vmx_segment cs; - vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS); + vmx_read_segment_descriptor(env_cpu(env), &cs, R_CS); /* check db */ if ((cs.ar >> 14) & 1) { if (decode->op_size_override) { @@ -2188,5 +2188,5 @@ target_ulong decode_linear_addr(CPUX86State *env, str= uct x86_decode *decode, default: break; } - return linear_addr_size(ENV_GET_CPU(env), addr, decode->addressing_siz= e, seg); + return linear_addr_size(env_cpu(env), addr, decode->addressing_size, s= eg); } diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 3ea18edc68..1b04bd7e94 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -182,12 +182,12 @@ void write_val_ext(struct CPUX86State *env, target_ul= ong ptr, target_ulong val, write_val_to_reg(ptr, val, size); return; } - vmx_write_mem(ENV_GET_CPU(env), ptr, &val, size); + vmx_write_mem(env_cpu(env), ptr, &val, size); } =20 uint8_t *read_mmio(struct CPUX86State *env, target_ulong ptr, int bytes) { - vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, ptr, bytes); + vmx_read_mem(env_cpu(env), env->hvf_emul->mmio_buf, ptr, bytes); return env->hvf_emul->mmio_buf; } =20 @@ -399,17 +399,18 @@ static void exec_out(struct CPUX86State *env, struct = x86_decode *decode) { switch (decode->opcode[0]) { case 0xe6: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &AL(env), 1, 1,= 1); + hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 1, 1, 1); break; case 0xe7: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &RAX(env), 1, + hvf_handle_io(env_cpu(env), decode->op[0].val, &RAX(env), 1, decode->operand_size, 1); break; case 0xee: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &AL(env), 1, 1, 1); + hvf_handle_io(env_cpu(env), DX(env), &AL(env), 1, 1, 1); break; case 0xef: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &RAX(env), 1, decode->ope= rand_size, 1); + hvf_handle_io(env_cpu(env), DX(env), &RAX(env), 1, + decode->operand_size, 1); break; default: VM_PANIC("Bad out opcode\n"); @@ -423,10 +424,11 @@ static void exec_in(struct CPUX86State *env, struct x= 86_decode *decode) target_ulong val =3D 0; switch (decode->opcode[0]) { case 0xe4: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &AL(env), 0, 1,= 1); + hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 0, 1, 1); break; case 0xe5: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &val, 0, decode= ->operand_size, 1); + hvf_handle_io(env_cpu(env), decode->op[0].val, &val, 0, + decode->operand_size, 1); if (decode->operand_size =3D=3D 2) { AX(env) =3D val; } else { @@ -434,10 +436,10 @@ static void exec_in(struct CPUX86State *env, struct x= 86_decode *decode) } break; case 0xec: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &AL(env), 0, 1, 1); + hvf_handle_io(env_cpu(env), DX(env), &AL(env), 0, 1, 1); break; case 0xed: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &val, 0, decode->operand_= size, 1); + hvf_handle_io(env_cpu(env), DX(env), &val, 0, decode->operand_size= , 1); if (decode->operand_size =3D=3D 2) { AX(env) =3D val; } else { @@ -484,12 +486,13 @@ static inline void string_rep(struct CPUX86State *env= , struct x86_decode *decode =20 static void exec_ins_single(struct CPUX86State *env, struct x86_decode *de= code) { - target_ulong addr =3D linear_addr_size(ENV_GET_CPU(env), RDI(env), dec= ode->addressing_size, - R_ES); + target_ulong addr =3D linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); =20 - hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 0, + hvf_handle_io(env_cpu(env), DX(env), env->hvf_emul->mmio_buf, 0, decode->operand_size, 1); - vmx_write_mem(ENV_GET_CPU(env), addr, env->hvf_emul->mmio_buf, decode-= >operand_size); + vmx_write_mem(env_cpu(env), addr, env->hvf_emul->mmio_buf, + decode->operand_size); =20 string_increment_reg(env, R_EDI, decode); } @@ -509,8 +512,9 @@ static void exec_outs_single(struct CPUX86State *env, s= truct x86_decode *decode) { target_ulong addr =3D decode_linear_addr(env, decode, RSI(env), R_DS); =20 - vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, addr, decode->= operand_size); - hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 1, + vmx_read_mem(env_cpu(env), env->hvf_emul->mmio_buf, addr, + decode->operand_size); + hvf_handle_io(env_cpu(env), DX(env), env->hvf_emul->mmio_buf, 1, decode->operand_size, 1); =20 string_increment_reg(env, R_ESI, decode); @@ -534,8 +538,8 @@ static void exec_movs_single(struct CPUX86State *env, s= truct x86_decode *decode) target_ulong val; =20 src_addr =3D decode_linear_addr(env, decode, RSI(env), R_DS); - dst_addr =3D linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addr= essing_size, - R_ES); + dst_addr =3D linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); =20 val =3D read_val_ext(env, src_addr, decode->operand_size); write_val_ext(env, dst_addr, val, decode->operand_size); @@ -561,8 +565,8 @@ static void exec_cmps_single(struct CPUX86State *env, s= truct x86_decode *decode) target_ulong dst_addr; =20 src_addr =3D decode_linear_addr(env, decode, RSI(env), R_DS); - dst_addr =3D linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addr= essing_size, - R_ES); + dst_addr =3D linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); =20 decode->op[0].type =3D X86_VAR_IMMEDIATE; decode->op[0].val =3D read_val_ext(env, src_addr, decode->operand_size= ); @@ -591,9 +595,10 @@ static void exec_stos_single(struct CPUX86State *env, = struct x86_decode *decode) target_ulong addr; target_ulong val; =20 - addr =3D linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressi= ng_size, R_ES); + addr =3D linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); val =3D read_reg(env, R_EAX, decode->operand_size); - vmx_write_mem(ENV_GET_CPU(env), addr, &val, decode->operand_size); + vmx_write_mem(env_cpu(env), addr, &val, decode->operand_size); =20 string_increment_reg(env, R_EDI, decode); } @@ -614,9 +619,10 @@ static void exec_scas_single(struct CPUX86State *env, = struct x86_decode *decode) { target_ulong addr; =20 - addr =3D linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressi= ng_size, R_ES); + addr =3D linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); decode->op[1].type =3D X86_VAR_IMMEDIATE; - vmx_read_mem(ENV_GET_CPU(env), &decode->op[1].val, addr, decode->opera= nd_size); + vmx_read_mem(env_cpu(env), &decode->op[1].val, addr, decode->operand_s= ize); =20 EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false); string_increment_reg(env, R_EDI, decode); @@ -641,7 +647,7 @@ static void exec_lods_single(struct CPUX86State *env, s= truct x86_decode *decode) target_ulong val =3D 0; =20 addr =3D decode_linear_addr(env, decode, RSI(env), R_DS); - vmx_read_mem(ENV_GET_CPU(env), &val, addr, decode->operand_size); + vmx_read_mem(env_cpu(env), &val, addr, decode->operand_size); write_reg(env, R_EAX, val, decode->operand_size); =20 string_increment_reg(env, R_ESI, decode); @@ -753,7 +759,7 @@ void simulate_rdmsr(struct CPUState *cpu) =20 static void exec_rdmsr(struct CPUX86State *env, struct x86_decode *decode) { - simulate_rdmsr(ENV_GET_CPU(env)); + simulate_rdmsr(env_cpu(env)); RIP(env) +=3D decode->len; } =20 @@ -851,7 +857,7 @@ void simulate_wrmsr(struct CPUState *cpu) =20 static void exec_wrmsr(struct CPUX86State *env, struct x86_decode *decode) { - simulate_wrmsr(ENV_GET_CPU(env)); + simulate_wrmsr(env_cpu(env)); RIP(env) +=3D decode->len; } =20 diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c index 6cc53bcb40..ae2b2fb4f4 100644 --- a/target/i386/mem_helper.c +++ b/target/i386/mem_helper.c @@ -89,7 +89,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) } CC_SRC =3D eflags; #else - cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC()); + cpu_loop_exit_atomic(env_cpu(env), GETPC()); #endif /* CONFIG_ATOMIC64 */ } =20 @@ -158,7 +158,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a= 0) } CC_SRC =3D eflags; } else { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); } } #endif diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 76f439985a..13fcaa74ef 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -800,7 +800,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, = uint32_t a1, uint32_t a2, #endif { /* Tell the main loop we need to serialize this insn. */ - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); } } else { /* We're executing in a serial context -- no need to be atomic. */ diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 69b71cba4a..0752699e25 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -113,7 +113,7 @@ unsigned int mmu_translate(CPUNios2State *env, =20 static void mmu_flush_pid(CPUNios2State *env, uint32_t pid) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); Nios2CPU *cpu =3D nios2_env_get_cpu(env); int idx; MMU_LOG(qemu_log("TLB Flush PID %d\n", pid)); @@ -137,7 +137,7 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t = pid) =20 void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); Nios2CPU *cpu =3D nios2_env_get_cpu(env); =20 MMU_LOG(qemu_log("mmu_write %08X =3D %08X\n", rn, v)); diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 529ec6ac0e..a60730faac 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -46,7 +46,7 @@ void helper_check_interrupts(CPUNios2State *env) =20 void helper_raise_exception(CPUNios2State *env, uint32_t index) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); cs->exception_index =3D index; cpu_loop_exit(cs); } diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 4a6be4d63b..2e8ffd7aaf 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -517,7 +517,7 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env,= mmu_ctx_t *ctx, ret =3D ppc6xx_tlb_check(env, ctx, eaddr, rw, type); #if defined(DUMP_PAGE_TABLES) if (qemu_loglevel_mask(CPU_LOG_MMU)) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); hwaddr curaddr; uint32_t a0, a1, a2, a3; =20 diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index df147596ce..1e6d99287b 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -96,7 +96,7 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *= mem_buf, int n) switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: env->aregs[n] =3D ldl_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 4; default: return 0; @@ -201,9 +201,9 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t = *mem_buf, int n) case S390_C0_REGNUM ... S390_C15_REGNUM: env->cregs[n] =3D ldtul_p(mem_buf); if (tcg_enabled()) { - tlb_flush(ENV_GET_CPU(env)); + tlb_flush(env_cpu(env)); } - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; default: return 0; @@ -251,35 +251,35 @@ static int cpu_write_virt_reg(CPUS390XState *env, uin= t8_t *mem_buf, int n) switch (n) { case S390_VIRT_CKC_REGNUM: env->ckc =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_CPUTM_REGNUM: env->cputm =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_BEA_REGNUM: env->gbea =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PREFIX_REGNUM: env->psa =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PP_REGNUM: env->pp =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PFT_REGNUM: env->pfault_token =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PFS_REGNUM: env->pfault_select =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PFC_REGNUM: env->pfault_compare =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; default: return 0; @@ -303,7 +303,7 @@ static int cpu_read_gs_reg(CPUS390XState *env, uint8_t = *mem_buf, int n) static int cpu_write_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n) { env->gscb[n] =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; } =20 diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 3f76a8abfd..e2992deb2f 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1477,7 +1477,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, #endif if ((HAVE_CMPXCHG128 ? 0 : fc + 2 > max) || (HAVE_ATOMIC128 ? 0 : sc > max)) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); } } =20 diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 4f825bae5a..12fba6fc78 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -119,7 +119,7 @@ void helper_trapa(CPUSH4State *env, uint32_t tra) void helper_exclusive(CPUSH4State *env) { /* We do not want cpu_restore_state to run. */ - cpu_loop_exit_atomic(ENV_GET_CPU(env), 0); + cpu_loop_exit_atomic(env_cpu(env), 0); } =20 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value) diff --git a/docs/devel/tracing.txt b/docs/devel/tracing.txt index 056aa56496..76e492a489 100644 --- a/docs/devel/tracing.txt +++ b/docs/devel/tracing.txt @@ -434,9 +434,9 @@ Can be used as: /* trace emitted at this point */ trace_foo(0xd1); /* trace emitted at this point */ - trace_bar(ENV_GET_CPU(env), 0xd2); + trace_bar(env_cpu(env), 0xd2); /* trace emitted at this point (env) and when guest code is execut= ed (cpu_env) */ - trace_baz_tcg(ENV_GET_CPU(env), cpu_env, 0xd3); + trace_baz_tcg(env_cpu(env), cpu_env, 0xd3); } =20 If the translating vCPU has address 0xc1 and code is later executed by vCPU diff --git a/scripts/tracetool/format/tcg_helper_c.py b/scripts/tracetool/f= ormat/tcg_helper_c.py index bbbd6ad0f4..79aa63eada 100644 --- a/scripts/tracetool/format/tcg_helper_c.py +++ b/scripts/tracetool/format/tcg_helper_c.py @@ -25,7 +25,7 @@ def vcpu_transform_args(args, mode): if mode =3D=3D "code": return Arguments([ # Does cast from helper requirements to tracing types - ("CPUState *", "ENV_GET_CPU(%s)" % args.names()[0]), + ("CPUState *", "env_cpu(%s)" % args.names()[0]), ]) else: args =3D Arguments([ --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553815756518988.2880821461489; Thu, 28 Mar 2019 16:29:16 -0700 (PDT) Received: from localhost ([127.0.0.1]:43276 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eSR-0000pE-Bc for importer@patchew.org; Thu, 28 Mar 2019 19:29:15 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42458) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKv-0001my-HM for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4M-0002yY-3U for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:22 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:44642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4L-0002y6-Kn for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:22 -0400 Received: by mail-pf1-x443.google.com with SMTP id y13so70213pfm.11 for ; Thu, 28 Mar 2019 16:04:21 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. [66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.19 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=pboOW5h3NGyyKEYef8MP27p99BzWuQLk4PmNbUbBl30=; b=WpYz0vxqQD/HcNkRJEGiIP0pOozpORh21Fiym7K9d6PvV1a+n+sYG0/+1IktkZgthL 7v3Ew12Goc7iAx9kr8Gi6dN1F77wyE/HNPFKtasNd77NUB2ff+j0fuA+yB32VY/1eW2z W3FIBzuJP43XlnasneVrWA4S+pn2XB6bAkU2wbZ1PWL7bPt689J28nFYSgH3oxP2cbH4 g8J9nbnYe9wifdwsc5Fu8zBjI3tYHDiqfY+l+bltUdQHufMMH67LTQRDnpCufTa2Iz/A XnK2PhIsZUUeWfgcdE/9GZIU3BBql3lJ4+DHwDVUNl1IYvFHOrKrvVrz306qs8cLgyDN 0rwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=pboOW5h3NGyyKEYef8MP27p99BzWuQLk4PmNbUbBl30=; b=U+Jps2z7spxDs6s0a/HIQz16EUApxdAMuQTA8AOFfn4Fn4x/becJNC/b2Y0123ZS+f duQ8P+FWYsQ5BENDlveGKxo24o/QXWyf5Mjk3MpDlJ5H3C95M9QrZhjh6Yq+/Z+DM+0H pdUGNi8MSmE0U+PquP8FzJp+ljbG7EVt6kBGcPH1jniIdSo27GQZPDp9cOWIJP+z0Omw OolT+S18o5SU0/Xu5+MmDG1yYILSHKrWCIUJ124jDMVaZxpkAZ4ArayciR4qBk5HdFSt HDycliI+HYtH2MLvmjyHBuD/WOL/erRZqC6MAHlpoBySGh66BMrOm/aDfFWFTXHxFbXM 7orQ== X-Gm-Message-State: APjAAAUqsudIgLQQBPqSUN5AfIOCfhw/xHWEtFpG4B12+Yxuw1fvG/Hp 08goE2sZ09KQh/oT5wJIHwtIcA5rYVE= X-Google-Smtp-Source: APXvYqyAHCpavTn+nQ8rTykhDe6YVcYtU7Wno/NwCdyqRaFVTLqOxg/TU0TqDF2qyDV1zqcADCaBOg== X-Received: by 2002:a65:4549:: with SMTP id x9mr43639392pgr.3.1553814260414; Thu, 28 Mar 2019 16:04:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:35 -1000 Message-Id: <20190328230404.12909-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.1 v2 07/36] cpu: Introduce env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will foo_env_get_cpu with a generic definition. No changes to the target specific code so far. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/exec/cpu-all.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 9fb3f57684..0951fd9053 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -371,6 +371,17 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong ad= dr, =20 int cpu_exec(CPUState *cpu); =20 +/** + * env_archcpu(env) + * @env: The architecture environment + * + * Return the ArchCPU associated with the environment. + */ +static inline ArchCPU *env_archcpu(CPUArchState *env) +{ + return container_of(env, ArchCPU, env); +} + /** * env_cpu(env) * @env: The architecture environment @@ -379,8 +390,7 @@ int cpu_exec(CPUState *cpu); */ static inline CPUState *env_cpu(CPUArchState *env) { - ArchCPU *arch_cpu =3D container_of(env, ArchCPU, env); - return &arch_cpu->parent_obj; + return &env_archcpu(env)->parent_obj; } =20 #endif /* CPU_ALL_H */ --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553815422535484.5270572107381; Thu, 28 Mar 2019 16:23:42 -0700 (PDT) Received: from localhost ([127.0.0.1]:43192 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eN3-0003IV-BP for importer@patchew.org; Thu, 28 Mar 2019 19:23:41 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKv-0001km-Ew for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4N-0002za-U6 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:25 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:40536) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4N-0002yy-NH for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:23 -0400 Received: by mail-pg1-x541.google.com with SMTP id u9so225816pgo.7 for ; Thu, 28 Mar 2019 16:04:23 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. [66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=Css6NKgFH171QC6SSk07lpmy2ZqpsnjuUU/ll24a9MA=; b=i4vPpYXWWtjFqgwtTbVG/QMC+0h8zIima4xpD1fHckDmkcqgkZK2JYExxt29Cm8zdY Fb7LxZN4cfCedKff88BbZSUKEQSP0DQJNf25SJuTh5xUGmnKbyNIQbPq5WMCSuq+z91T zxwcwyL4kLjxi8IWNusDbLYucXI0319854bfUPMVJ2Cs01Y+UwAoVgfkQDPK65O8B8jS vohyaTnlvh+m+S6aBeuOKm6+1xK48iL/6dxYvJKhjFDI3W9P8esHW2oa8Z8j1VfEYlMl uHNKMBdplFFYvFUlohdtOU1LrWBEuGgxlbMvBPKXFm2DO2e8I3xdGuR9BztQyqWUXJV1 PMrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Css6NKgFH171QC6SSk07lpmy2ZqpsnjuUU/ll24a9MA=; b=mIB3GVmP1Kg/mQGZoRLjGbkHGTjXupe1nnSz5SDW9Twd4fTASQnIPrYuHX6ajDAu7V w1vpGpsHmkRwlgei5NiRggWfqrXwR39ykwJS0cSx8tWixcHfZ0tckhG4XvVfizL9sHQ0 PbB4YXXp+hmiIOO/+A2G6ExPmiYRBzN3Bu/jWcOtyFKDl65ULqghvBN3V3pV11eIrwCO pXZ5DBe9jdEllwoiX/LEZYDFlocnEaxMya8WXBOJaavZ7ZUB5J2c83gGhondQgpnBE8o 87p5xf5C3XHPCzymcsJUukTVgBX2RXjUKDHaAuS1wyG95MJIhSSYxwYGLmIbC+vcL1zi ogYw== X-Gm-Message-State: APjAAAVzq/V/qKEolo/qZj1/lcs3JBCOTDLZONVQh2j2FQDE9dPPmrVs 1OekqOHpfa8y+6wdYQP+jrdJCcA90d4= X-Google-Smtp-Source: APXvYqyEPEVpIBHHdWJrIPUfM/5fwkJbYaSzC4iotDZOCdbzk2MJaODNf/Izsthguvc9tgsNU1/ZRA== X-Received: by 2002:a62:445a:: with SMTP id r87mr42875056pfa.13.1553814261891; Thu, 28 Mar 2019 16:04:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:36 -1000 Message-Id: <20190328230404.12909-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH for-4.1 v2 08/36] target/alpha: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" With exactly one exception, most uses of alpha_env_get_cpu were failures to use the more proper, ENV_GET_CPU macro, now replaced by env_cpu. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/alpha/cpu.h | 5 ----- linux-user/alpha/cpu_loop.c | 2 +- target/alpha/helper.c | 8 +++----- target/alpha/sys_helper.c | 8 ++++---- 4 files changed, 8 insertions(+), 15 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 788edd5cb3..e22518871a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -273,11 +273,6 @@ struct AlphaCPU { QEMUTimer *alarm_timer; }; =20 -static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env) -{ - return container_of(env, AlphaCPU, env); -} - #define ENV_OFFSET offsetof(AlphaCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 824b6d6658..2acdefde03 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUAlphaState *env) { - CPUState *cs =3D CPU(alpha_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; target_siginfo_t info; abi_long sysret; diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 57e2c212b3..4769d44fd9 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -118,7 +118,7 @@ static int get_physical_address(CPUAlphaState *env, tar= get_ulong addr, int prot_need, int mmu_idx, target_ulong *pphys, int *pprot) { - CPUState *cs =3D CPU(alpha_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_long saddr =3D addr; target_ulong phys =3D 0; target_ulong L1pte, L2pte, L3pte; @@ -463,8 +463,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprint= f_function cpu_fprintf, We expect that ENV->PC has already been updated. */ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) { - AlphaCPU *cpu =3D alpha_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; env->error_code =3D error; @@ -475,8 +474,7 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int = excp, int error) void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, int excp, int error) { - AlphaCPU *cpu =3D alpha_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; env->error_code =3D error; diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index ac22323191..f9c34b1144 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -44,17 +44,17 @@ uint64_t helper_load_pcc(CPUAlphaState *env) #ifndef CONFIG_USER_ONLY void helper_tbia(CPUAlphaState *env) { - tlb_flush(CPU(alpha_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } =20 void helper_tbis(CPUAlphaState *env, uint64_t p) { - tlb_flush_page(CPU(alpha_env_get_cpu(env)), p); + tlb_flush_page(env_cpu(env), p); } =20 void helper_tb_flush(CPUAlphaState *env) { - tb_flush(CPU(alpha_env_get_cpu(env))); + tb_flush(env_cpu(env)); } =20 void helper_halt(uint64_t restart) @@ -78,7 +78,7 @@ uint64_t helper_get_walltime(void) =20 void helper_set_alarm(CPUAlphaState *env, uint64_t expire) { - AlphaCPU *cpu =3D alpha_env_get_cpu(env); + AlphaCPU *cpu =3D env_archcpu(env); =20 if (expire) { env->alarm_expire =3D expire; --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553817072053300.5578688217141; Thu, 28 Mar 2019 16:51:12 -0700 (PDT) Received: from localhost ([127.0.0.1]:43634 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9enf-0003fz-0h for importer@patchew.org; Thu, 28 Mar 2019 19:51:11 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42236) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKv-0001dn-Dj for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4S-00031F-HA for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:31 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:46713) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4Q-000300-Mb for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:27 -0400 Received: by mail-pf1-x441.google.com with SMTP id 9so65479pfj.13 for ; Thu, 28 Mar 2019 16:04:25 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. [66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=VSicWXAnsqgImKK3oQwCAroayUhfzNBl6vMMopLqj/c=; b=qWa8jxbwwYV5gXgjov9ZQ2s8e3vTXv5BB8N2HmoYzkopEguJkbaxfS+tHvn7MCSr0b DBfUxpq+3VqKFMQSOlhYOQCiBVLmai26Prcvz1m6ZL2AGi9dz47I6CwrC3pEYZMkbruY soTIae6QsMQB79GsQt6fZ8560UuqiUzFz9huY2jNEw2u5aJ0AN8J385DMD4uMl4NmgRd PMbSPbD05aydWeL0wOpXLZr2v+ZNkypikY2IieV/UAetl9e250XIb4ZrquIg7IVs+lsU RUwD2dTmQH5la8NbhDhIwMY7MhJarFBA3YkefrnLBM9BlyqgjLbH2sjgLsFEJW9+oKkB wfPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=VSicWXAnsqgImKK3oQwCAroayUhfzNBl6vMMopLqj/c=; b=ZGzrflNvOGutgF23BY7AoJtP2H53qmA0HBfCxFJr+eevclZwCREtfvYT3o8xOVVBQQ j1DjZ1YnHgrRV8QgPdRYCNUIaQ0Und3rKqGYEGujMlcdk3/DgXIjNA6DyY/7zhWDk9Xw bJ+UBspXagsej7c6vHxJunxIaXlfq1OU5DIuyyzs14nwuIxNwJbEfAzw4RmTbsy6WNmZ Ph1DjOf43fYkphB6FvqyRcMMFcCPZpiPUCt0NE9Cfx/3BnjD+PdXRpX25bhPnBiZunQV rhVs8vCxd6ghswTleNmj+GL2/TeuJNIydGXpUdzdIPra/rOkPD9mDSN9W4KyHuMntHRX nXXA== X-Gm-Message-State: APjAAAU7Ve6ezeqi9amwjbOIGZRCZyhEHnmZeD3WcZLxC0wvjTQOS5Po zd8PWpmvJTU2EjIrh5pea/bcb6fpHiQ= X-Google-Smtp-Source: APXvYqyKgyPHuAaK8irOSG57HT4/vflY4+ARgPCOxP9giJZhFaBcuPp/WnxEXo50CtVckZ9DT27uEQ== X-Received: by 2002:a62:e418:: with SMTP id r24mr44413099pfh.52.1553814263713; Thu, 28 Mar 2019 16:04:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:37 -1000 Message-Id: <20190328230404.12909-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.1 v2 09/36] target/arm: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Combined uses of CPU(arm_env_get_cpu()) were failures to use the more proper, ENV_GET_CPU macro, now replaced by env_cpu. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 5 -- linux-user/aarch64/cpu_loop.c | 6 +- linux-user/aarch64/signal.c | 4 +- linux-user/arm/cpu_loop.c | 2 +- linux-user/syscall.c | 8 +-- target/arm/arm-semi.c | 4 +- target/arm/cpu64.c | 2 +- target/arm/helper-a64.c | 4 +- target/arm/helper.c | 118 +++++++++++++++++----------------- target/arm/op_helper.c | 21 +++--- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- target/arm/vfp_helper.c | 2 +- 13 files changed, 87 insertions(+), 93 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b6bd34f5b5..3de68c5844 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -903,11 +903,6 @@ struct ARMCPU { uint32_t sve_max_vq; }; =20 -static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) -{ - return container_of(env, ARMCPU, env); -} - void arm_cpu_post_init(Object *obj); =20 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index d75fd9d3e2..97f355ee23 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -72,7 +72,7 @@ /* AArch64 main loop */ void cpu_loop(CPUARMState *env) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; abi_long ret; target_siginfo_t info; @@ -167,8 +167,8 @@ void arm_init_pauth_key(ARMPACKey *key) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; struct image_info *info =3D ts->info; int i; diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index f84a9cf28a..cd521ee42d 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -314,7 +314,7 @@ static int target_restore_sigframe(CPUARMState *env, break; =20 case TARGET_SVE_MAGIC: - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) { + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); if (!sve && size =3D=3D sve_size) { @@ -433,7 +433,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, &layout); =20 /* SVE state needs saving only if it exists. */ - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) { + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); sve_ofs =3D alloc_sigframe_space(sve_size, &layout); diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index b7e7a6323c..ece4cf335e 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -206,7 +206,7 @@ do_kernel_trap(CPUARMState *env) =20 void cpu_loop(CPUARMState *env) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; unsigned int n, insn; target_siginfo_t info; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e2fc01ad6c..88dfd9c236 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9690,10 +9690,10 @@ static abi_long do_syscall1(void *cpu_env, int num,= abi_long arg1, * even though the current architectural maximum is VQ=3D16. */ ret =3D -TARGET_EINVAL; - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(cpu_env)) + if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env)) && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t vq, old_vq; =20 old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; @@ -9710,7 +9710,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, case TARGET_PR_SVE_GET_VL: ret =3D -TARGET_EINVAL; { - ARMCPU *cpu =3D arm_env_get_cpu(cpu_env); + ARMCPU *cpu =3D env_archcpu(cpu_env); if (cpu_isar_feature(aa64_sve, cpu)) { ret =3D ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; } @@ -9719,7 +9719,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, case TARGET_PR_PAC_RESET_KEYS: { CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index b2b22d231e..c4614effff 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -242,8 +242,8 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_sy= scall_complete_cb cb, =20 target_ulong do_arm_semihosting(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 228906f267..1150cec22d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -44,7 +44,7 @@ static inline void unset_feature(CPUARMState *env, int fe= ature) #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 /* Number of cores is in [25:24]; otherwise we RAZ */ return (cpu->core_count - 1) << 24; diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 796ef34b55..44e45a8037 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1005,7 +1005,7 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) } =20 qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); =20 if (!return_to_aa64) { @@ -1047,7 +1047,7 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); =20 qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); + arm_call_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); =20 return; diff --git a/target/arm/helper.c b/target/arm/helper.c index 430a769457..a623552b5a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -223,7 +223,7 @@ static void write_raw_cp_reg(CPUARMState *env, const AR= MCPRegInfo *ri, =20 static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); const ARMCPRegInfo *ri; uint32_t key; =20 @@ -521,7 +521,7 @@ static CPAccessResult access_tpm(CPUARMState *env, cons= t ARMCPRegInfo *ri, =20 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 raw_write(env, ri, value); tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ @@ -529,7 +529,7 @@ static void dacr_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) =20 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) !=3D value) { /* Unlike real hardware the qemu TLB uses virtual addresses, @@ -543,7 +543,7 @@ static void fcse_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_PMSA) && !extended_addresses_enabled(env)) { @@ -604,7 +604,7 @@ static void tlbiall_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbiall_is_write(env, NULL, value); @@ -618,7 +618,7 @@ static void tlbimva_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbimva_is_write(env, NULL, value); @@ -632,7 +632,7 @@ static void tlbiasid_write(CPUARMState *env, const ARMC= PRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbiasid_is_write(env, NULL, value); @@ -646,7 +646,7 @@ static void tlbimvaa_write(CPUARMState *env, const ARMC= PRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbimvaa_is_write(env, NULL, value); @@ -1326,7 +1326,7 @@ static bool pmu_counter_enabled(CPUARMState *env, uin= t8_t counter) =20 static void pmu_update_irq(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); } @@ -1381,7 +1381,7 @@ static void pmccntr_op_finish(CPUARMState *env) if (overflow_in > 0) { int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_in; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); } #endif @@ -1430,7 +1430,7 @@ static void pmevcntr_op_finish(CPUARMState *env, uint= 8_t counter) if (overflow_in > 0) { int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_in; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); } #endif @@ -1838,7 +1838,7 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) { /* Begin with base v8.0 state. */ uint32_t valid_mask =3D 0x3fff; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (arm_el_is_aa64(env, 3)) { value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. */ @@ -1875,7 +1875,7 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) =20 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR * bank @@ -2425,7 +2425,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 timer_del(cpu->gt_timer[timeridx]); } @@ -2446,7 +2446,7 @@ static void gt_cval_write(CPUARMState *env, const ARM= CPRegInfo *ri, { trace_arm_gt_cval_write(timeridx, value); env->cp15.c14_timer[timeridx].cval =3D value; - gt_recalc_timer(arm_env_get_cpu(env), timeridx); + gt_recalc_timer(env_archcpu(env), timeridx); } =20 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2467,14 +2467,14 @@ static void gt_tval_write(CPUARMState *env, const A= RMCPRegInfo *ri, trace_arm_gt_tval_write(timeridx, value); env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - offs= et + sextract64(value, 0, 32); - gt_recalc_timer(arm_env_get_cpu(env), timeridx); + gt_recalc_timer(env_archcpu(env), timeridx); } =20 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t oldval =3D env->cp15.c14_timer[timeridx].ctl; =20 trace_arm_gt_ctl_write(timeridx, value); @@ -2552,7 +2552,7 @@ static void gt_virt_ctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 trace_arm_gt_cntvoff_write(value); raw_write(env, ri, value); @@ -3185,7 +3185,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const A= RMCPRegInfo *ri) static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); =20 if (!u32p) { @@ -3200,7 +3200,7 @@ static void pmsav7_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t nrgs =3D cpu->pmsav7_dregion; =20 if (value >=3D nrgs) { @@ -3328,7 +3328,7 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); TCR *tcr =3D raw_ptr(env, ri); =20 if (arm_feature(env, ARM_FEATURE_LPAE)) { @@ -3357,7 +3357,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const = ARMCPRegInfo *ri) static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); TCR *tcr =3D raw_ptr(env, ri); =20 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ @@ -3371,7 +3371,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const A= RMCPRegInfo *ri, /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ if (cpreg_field_is_64bit(ri) && extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); tlb_flush(CPU(cpu)); } raw_write(env, ri, value); @@ -3380,7 +3380,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const A= RMCPRegInfo *ri, static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ @@ -3470,7 +3470,7 @@ static void omap_wfi_write(CPUARMState *env, const AR= MCPRegInfo *ri, uint64_t value) { /* Wait-for-interrupt (deprecated) */ - cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); } =20 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3623,7 +3623,7 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { =20 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); unsigned int cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); =20 @@ -3635,7 +3635,7 @@ static uint64_t midr_read(CPUARMState *env, const ARM= CPRegInfo *ri) =20 static uint64_t mpidr_read_val(CPUARMState *env) { - ARMCPU *cpu =3D ARM_CPU(arm_env_get_cpu(env)); + ARMCPU *cpu =3D env_archcpu(env); uint64_t mpidr =3D cpu->mp_affinity; =20 if (arm_feature(env, ARM_FEATURE_V7MP)) { @@ -3788,7 +3788,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 if (arm_is_secure_below_el3(env)) { @@ -3812,7 +3812,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); @@ -3821,7 +3821,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); @@ -3877,7 +3877,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 @@ -3891,7 +3891,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * Currently handles both VAE3 and VALE3, since we don't support * flush-last-level-only. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 @@ -3901,7 +3901,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); bool sec =3D arm_is_secure_below_el3(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); @@ -3925,7 +3925,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 @@ -3974,7 +3974,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env,= const ARMCPRegInfo *ri, * translation information. * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr; =20 @@ -4017,7 +4017,7 @@ static CPAccessResult aa64_zva_access(CPUARMState *en= v, const ARMCPRegInfo *ri, =20 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int dzp_bit =3D 1 << 4; =20 /* DZP indicates whether DC ZVA access is allowed */ @@ -4052,7 +4052,7 @@ static void spsel_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t val) static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) =3D=3D value) { /* Skip the TLB flush if nothing actually changed; Linux likes @@ -4544,7 +4544,7 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = =3D { =20 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t valid_mask =3D HCR_MASK; =20 if (arm_feature(env, ARM_FEATURE_EL3)) { @@ -5211,7 +5211,7 @@ int sve_exception_el(CPUARMState *env, int el) */ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t zcr_len =3D cpu->sve_max_vq - 1; =20 if (el <=3D 1) { @@ -5379,7 +5379,7 @@ void hw_watchpoint_update_all(ARMCPU *cpu) static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the @@ -5395,7 +5395,7 @@ static void dbgwvr_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 raw_write(env, ri, value); @@ -5497,7 +5497,7 @@ void hw_breakpoint_update_all(ARMCPU *cpu) static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 raw_write(env, ri, value); @@ -5507,7 +5507,7 @@ static void dbgbvr_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only @@ -5603,7 +5603,7 @@ static void define_debug_regs(ARMCPU *cpu) */ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t pfr1 =3D cpu->id_pfr1; =20 if (env->gicv3state) { @@ -5614,7 +5614,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const = ARMCPRegInfo *ri) =20 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t pfr0 =3D cpu->isar.id_aa64pfr0; =20 if (env->gicv3state) { @@ -7358,14 +7358,14 @@ uint32_t HELPER(rbit)(uint32_t x) /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); } =20 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); return 0; @@ -7407,7 +7407,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) =20 static void switch_mode(CPUARMState *env, int mode) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (mode !=3D ARM_CPU_MODE_USR) { cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); @@ -10216,7 +10216,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint= 32_t address, target_ulong *page_size, ARMMMUFaultInfo *fi) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int level =3D 1; uint32_t table; uint32_t desc; @@ -10337,7 +10337,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, hwaddr *phys_ptr, MemTxAttrs *attrs, int *pro= t, target_ulong *page_size, ARMMMUFaultInfo *fi) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int level =3D 1; uint32_t table; uint32_t desc; @@ -10722,7 +10722,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); /* Read an LPAE long-descriptor translation table. */ ARMFaultType fault_type =3D ARMFault_Translation; @@ -11080,7 +11080,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, target_ulong *page_size, ARMMMUFaultInfo *fi) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int n; bool is_user =3D regime_is_user(env, mmu_idx); =20 @@ -11284,7 +11284,7 @@ static void v8m_security_lookup(CPUARMState *env, u= int32_t address, * pseudocode SecurityCheck() function. * We assume the caller has zero-initialized *sattrs. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int r; bool idau_exempt =3D false, idau_ns =3D true, idau_nsc =3D true; int idau_region =3D IREGION_NOTVALID; @@ -11397,7 +11397,7 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uin= t32_t address, * We set is_subpage to true if the region hit doesn't cover the * entire TARGET_PAGE the address is within. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); bool is_user =3D regime_is_user(env, mmu_idx); uint32_t secure =3D regime_is_secure(env, mmu_idx); int n; @@ -12190,7 +12190,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t mas= kreg, uint32_t val) limit =3D is_psp ? env->v7m.psplim[false] : env->v7m.msplim[fa= lse]; =20 if (val < limit) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cpu_restore_state(cs, GETPC(), true); raise_exception(env, EXCP_STKOF, 0, 1); @@ -12398,7 +12398,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vadd= r_in) * alignment faults or any memory attribute handling). */ =20 - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t blocklen =3D 4 << cpu->dcz_blocksize; uint64_t vaddr =3D vaddr_in & ~(blocklen - 1); =20 @@ -12871,7 +12871,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, uint32_t flags =3D 0; =20 if (is_a64(env)) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t sctlr; =20 *pc =3D env->pc; @@ -13014,7 +13014,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsign= ed vq) uint64_t pmask; =20 assert(vq >=3D 1 && vq <=3D ARM_MAX_VQ); - assert(vq <=3D arm_env_get_cpu(env)->sve_max_vq); + assert(vq <=3D env_archcpu(env)->sve_max_vq); =20 /* Zap the high bits of the zregs. */ for (i =3D 0; i < 32; i++) { @@ -13040,7 +13040,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsign= ed vq) void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int old_len, new_len; bool old_a64, new_a64; =20 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8698b4dc83..5af8a1f408 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -31,7 +31,7 @@ static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t target_el) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (target_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { /* @@ -245,7 +245,7 @@ void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t = newvalue) * raising an exception if the limit is breached. */ if (newvalue < v7m_sp_limit(env)) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* * Stack limit exceptions are a rare case, so rather than syncing @@ -448,7 +448,7 @@ static inline int check_wfx_trap(CPUARMState *env, bool= is_wfe) =20 void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int target_el =3D check_wfx_trap(env, false); =20 if (cpu_has_work(cs)) { @@ -483,8 +483,7 @@ void HELPER(wfe)(CPUARMState *env) =20 void HELPER(yield)(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 /* This is a non-trappable hint instruction that generally indicates * that the guest is currently busy-looping. Yield control back to the @@ -502,7 +501,7 @@ void HELPER(yield)(CPUARMState *env) */ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 assert(excp_is_internal(excp)); cs->exception_index =3D excp; @@ -545,7 +544,7 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val,= uint32_t mask) void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); =20 cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); @@ -558,7 +557,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t= val) env->regs[15] &=3D (env->thumb ? ~1 : ~3); =20 qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); + arm_call_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); } =20 @@ -863,7 +862,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *r= ip) =20 void HELPER(pre_hvc)(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int cur_el =3D arm_current_el(env); /* FIXME: Use actual secure state. */ bool secure =3D false; @@ -903,7 +902,7 @@ void HELPER(pre_hvc)(CPUARMState *env) =20 void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); bool smd_flag =3D env->cp15.scr_el3 & SCR_SMD; @@ -1177,7 +1176,7 @@ static bool check_breakpoints(ARMCPU *cpu) =20 void HELPER(check_breakpoints)(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (check_breakpoints(cpu)) { HELPER(exception_internal(env, EXCP_DEBUG)); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index dfa90a9db2..e9d5ce62ba 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14318,7 +14318,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; - ARMCPU *arm_cpu =3D arm_env_get_cpu(env); + ARMCPU *arm_cpu =3D env_archcpu(env); uint32_t tb_flags =3D dc->base.tb->flags; int bound, core_mmu_idx; =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index d408e4d7ef..89418e4cb6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -13260,7 +13260,7 @@ static void arm_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t tb_flags =3D dc->base.tb->flags; uint32_t condexec, core_mmu_idx; =20 diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 2468fc1629..e2cecd69b0 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -101,7 +101,7 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t v= al) uint32_t changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; =20 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) { + if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) { val &=3D ~FPCR_FZ16; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.1 v2 10/36] target/cris: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/cris/cpu.h | 5 ----- linux-user/cris/cpu_loop.c | 2 +- target/cris/mmu.c | 3 +-- target/cris/op_helper.c | 10 +++------- target/cris/translate.c | 2 +- 5 files changed, 6 insertions(+), 16 deletions(-) diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 632ebf84b0..6111dbb14c 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -183,11 +183,6 @@ struct CRISCPU { CPUCRISState env; }; =20 -static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env) -{ - return container_of(env, CRISCPU, env); -} - #define ENV_OFFSET offsetof(CRISCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index d012e70a7a..06709f19c1 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUCRISState *env) { - CPUState *cs =3D CPU(cris_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, ret; target_siginfo_t info; =20 diff --git a/target/cris/mmu.c b/target/cris/mmu.c index b8db908823..ff0d3f4182 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -290,7 +290,6 @@ static int cris_mmu_translate_page(struct cris_mmu_resu= lt *res, =20 void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) { - CRISCPU *cpu =3D cris_env_get_cpu(env); target_ulong vaddr; unsigned int idx; uint32_t lo, hi; @@ -316,7 +315,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) vaddr =3D tlb_vpn << TARGET_PAGE_BITS; D_LOG("flush pid=3D%x vaddr=3D%x\n",=20 pid, vaddr); - tlb_flush_page(CPU(cpu), vaddr); + tlb_flush_page(env_cpu(env), vaddr); } } } diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index 0ee3a3117b..acb137a8ce 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, =20 void helper_raise_exception(CPUCRISState *env, uint32_t index) { - CPUState *cs =3D CPU(cris_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D index; cpu_loop_exit(cs); @@ -85,8 +85,7 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) void helper_spc_write(CPUCRISState *env, uint32_t new_spc) { #if !defined(CONFIG_USER_ONLY) - CRISCPU *cpu =3D cris_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_page(cs, env->pregs[PR_SPC]); tlb_flush_page(cs, new_spc); @@ -99,9 +98,6 @@ void helper_spc_write(CPUCRISState *env, uint32_t new_spc) =20 void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) { -#if !defined(CONFIG_USER_ONLY) - CRISCPU *cpu =3D cris_env_get_cpu(env); -#endif uint32_t srs; srs =3D env->pregs[PR_SRS]; srs &=3D 3; @@ -143,7 +139,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t s= reg, uint32_t reg) D_LOG("tlb flush vaddr=3D%x v=3D%d pc=3D%x\n",=20 vaddr, tlb_v, env->pc); if (tlb_v) { - tlb_flush_page(CPU(cpu), vaddr); + tlb_flush_page(env_cpu(env), vaddr); } } } diff --git a/target/cris/translate.c b/target/cris/translate.c index 11b2c11174..b5598c6fd5 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3104,7 +3104,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) * delayslot, like in real hw. */ pc_start =3D tb->pc & ~1; - dc->cpu =3D cris_env_get_cpu(env); + dc->cpu =3D env_archcpu(env); dc->tb =3D tb; =20 dc->is_jmp =3D DISAS_NEXT; --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH for-4.1 v2 11/36] target/hppa: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Combined uses of CPU(hppa_env_get_cpu()) were failures to use the more proper, ENV_GET_CPU macro, now replaced by env_cpu. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/hppa/cpu.h | 5 ----- linux-user/hppa/cpu_loop.c | 2 +- target/hppa/helper.c | 3 +-- target/hppa/int_helper.c | 4 ++-- target/hppa/mem_helper.c | 10 ++++------ target/hppa/op_helper.c | 8 +++----- 6 files changed, 11 insertions(+), 21 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6ae73e24e4..1387066324 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -222,11 +222,6 @@ struct HPPACPU { QEMUTimer *alarm_timer; }; =20 -static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) -{ - return container_of(env, HPPACPU, env); -} - #define ENV_OFFSET offsetof(HPPACPU, env) =20 typedef CPUHPPAState CPUArchState; diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 880955fdef..9915456a1d 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -105,7 +105,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) =20 void cpu_loop(CPUHPPAState *env) { - CPUState *cs =3D CPU(hppa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_siginfo_t info; abi_ulong ret; int trapnr; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index ac750b62ef..eb5047037e 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -70,8 +70,7 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) /* If PSW_P changes, it affects how we translate addresses. */ if ((psw ^ old_psw) & PSW_P) { #ifndef CONFIG_USER_ONLY - CPUState *src =3D CPU(hppa_env_get_cpu(env)); - tlb_flush_by_mmuidx(src, 0xf); + tlb_flush_by_mmuidx(env_cpu(env), 0xf); #endif } } diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 8d5edd3a20..89241c31e7 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -77,7 +77,7 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ureg va= l) { env->cr[CR_EIRR] &=3D ~val; qemu_mutex_lock_iothread(); - eval_interrupt(hppa_env_get_cpu(env)); + eval_interrupt(env_archcpu(env)); qemu_mutex_unlock_iothread(); } =20 @@ -85,7 +85,7 @@ void HELPER(write_eiem)(CPUHPPAState *env, target_ureg va= l) { env->cr[CR_EIEM] =3D val; qemu_mutex_lock_iothread(); - eval_interrupt(hppa_env_get_cpu(env)); + eval_interrupt(env_archcpu(env)); qemu_mutex_unlock_iothread(); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index c9b57d07c3..77d5cb6c42 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -55,7 +55,7 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, v= addr addr) =20 static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent) { - CPUState *cs =3D CPU(hppa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); unsigned i, n =3D 1 << (2 * ent->page_size); uint64_t addr =3D ent->va_b; =20 @@ -324,7 +324,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data da= ta) =20 void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) { - CPUState *src =3D CPU(hppa_env_get_cpu(env)); + CPUState *src =3D env_cpu(env); CPUState *cpu; trace_hppa_tlb_ptlb(env); run_on_cpu_data data =3D RUN_ON_CPU_TARGET_PTR(addr); @@ -341,17 +341,15 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong add= r) number of pages/entries (we choose all), and is local to the cpu. */ void HELPER(ptlbe)(CPUHPPAState *env) { - CPUState *src =3D CPU(hppa_env_get_cpu(env)); trace_hppa_tlb_ptlbe(env); memset(env->tlb, 0, sizeof(env->tlb)); - tlb_flush_by_mmuidx(src, 0xf); + tlb_flush_by_mmuidx(env_cpu(env), 0xf); } =20 void cpu_hppa_change_prot_id(CPUHPPAState *env) { if (env->psw & PSW_P) { - CPUState *src =3D CPU(hppa_env_get_cpu(env)); - tlb_flush_by_mmuidx(src, 0xf); + tlb_flush_by_mmuidx(env_cpu(env), 0xf); } } =20 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 952e97a7d7..04d23c1b22 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -29,8 +29,7 @@ =20 void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) { - HPPACPU *cpu =3D hppa_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; cpu_loop_exit(cs); @@ -38,8 +37,7 @@ void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int ex= cp) =20 void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_= t ra) { - HPPACPU *cpu =3D hppa_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; cpu_loop_exit_restore(cs, ra); @@ -630,7 +628,7 @@ target_ureg HELPER(read_interval_timer)(void) #ifndef CONFIG_USER_ONLY void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val) { - HPPACPU *cpu =3D hppa_env_get_cpu(env); + HPPACPU *cpu =3D env_archcpu(env); uint64_t current =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); uint64_t timeout; =20 --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816899596672.9376116286987; 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH for-4.1 v2 12/36] target/i386: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Combined uses of CPU(x86_env_get_cpu()) were failures to use the more proper, ENV_GET_CPU macro, now replaced by env_cpu. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/i386/cpu.h | 5 ----- bsd-user/main.c | 3 +-- hw/i386/kvmvapic.c | 4 ++-- hw/i386/pc.c | 2 +- linux-user/i386/cpu_loop.c | 2 +- linux-user/i386/signal.c | 2 +- linux-user/vm86.c | 18 +++++++++--------- target/i386/bpt_helper.c | 4 ++-- target/i386/cpu.c | 4 ++-- target/i386/excp_helper.c | 2 +- target/i386/fpu_helper.c | 2 +- target/i386/helper.c | 16 ++++++---------- target/i386/misc_helper.c | 24 +++++++++++------------- target/i386/seg_helper.c | 14 +++++++------- target/i386/smm_helper.c | 4 ++-- target/i386/svm_helper.c | 22 +++++++++++----------- 16 files changed, 58 insertions(+), 70 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 450842185a..7ff5ab77c1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1477,11 +1477,6 @@ struct X86CPU { int32_t hv_max_vps; }; =20 -static inline X86CPU *x86_env_get_cpu(CPUX86State *env) -{ - return container_of(env, X86CPU, env); -} - #define ENV_OFFSET offsetof(X86CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/bsd-user/main.c b/bsd-user/main.c index 0d3156974c..e554ebdfb3 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -139,8 +139,7 @@ static void set_idt(int n, unsigned int dpl) =20 void cpu_loop(CPUX86State *env) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(cpu); int trapnr; abi_ulong pc; //target_siginfo_t info; diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 70f6f26a94..fe5b12ef6e 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -152,7 +152,7 @@ static void update_guest_rom_state(VAPICROMState *s) =20 static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); hwaddr paddr; target_ulong addr; =20 @@ -279,7 +279,7 @@ instruction_ok: =20 static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_u= long ip) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); hwaddr paddr; uint32_t rom_state_vaddr; uint32_t pos, patch, offset; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 6077d27361..f2caaa8132 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -405,7 +405,7 @@ uint64_t cpu_get_tsc(CPUX86State *env) /* IRQ handling */ int cpu_get_pic_interrupt(CPUX86State *env) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); int intno; =20 if (!kvm_irqchip_in_kernel()) { diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 51cfa006c9..71da24384f 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -82,7 +82,7 @@ static void set_idt(int n, unsigned int dpl) =20 void cpu_loop(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; abi_ulong pc; abi_ulong ret; diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index fecb4c99c3..97a39204cc 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -198,7 +198,7 @@ static void setup_sigcontext(struct target_sigcontext *= sc, struct target_fpstate *fpstate, CPUX86State *env, abi_ulong mask, abi_ulong fpstate_addr) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); #ifndef TARGET_X86_64 uint16_t magic; =20 diff --git a/linux-user/vm86.c b/linux-user/vm86.c index 9c393df424..2fa7a89edc 100644 --- a/linux-user/vm86.c +++ b/linux-user/vm86.c @@ -72,7 +72,7 @@ static inline unsigned int vm_getl(CPUX86State *env, =20 void save_v86_state(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; struct target_vm86plus_struct * target_v86; =20 @@ -132,7 +132,7 @@ static inline void return_to_32bit(CPUX86State *env, in= t retval) =20 static inline int set_IF(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 ts->v86flags |=3D VIF_MASK; @@ -145,7 +145,7 @@ static inline int set_IF(CPUX86State *env) =20 static inline void clear_IF(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 ts->v86flags &=3D ~VIF_MASK; @@ -163,7 +163,7 @@ static inline void clear_AC(CPUX86State *env) =20 static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 set_flags(ts->v86flags, eflags, ts->v86mask); @@ -177,7 +177,7 @@ static inline int set_vflags_long(unsigned long eflags,= CPUX86State *env) =20 static inline int set_vflags_short(unsigned short flags, CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 set_flags(ts->v86flags, flags, ts->v86mask & 0xffff); @@ -191,7 +191,7 @@ static inline int set_vflags_short(unsigned short flags= , CPUX86State *env) =20 static inline unsigned int get_vflags(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; unsigned int flags; =20 @@ -208,7 +208,7 @@ static inline unsigned int get_vflags(CPUX86State *env) support TSS interrupt revectoring, so this code is always executed) */ static void do_int(CPUX86State *env, int intno) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; uint32_t int_addr, segoffs, ssp; unsigned int sp; @@ -267,7 +267,7 @@ void handle_vm86_trap(CPUX86State *env, int trapno) =20 void handle_vm86_fault(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; uint32_t csp, ssp; unsigned int ip, sp, newflags, newip, newcs, opcode, intno; @@ -392,7 +392,7 @@ void handle_vm86_fault(CPUX86State *env) =20 int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; struct target_vm86plus_struct * target_v86; int ret; diff --git a/target/i386/bpt_helper.c b/target/i386/bpt_helper.c index b3efdc77ec..c3a8ea73c9 100644 --- a/target/i386/bpt_helper.c +++ b/target/i386/bpt_helper.c @@ -53,7 +53,7 @@ static inline int hw_breakpoint_len(unsigned long dr7, in= t index) =20 static int hw_breakpoint_insert(CPUX86State *env, int index) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong dr7 =3D env->dr[7]; target_ulong drN =3D env->dr[index]; int err =3D 0; @@ -97,7 +97,7 @@ static int hw_breakpoint_insert(CPUX86State *env, int ind= ex) =20 static void hw_breakpoint_remove(CPUX86State *env, int index) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 switch (hw_breakpoint_type(env->dr[7], index)) { case DR7_TYPE_BP_INST: diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d6bb57d210..cdec1db05e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4176,8 +4176,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + X86CPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); uint32_t pkg_offset; uint32_t limit; uint32_t signature[3]; diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index 49231f6b69..371792ce8b 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -90,7 +90,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *e= nv, int intno, int next_eip_addend, uintptr_t retaddr) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (!is_int) { cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno, diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c index ea5a0c4861..005f1f68f8 100644 --- a/target/i386/fpu_helper.c +++ b/target/i386/fpu_helper.c @@ -1477,7 +1477,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr= , uint64_t rfbm) env->pkru =3D 0; } if (env->pkru !=3D old_pkru) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); tlb_flush(cs); } } diff --git a/target/i386/helper.c b/target/i386/helper.c index e695f8ba7a..3cfcde9021 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -628,7 +628,7 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state) =20 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); int pe_state; =20 qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=3D0x%08x\n", new_cr0); @@ -670,19 +670,16 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t ne= w_cr0) the PDPT */ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3) { - X86CPU *cpu =3D x86_env_get_cpu(env); - env->cr[3] =3D new_cr3; if (env->cr[0] & CR0_PG_MASK) { qemu_log_mask(CPU_LOG_MMU, "CR3 update: CR3=3D" TARGET_FMT_lx "\n", new_cr3); - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4) { - X86CPU *cpu =3D x86_env_get_cpu(env); uint32_t hflags; =20 #if defined(DEBUG_MMU) @@ -691,7 +688,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_= cr4) if ((new_cr4 ^ env->cr[4]) & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 /* Clear bits we're going to recompute. */ @@ -983,8 +980,8 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int = bank, =20 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + X86CPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (kvm_enabled() || whpx_enabled()) { env->tpr_access_type =3D access; @@ -1002,8 +999,7 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned= int selector, target_ulong *base, unsigned int *limit, unsigned int *flags) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); SegmentCache *dt; target_ulong ptr; uint32_t e1, e2; diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c index 78f2020ef2..3eff6885f8 100644 --- a/target/i386/misc_helper.c +++ b/target/i386/misc_helper.c @@ -133,7 +133,7 @@ target_ulong helper_read_crN(CPUX86State *env, int reg) break; case 8: if (!(env->hflags2 & HF2_VINTR_MASK)) { - val =3D cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state); + val =3D cpu_get_apic_tpr(env_archcpu(env)->apic_state); } else { val =3D env->v_tpr; } @@ -158,7 +158,7 @@ void helper_write_crN(CPUX86State *env, int reg, target= _ulong t0) case 8: if (!(env->hflags2 & HF2_VINTR_MASK)) { qemu_mutex_lock_iothread(); - cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0); + cpu_set_apic_tpr(env_archcpu(env)->apic_state, t0); qemu_mutex_unlock_iothread(); } env->v_tpr =3D t0 & 0x0f; @@ -180,7 +180,7 @@ void helper_lmsw(CPUX86State *env, target_ulong t0) =20 void helper_invlpg(CPUX86State *env, target_ulong addr) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); =20 cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC()); tlb_flush_page(CPU(cpu), addr); @@ -247,7 +247,7 @@ void helper_wrmsr(CPUX86State *env) env->sysenter_eip =3D val; break; case MSR_IA32_APICBASE: - cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val); + cpu_set_apic_base(env_archcpu(env)->apic_state, val); break; case MSR_EFER: { @@ -404,7 +404,7 @@ void helper_rdmsr(CPUX86State *env) val =3D env->sysenter_eip; break; case MSR_IA32_APICBASE: - val =3D cpu_get_apic_base(x86_env_get_cpu(env)->apic_state); + val =3D cpu_get_apic_base(env_archcpu(env)->apic_state); break; case MSR_EFER: val =3D env->efer; @@ -561,7 +561,7 @@ static void do_hlt(X86CPU *cpu) =20 void helper_hlt(CPUX86State *env, int next_eip_addend) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); =20 cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC()); env->eip +=3D next_eip_addend; @@ -580,8 +580,8 @@ void helper_monitor(CPUX86State *env, target_ulong ptr) =20 void helper_mwait(CPUX86State *env, int next_eip_addend) { - CPUState *cs; - X86CPU *cpu; + CPUState *cs =3D env_cpu(env); + X86CPU *cpu =3D env_archcpu(env); =20 if ((uint32_t)env->regs[R_ECX] !=3D 0) { raise_exception_ra(env, EXCP0D_GPF, GETPC()); @@ -589,8 +589,6 @@ void helper_mwait(CPUX86State *env, int next_eip_addend) cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC()); env->eip +=3D next_eip_addend; =20 - cpu =3D x86_env_get_cpu(env); - cs =3D CPU(cpu); /* XXX: not complete but not completely erroneous */ if (cs->cpu_index !=3D 0 || CPU_NEXT(cs) !=3D NULL) { do_pause(cpu); @@ -601,7 +599,7 @@ void helper_mwait(CPUX86State *env, int next_eip_addend) =20 void helper_pause(CPUX86State *env, int next_eip_addend) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); =20 cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC()); env->eip +=3D next_eip_addend; @@ -611,7 +609,7 @@ void helper_pause(CPUX86State *env, int next_eip_addend) =20 void helper_debug(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_DEBUG; cpu_loop_exit(cs); @@ -631,7 +629,7 @@ uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx) =20 void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if ((env->cr[4] & CR4_PKE_MASK) =3D=3D 0) { raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC()); diff --git a/target/i386/seg_helper.c b/target/i386/seg_helper.c index 63e265cb38..87a627f9dc 100644 --- a/target/i386/seg_helper.c +++ b/target/i386/seg_helper.c @@ -137,7 +137,7 @@ static inline void get_ss_esp_from_tss(CPUX86State *env= , uint32_t *ss_ptr, uint32_t *esp_ptr, int dpl, uintptr_t retaddr) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); int type, index, shift; =20 #if 0 @@ -830,7 +830,7 @@ static void do_interrupt_protected(CPUX86State *env, in= t intno, int is_int, =20 static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); int index; =20 #if 0 @@ -972,7 +972,7 @@ static void do_interrupt64(CPUX86State *env, int intno,= int is_int, #if defined(CONFIG_USER_ONLY) void helper_syscall(CPUX86State *env, int next_eip_addend) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_SYSCALL; env->exception_next_eip =3D env->eip + next_eip_addend; @@ -1172,7 +1172,7 @@ static void do_interrupt_user(CPUX86State *env, int i= ntno, int is_int, static void handle_even_inj(CPUX86State *env, int intno, int is_int, int error_code, int is_hw, int rm) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t event_inj =3D x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct= vmcb, control.event_in= j)); =20 @@ -1312,7 +1312,7 @@ void x86_cpu_do_interrupt(CPUState *cs) =20 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw) { - do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw); + do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw); } =20 bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -1763,7 +1763,7 @@ void helper_lcall_protected(CPUX86State *env, int new= _cs, target_ulong new_eip, target_ulong ssp, old_ssp, offset, sp; =20 LOG_PCALL("lcall %04x:" TARGET_FMT_lx " s=3D%d\n", new_cs, new_eip, sh= ift); - LOG_PCALL_STATE(CPU(x86_env_get_cpu(env))); + LOG_PCALL_STATE(env_cpu(env)); if ((new_cs & 0xfffc) =3D=3D 0) { raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); } @@ -2167,7 +2167,7 @@ static inline void helper_ret_protected(CPUX86State *= env, int shift, } LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=3D%d addend=3D0x%x\n", new_cs, new_eip, shift, addend); - LOG_PCALL_STATE(CPU(x86_env_get_cpu(env))); + LOG_PCALL_STATE(env_cpu(env)); if ((new_cs & 0xfffc) =3D=3D 0) { raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr); } diff --git a/target/i386/smm_helper.c b/target/i386/smm_helper.c index c1c34a75db..eb5aa6eb3d 100644 --- a/target/i386/smm_helper.c +++ b/target/i386/smm_helper.c @@ -204,8 +204,8 @@ void do_smm_enter(X86CPU *cpu) =20 void helper_rsm(CPUX86State *env) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + X86CPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); target_ulong sm_state; int i, offset; uint32_t val; diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c index 9fd22a883b..7b8105a1c3 100644 --- a/target/i386/svm_helper.c +++ b/target/i386/svm_helper.c @@ -84,7 +84,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port,= uint32_t param, static inline void svm_save_seg(CPUX86State *env, hwaddr addr, const SegmentCache *sc) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 x86_stw_phys(cs, addr + offsetof(struct vmcb_seg, selector), sc->selector); @@ -99,7 +99,7 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr = addr, static inline void svm_load_seg(CPUX86State *env, hwaddr addr, SegmentCache *sc) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); unsigned int flags; =20 sc->selector =3D x86_lduw_phys(cs, @@ -122,7 +122,7 @@ static inline void svm_load_seg_cache(CPUX86State *env,= hwaddr addr, =20 void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong addr; uint64_t nested_ctl; uint32_t event_inj; @@ -314,7 +314,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next= _eip_addend) env->hflags2 |=3D HF2_GIF_MASK; =20 if (int_ctl & V_IRQ_MASK) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->interrupt_request |=3D CPU_INTERRUPT_VIRQ; } @@ -379,7 +379,7 @@ void helper_vmmcall(CPUX86State *env) =20 void helper_vmload(CPUX86State *env, int aflag) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong addr; =20 cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0, GETPC()); @@ -419,7 +419,7 @@ void helper_vmload(CPUX86State *env, int aflag) =20 void helper_vmsave(CPUX86State *env, int aflag) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong addr; =20 cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0, GETPC()); @@ -482,7 +482,7 @@ void helper_skinit(CPUX86State *env) =20 void helper_invlpga(CPUX86State *env, int aflag) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); target_ulong addr; =20 cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0, GETPC()); @@ -501,7 +501,7 @@ void helper_invlpga(CPUX86State *env, int aflag) void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, uint64_t param, uintptr_t retaddr) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (likely(!(env->hflags & HF_GUEST_MASK))) { return; @@ -583,7 +583,7 @@ void helper_svm_check_intercept_param(CPUX86State *env,= uint32_t type, void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, uint32_t next_eip_addend) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) { /* FIXME: this should be read in at vmrun (faster this way?) */ @@ -604,7 +604,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t por= t, uint32_t param, void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1, uintptr_t retaddr) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cpu_restore_state(cs, retaddr, true); =20 @@ -625,7 +625,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, u= int64_t exit_info_1, =20 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t int_ctl; =20 if (env->hflags & HF_INHIBIT_IRQ_MASK) { --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553817006209313.6206411629196; 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.1 v2 13/36] target/lm32: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/lm32/cpu.h | 5 ----- target/lm32/helper.c | 19 ++++++------------- target/lm32/op_helper.c | 6 +++--- target/lm32/translate.c | 2 +- 4 files changed, 10 insertions(+), 22 deletions(-) diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 258f2b4266..69beb16972 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -195,11 +195,6 @@ struct LM32CPU { uint32_t features; }; =20 -static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env) -{ - return container_of(env, LM32CPU, env); -} - #define ENV_OFFSET offsetof(LM32CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/lm32/helper.c b/target/lm32/helper.c index a039a993ff..674cbd7fe4 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -58,28 +58,23 @@ hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) =20 void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong addre= ss) { - LM32CPU *cpu =3D lm32_env_get_cpu(env); - - cpu_breakpoint_insert(CPU(cpu), address, BP_CPU, + cpu_breakpoint_insert(env_cpu(env), address, BP_CPU, &env->cpu_breakpoint[idx]); } =20 void lm32_breakpoint_remove(CPULM32State *env, int idx) { - LM32CPU *cpu =3D lm32_env_get_cpu(env); - if (!env->cpu_breakpoint[idx]) { return; } =20 - cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]); + cpu_breakpoint_remove_by_ref(env_cpu(env), env->cpu_breakpoint[idx]); env->cpu_breakpoint[idx] =3D NULL; } =20 void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong addre= ss, lm32_wp_t wp_type) { - LM32CPU *cpu =3D lm32_env_get_cpu(env); int flags =3D 0; =20 switch (wp_type) { @@ -98,26 +93,24 @@ void lm32_watchpoint_insert(CPULM32State *env, int idx,= target_ulong address, } =20 if (flags !=3D 0) { - cpu_watchpoint_insert(CPU(cpu), address, 1, flags, - &env->cpu_watchpoint[idx]); + cpu_watchpoint_insert(env_cpu(env), address, 1, flags, + &env->cpu_watchpoint[idx]); } } =20 void lm32_watchpoint_remove(CPULM32State *env, int idx) { - LM32CPU *cpu =3D lm32_env_get_cpu(env); - if (!env->cpu_watchpoint[idx]) { return; } =20 - cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]); + cpu_watchpoint_remove_by_ref(env_cpu(env), env->cpu_watchpoint[idx]); env->cpu_watchpoint[idx] =3D NULL; } =20 static bool check_watchpoints(CPULM32State *env) { - LM32CPU *cpu =3D lm32_env_get_cpu(env); + LM32CPU *cpu =3D env_archcpu(env); int i; =20 for (i =3D 0; i < cpu->num_watchpoints; i++) { diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c index 234d55e056..ebff4c4518 100644 --- a/target/lm32/op_helper.c +++ b/target/lm32/op_helper.c @@ -16,7 +16,7 @@ #if !defined(CONFIG_USER_ONLY) void raise_exception(CPULM32State *env, int index) { - CPUState *cs =3D CPU(lm32_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D index; cpu_loop_exit(cs); @@ -29,7 +29,7 @@ void HELPER(raise_exception)(CPULM32State *env, uint32_t = index) =20 void HELPER(hlt)(CPULM32State *env) { - CPUState *cs =3D CPU(lm32_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; @@ -39,7 +39,7 @@ void HELPER(hlt)(CPULM32State *env) void HELPER(ill)(CPULM32State *env) { #ifndef CONFIG_USER_ONLY - CPUState *cs =3D CPU(lm32_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); fprintf(stderr, "VM paused due to illegal instruction. " "Connect a debugger or switch to the monitor console " "to find out more.\n"); diff --git a/target/lm32/translate.c b/target/lm32/translate.c index b32feb7564..e2163809f2 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1052,7 +1052,7 @@ static inline void decode(DisasContext *dc, uint32_t = ir) void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { CPULM32State *env =3D cs->env_ptr; - LM32CPU *cpu =3D lm32_env_get_cpu(env); + LM32CPU *cpu =3D env_archcpu(env); struct DisasContext ctx, *dc =3D &ctx; uint32_t pc_start; uint32_t page_start; --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155381674801973.1371473754889; Thu, 28 Mar 2019 16:45:48 -0700 (PDT) Received: from localhost ([127.0.0.1]:43564 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eiN-0007on-MY for importer@patchew.org; Thu, 28 Mar 2019 19:45:43 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42236) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKr-0001dn-O6 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4X-00034S-Ex for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:35 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:34171) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4X-00033q-00 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:33 -0400 Received: by mail-pf1-x442.google.com with SMTP id b3so91475pfd.1 for ; Thu, 28 Mar 2019 16:04:32 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. [66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.29 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=t6biCR3bYjtIIkxF1uGVJl2LJQiurMRXpIddInTdyro=; b=YJ+g6xVhTVGDWFVpHHGPBglOvc8YF7z+RAqugS+dCuMAfrTG0wDektFliF7cm3VjTz Qn42ok7JR/435YJ3BP4QfQ2NZ+Wm7/axOAwi4A0x5Y7KGKu+HhjMfOcdkHlMHowGLXlR Y/+spMLL/RiuRBsDr1GAyXf/e4KCp0Yuigljvt4WiuO16OgU1B7XKGbolwo5NtQOHDFv ShA5mL+Wjdm8tZO5+czu7GpMZqjbHNfaWqTXvCQ9Oy1BzahQDKbvHvzKNf0Ok5Mhw6oT WzWKGL0Q5KoCDp47i2Ad2PHgLwe9ixXc/iRw5KpayNGx3+MxFsIhl/0RMAXSQV/pBUqj I72A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=t6biCR3bYjtIIkxF1uGVJl2LJQiurMRXpIddInTdyro=; b=UupEzEuq9TPCw7so4+G84X9ke+ndQrZYHlS42TBEe3UtGWt4rkHGWXB2TlFntkReM2 ZZ85jY5Xz8A330b3395JrIBH41L505tUV08Oz7lltzgc63JypysNQGWXtFBWqMsgS0aC NapakCEqUCpA72a1Q3j53TtBddPEnhKFhyc1kUQWyx/RESIdwutxtsjkBOJcbtcME3VZ RnWnf4n+iVV8m9IiqiMVkR7K32zL5Qdft5y9lQ24+KcsHOlkM+ouEd5AE88D/IP+ZTXZ jsIRQWwioID9XFDYfW2nILHyTrUVse2cf5IzPk8IRJ65W+fpUT0ChrXx4LQwUiyBvzO5 nrIQ== X-Gm-Message-State: APjAAAXwsVNYkoErQo/dh3gBSeHvcS5XkceXmZ+9XqooSYWEvjMjTUKT hCH/T8G+BvNeFO8zbUvYDdM5+w5AxwU= X-Google-Smtp-Source: APXvYqyVxkU10vwlhMxmFoGXWSYo6VDVKeUpAeym4cFFxMfUI9fj4DBl+YTsOVEb/SII7HoNn9tcbQ== X-Received: by 2002:a62:cfc4:: with SMTP id b187mr15964464pfg.130.1553814271486; Thu, 28 Mar 2019 16:04:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:42 -1000 Message-Id: <20190328230404.12909-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.1 v2 14/36] target/m68k: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/m68k/target_cpu.h | 2 +- target/m68k/cpu.h | 5 ----- linux-user/m68k-sim.c | 3 +-- linux-user/m68k/cpu_loop.c | 2 +- target/m68k/helper.c | 33 ++++++++++++--------------------- target/m68k/m68k-semi.c | 4 ++-- target/m68k/op_helper.c | 12 ++++++------ target/m68k/translate.c | 4 +--- 8 files changed, 24 insertions(+), 41 deletions(-) diff --git a/linux-user/m68k/target_cpu.h b/linux-user/m68k/target_cpu.h index 7a26f3c3fc..bc7446fbaf 100644 --- a/linux-user/m68k/target_cpu.h +++ b/linux-user/m68k/target_cpu.h @@ -31,7 +31,7 @@ static inline void cpu_clone_regs(CPUM68KState *env, targ= et_ulong newsp) =20 static inline void cpu_set_tls(CPUM68KState *env, target_ulong newtls) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 ts->tp_value =3D newtls; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index b216be33b4..eb3048914e 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -163,11 +163,6 @@ struct M68kCPU { CPUM68KState env; }; =20 -static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) -{ - return container_of(env, M68kCPU, env); -} - #define ENV_OFFSET offsetof(M68kCPU, env) =20 void m68k_cpu_do_interrupt(CPUState *cpu); diff --git a/linux-user/m68k-sim.c b/linux-user/m68k-sim.c index 34d332d8b1..9bc6ff3d3a 100644 --- a/linux-user/m68k-sim.c +++ b/linux-user/m68k-sim.c @@ -91,7 +91,6 @@ static int translate_openflags(int flags) #define ARG(x) tswap32(args[x]) void do_m68k_simcall(CPUM68KState *env, int nr) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); uint32_t *args; =20 args =3D (uint32_t *)(unsigned long)(env->aregs[7] + 4); @@ -159,6 +158,6 @@ void do_m68k_simcall(CPUM68KState *env, int nr) check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2))); break; default: - cpu_abort(CPU(cpu), "Unsupported m68k sim syscall %d\n", nr); + cpu_abort(env_cpu(env), "Unsupported m68k sim syscall %d\n", nr); } } diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 42d8d841ea..f2c33057b3 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUM68KState *env) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; unsigned int n; target_siginfo_t info; diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 3e26d337bf..c519086c4b 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -174,8 +174,6 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) =20 void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - switch (reg) { case M68K_CR_CACR: env->cacr =3D val; @@ -192,7 +190,7 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t re= g, uint32_t val) break; /* TODO: Implement control registers. */ default: - cpu_abort(CPU(cpu), + cpu_abort(env_cpu(env), "Unimplemented control register write 0x%x =3D 0x%x\n", reg, val); } @@ -200,8 +198,6 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t re= g, uint32_t val) =20 void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - switch (reg) { /* MC680[1234]0 */ case M68K_CR_SFC: @@ -254,14 +250,13 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_= t reg, uint32_t val) env->mmu.ttr[M68K_DTTR1] =3D val; return; } - cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x =3D 0x%= x\n", + cpu_abort(env_cpu(env), + "Unimplemented control register write 0x%x =3D 0x%x\n", reg, val); } =20 uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - switch (reg) { /* MC680[1234]0 */ case M68K_CR_SFC: @@ -298,7 +293,7 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uin= t32_t reg) case M68K_CR_DTT1: return env->mmu.ttr[M68K_DTTR1]; } - cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n", + cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n", reg); } =20 @@ -409,8 +404,7 @@ static void dump_address_map(FILE *f, fprintf_function = cpu_fprintf, uint32_t last_logical, last_physical; int32_t size; int last_attr =3D -1, attr =3D -1; - M68kCPU *cpu =3D m68k_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 if (env->mmu.tcr & M68K_TCR_PAGE_8K) { /* 8k page */ @@ -644,8 +638,7 @@ static int get_physical_address(CPUM68KState *env, hwad= dr *physical, int *prot, target_ulong address, int access_type, target_ulong *page_size) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); uint32_t entry; uint32_t next; target_ulong page_mask; @@ -1137,7 +1130,7 @@ void HELPER(mac_set_flags)(CPUM68KState *env, uint32_= t acc) z =3D n; = \ break; = \ default: = \ - cpu_abort(CPU(m68k_env_get_cpu(env)), "Bad CC_OP %d", op); = \ + cpu_abort(env_cpu(env), "Bad CC_OP %d", op); = \ } = \ } while (0) =20 @@ -1320,8 +1313,6 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t= val, uint32_t acc) #if defined(CONFIG_SOFTMMU) void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); hwaddr physical; int access_type; int prot; @@ -1346,7 +1337,7 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, = uint32_t is_read) if (ret =3D=3D 0) { addr &=3D TARGET_PAGE_MASK; physical +=3D addr & (page_size - 1); - tlb_set_page(cs, addr, physical, + tlb_set_page(env_cpu(env), addr, physical, prot, access_type & ACCESS_SUPER ? MMU_KERNEL_IDX : MMU_USER_IDX, page_size); } @@ -1354,18 +1345,18 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr= , uint32_t is_read) =20 void HELPER(pflush)(CPUM68KState *env, uint32_t addr, uint32_t opmode) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); + CPUState *cs =3D env_cpu(env); =20 switch (opmode) { case 0: /* Flush page entry if not global */ case 1: /* Flush page entry */ - tlb_flush_page(CPU(cpu), addr); + tlb_flush_page(cs, addr); break; case 2: /* Flush all except global entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; case 3: /* Flush all entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; } } diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index 1402145c8f..6716b93b5a 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -421,7 +421,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) case HOSTED_INIT_SIM: #if defined(CONFIG_USER_ONLY) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; /* Allocate the heap using sbrk. */ if (!ts->heap_limit) { @@ -454,7 +454,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) #endif return; default: - cpu_abort(CPU(m68k_env_get_cpu(env)), "Unsupported semihosting sys= call %d\n", nr); + cpu_abort(env_cpu(env), "Unsupported semihosting syscall %d\n", nr= ); result =3D 0; } failed: diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 13fcaa74ef..39aa9310e1 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -211,7 +211,7 @@ static const char *m68k_exception_name(int index) =20 static void cf_interrupt_all(CPUM68KState *env, int is_hw) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t sp; uint32_t sr; uint32_t fmt; @@ -289,7 +289,7 @@ static inline void do_stack_frame(CPUM68KState *env, ui= nt32_t *sp, { if (m68k_feature(env, M68K_FEATURE_QUAD_MULDIV)) { /* all except 68000 */ - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); switch (format) { case 4: *sp -=3D 4; @@ -314,7 +314,7 @@ static inline void do_stack_frame(CPUM68KState *env, ui= nt32_t *sp, =20 static void m68k_interrupt_all(CPUM68KState *env, int is_hw) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t sp; uint32_t retaddr; uint32_t vector; @@ -526,7 +526,7 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D tt; cpu_loop_exit_restore(cs, raddr); @@ -1056,7 +1056,7 @@ void HELPER(chk)(CPUM68KState *env, int32_t val, int3= 2_t ub) env->cc_c =3D 0 <=3D ub ? val < 0 || val > ub : val > ub && val < 0; =20 if (val < 0 || val > ub) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* Recover PC and CC_OP for the beginning of the insn. */ cpu_restore_state(cs, GETPC(), true); @@ -1087,7 +1087,7 @@ void HELPER(chk2)(CPUM68KState *env, int32_t val, int= 32_t lb, int32_t ub) env->cc_c =3D lb <=3D ub ? val < lb || val > ub : val > ub && val < lb; =20 if (env->cc_c) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* Recover PC and CC_OP for the beginning of the insn. */ cpu_restore_state(cs, GETPC(), true); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 6217a683f1..b06c1528b9 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4777,14 +4777,12 @@ DISAS_INSN(wddata) =20 DISAS_INSN(wdebug) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - if (IS_USER(s)) { gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE); return; } /* TODO: Implement wdebug. */ - cpu_abort(CPU(cpu), "WDEBUG not implemented"); + cpu_abort(env_cpu(env), "WDEBUG not implemented"); } #endif =20 --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816492877918.5192193369413; Thu, 28 Mar 2019 16:41:32 -0700 (PDT) Received: from localhost ([127.0.0.1]:43474 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eeA-0003Gq-Lk for importer@patchew.org; Thu, 28 Mar 2019 19:41:22 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42458) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKr-0001my-D4 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4Y-00034k-FJ for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:35 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:40538) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4Y-00034Y-5a for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:34 -0400 Received: by mail-pg1-x542.google.com with SMTP id u9so226027pgo.7 for ; Thu, 28 Mar 2019 16:04:34 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. [66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=3OxT6mpM/m6PbtrRF3gNTdG5tddrrD1q+DqAaSZ/g70=; b=XSlIGQGfWdFttawaUTNFX8GG2F2rwIKAozctshacQhyFl5lXFj+F4YsuzW01N85QNu QNYYNGOLBUll85lNR8yzAolC0bZK4/t7eHim7EvgmJ3RD0mHxt2Q1Bfdzum2b1fRBSKr oTRHVrZ1KnK9JbQ+pkmKpVIA9jmdlO1qZ7u0v+aDZ2o/J3TfzN5srfEBBaIh7ENdQN/R lNJptS9clPMwTVNJ+Y6YDEckKbRSGvvA9CEMplXSk3Vyl3ywsli8fobYW86riyL60qoJ Ti0ZBt48wO8Nlr+/ir3+eXrH/bsWngWGL4u1UvYu3nQBYNbHNji8W4hM9R7D0pD/nF3j sZ6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=3OxT6mpM/m6PbtrRF3gNTdG5tddrrD1q+DqAaSZ/g70=; b=qMq9kw7CHiYrALn+BEl4tVoQ9cAJhVYDxyqBcCtCAYDwvZ4GEeDAgDEvk2lvugqLdV hahGnpgHJS3Y/64wIwa7Y5feCSchf7s8+JUo6Bt3lfd/8iyiHbe1yBKKJkJ2ffNlsd0r duS4nxaSweQDdFJuL/boTuMtOEYwGhq1Sf/8vHSnSLWvgJH4lG02CEZasmCorRyVM62O qwiNmWhCn5TIM6rOKIfVBeRVNTEzsaxgw2M3FszP58af7tuKuBuYV8NhDMC3tlAQm6HI MA1qD5iwf46QYL0ew2IAhAvYrhpT/S9mS1gB3LElSPRqcSATPKnsyCf13l3sV+eD3nsK Qvkw== X-Gm-Message-State: APjAAAW7ZpVD0si8OaWfxJrxgWk5FcZ0/MjPdfp1a0XGGlDXZzKoIKak o/dN7n92j6/9VuPYtVwsjID080EPELY= X-Google-Smtp-Source: APXvYqyDzD+yksmmjRfuQSeQ3c0AU69c96/ZPS8zMHr3LTQN9BFVXL93MPjZB2FSQCm6i3npqM1iwA== X-Received: by 2002:aa7:93a5:: with SMTP id x5mr26783816pff.234.1553814272897; Thu, 28 Mar 2019 16:04:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:43 -1000 Message-Id: <20190328230404.12909-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH for-4.1 v2 15/36] target/microblaze: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/microblaze/cpu.h | 35 ++++++++++++++------------------ linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/mmu.c | 5 ++--- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 2 +- 5 files changed, 20 insertions(+), 26 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 3ca5d21451..a9748d57ad 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -310,11 +310,6 @@ struct MicroBlazeCPU { CPUMBState env; }; =20 -static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) -{ - return container_of(env, MicroBlazeCPU, env); -} - #define ENV_OFFSET offsetof(MicroBlazeCPU, env) =20 void mb_cpu_do_interrupt(CPUState *cs); @@ -345,21 +340,6 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ =20 -static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) -{ - MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); - - /* Are we in nommu mode?. */ - if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { - return MMU_NOMMU_IDX; - } - - if (env->sregs[SR_MSR] & MSR_UM) { - return MMU_USER_IDX; - } - return MMU_KERNEL_IDX; -} - int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); =20 @@ -384,4 +364,19 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr ph= ysaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif =20 +static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) +{ + MicroBlazeCPU *cpu =3D env_archcpu(env); + + /* Are we in nommu mode?. */ + if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { + return MMU_NOMMU_IDX; + } + + if (env->sregs[SR_MSR] & MSR_UM) { + return MMU_USER_IDX; + } + return MMU_KERNEL_IDX; +} + #endif diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index c2190e15fd..f70329e021 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUMBState *env) { - CPUState *cs =3D CPU(mb_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, ret; target_siginfo_t info; =20 diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index fcf86b12d5..6763421ba2 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -34,7 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f) =20 static void mmu_flush_idx(CPUMBState *env, unsigned int idx) { - CPUState *cs =3D CPU(mb_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); struct microblaze_mmu *mmu =3D &env->mmu; unsigned int tlb_size; uint32_t tlb_tag, end, t; @@ -228,7 +228,6 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t r= n) =20 void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) { - MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); uint64_t tmp64; unsigned int i; qemu_log_mask(CPU_LOG_MMU, @@ -269,7 +268,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, = uint32_t v) /* Changes to the zone protection reg flush the QEMU TLB. Fortunately, these are very uncommon. */ if (v !=3D env->mmu.regs[rn]) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } env->mmu.regs[rn] =3D v; break; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index e23dcfdc20..aa91d3a257 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -84,7 +84,7 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl) =20 void helper_raise_exception(CPUMBState *env, uint32_t index) { - CPUState *cs =3D CPU(mb_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D index; cpu_loop_exit(cs); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 78ca265b04..816ba53721 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1603,7 +1603,7 @@ static inline void decode(DisasContext *dc, uint32_t = ir) void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { CPUMBState *env =3D cs->env_ptr; - MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); + MicroBlazeCPU *cpu =3D env_archcpu(env); uint32_t pc_start; struct DisasContext ctx; struct DisasContext *dc =3D &ctx; --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816798411899.7243502065728; Thu, 28 Mar 2019 16:46:38 -0700 (PDT) Received: from localhost ([127.0.0.1]:43566 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9ej4-0008FH-Sc for importer@patchew.org; Thu, 28 Mar 2019 19:46:26 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42644) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKq-0001yi-SJ for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4b-00035f-2P for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:39 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:43767) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4Z-000352-V4 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:36 -0400 Received: by mail-pg1-x543.google.com with SMTP id z9so219975pgu.10 for ; Thu, 28 Mar 2019 16:04:35 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH for-4.1 v2 16/36] target/mips: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 5 ----- hw/intc/mips_gic.c | 2 +- hw/mips/mips_int.c | 2 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/helper.c | 15 +++++---------- target/mips/op_helper.c | 25 +++++++++++-------------- target/mips/translate.c | 3 +-- target/mips/translate_init.inc.c | 4 +--- 8 files changed, 21 insertions(+), 37 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e7ad81becb..914cc26c21 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1051,11 +1051,6 @@ struct MIPSCPU { CPUMIPSState env; }; =20 -static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) -{ - return container_of(env, MIPSCPU, env); -} - #define ENV_OFFSET offsetof(MIPSCPU, env) =20 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index 15e6e40f9f..8f509493ea 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -44,7 +44,7 @@ static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp= , int pin) GIC_VP_MASK_CMP_SHF; } if (kvm_enabled()) { - kvm_mips_set_ipi_interrupt(mips_env_get_cpu(gic->vps[vp].env), + kvm_mips_set_ipi_interrupt(env_archcpu(gic->vps[vp].env), pin + GIC_CPU_PIN_OFFSET, ored_level); } else { diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 5ddeb15848..f899f6ceb3 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -76,7 +76,7 @@ void cpu_mips_irq_init_cpu(MIPSCPU *cpu) qemu_irq *qi; int i; =20 - qi =3D qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env),= 8); + qi =3D qemu_allocate_irqs(cpu_mips_irq_request, env_archcpu(env), 8); for (i =3D 0; i < 8; i++) { env->irq[i] =3D qi[i]; } diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 828137cd84..ac6c6d1504 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -425,7 +425,7 @@ static int do_break(CPUMIPSState *env, target_siginfo_t= *info, =20 void cpu_loop(CPUMIPSState *env) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_siginfo_t info; int trapnr; abi_long ret; diff --git a/target/mips/helper.c b/target/mips/helper.c index c44cdca3b5..1fc0a4ce4b 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -336,10 +336,8 @@ static int get_physical_address (CPUMIPSState *env, hw= addr *physical, =20 void cpu_mips_tlb_flush(CPUMIPSState *env) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - /* Flush qemu's TLB and discard all shadowed entries. */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); env->tlb->tlb_in_use =3D env->tlb->nb_tlb; } =20 @@ -401,7 +399,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ul= ong val) #if defined(TARGET_MIPS64) if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { /* Access to at least one of the 64-bit segments has been disabled= */ - tlb_flush(CPU(mips_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } #endif if (env->CP0_Config3 & (1 << CP0C3_MT)) { @@ -446,7 +444,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val) static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, int rw, int tlb_error) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int exception =3D 0, error_code =3D 0; =20 if (rw =3D=3D MMU_INST_FETCH) { @@ -1400,8 +1398,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - CPUState *cs; + CPUState *cs =3D env_cpu(env); r4k_tlb_t *tlb; target_ulong addr; target_ulong end; @@ -1427,7 +1424,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, = int use_extra) /* 1k pages are not supported. */ mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); if (tlb->V0) { - cs =3D CPU(cpu); addr =3D tlb->VPN & ~mask; #if defined(TARGET_MIPS64) if (addr >=3D (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -1441,7 +1437,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, = int use_extra) } } if (tlb->V1) { - cs =3D CPU(cpu); addr =3D (tlb->VPN & ~mask) | ((mask >> 1) + 1); #if defined(TARGET_MIPS64) if (addr >=3D (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -1462,7 +1457,7 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSStat= e *env, int error_code, uintptr_t pc) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", __func__, exception, error_code); diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0f272a5b93..0705e8c686 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -350,7 +350,7 @@ static inline hwaddr do_translate_address(CPUMIPSState = *env, int rw, uintptr_t re= taddr) { hwaddr paddr; - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 paddr =3D cpu_mips_translate_address(env, address, rw); =20 @@ -699,7 +699,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env,= int *tc) return env; } =20 - cs =3D CPU(mips_env_get_cpu(env)); + cs =3D env_cpu(env); vpe_idx =3D tc_idx / cs->nr_threads; *tc =3D tc_idx % cs->nr_threads; other_cs =3D qemu_get_cpu(vpe_idx); @@ -1298,7 +1298,7 @@ void helper_mttc0_tcrestart(CPUMIPSState *env, target= _ulong arg1) =20 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); + MIPSCPU *cpu =3D env_archcpu(env); =20 env->active_tc.CP0_TCHalt =3D arg1 & 0x1; =20 @@ -1314,7 +1314,7 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ul= ong arg1) { int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - MIPSCPU *other_cpu =3D mips_env_get_cpu(other); + MIPSCPU *other_cpu =3D env_archcpu(other); =20 // TODO: Halt TC / Restart (if allocated+active) TC. =20 @@ -1427,7 +1427,7 @@ void helper_mtc0_pagegrain(CPUMIPSState *env, target_= ulong arg1) =20 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->CP0_SegCtl0 =3D arg1 & CP0SC0_MASK; tlb_flush(cs); @@ -1435,7 +1435,7 @@ void helper_mtc0_segctl0(CPUMIPSState *env, target_ul= ong arg1) =20 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->CP0_SegCtl1 =3D arg1 & CP0SC1_MASK; tlb_flush(cs); @@ -1443,7 +1443,7 @@ void helper_mtc0_segctl1(CPUMIPSState *env, target_ul= ong arg1) =20 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->CP0_SegCtl2 =3D arg1 & CP0SC2_MASK; tlb_flush(cs); @@ -1666,7 +1666,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ul= ong arg1) /* If the ASID changes, flush qemu's TLB. */ if ((old & env->CP0_EntryHi_ASID_mask) !=3D (val & env->CP0_EntryHi_ASID_mask)) { - tlb_flush(CPU(mips_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } } =20 @@ -1686,7 +1686,6 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ul= ong arg1) =20 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); uint32_t val, old; =20 old =3D env->CP0_Status; @@ -1706,7 +1705,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulo= ng arg1) case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; default: - cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; } } @@ -2485,8 +2484,6 @@ static void debug_pre_eret(CPUMIPSState *env) =20 static void debug_post_eret(CPUMIPSState *env) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); @@ -2502,7 +2499,7 @@ static void debug_post_eret(CPUMIPSState *env) case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; default: - cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; } } @@ -2633,7 +2630,7 @@ void helper_pmon(CPUMIPSState *env, int function) =20 void helper_wait(CPUMIPSState *env) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->halted =3D 1; cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); diff --git a/target/mips/translate.c b/target/mips/translate.c index 364bd6dc4f..7ace8c3b96 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29911,8 +29911,7 @@ void cpu_set_exception_base(int vp_index, target_ul= ong address) =20 void cpu_state_reset(CPUMIPSState *env) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 /* Reset registers to their default values */ env->CP0_PRid =3D env->cpu_model->CP0_PRid; diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index bf559aff08..50586a01a2 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -872,8 +872,6 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips= _def_t *def) =20 static void mmu_init (CPUMIPSState *env, const mips_def_t *def) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - env->tlb =3D g_malloc0(sizeof(CPUMIPSTLBContext)); =20 switch (def->mmu_type) { @@ -890,7 +888,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def= _t *def) case MMU_TYPE_R6000: case MMU_TYPE_R8000: default: - cpu_abort(CPU(cpu), "MMU type not supported\n"); + cpu_abort(env_cpu(env), "MMU type not supported\n"); } } #endif /* CONFIG_USER_ONLY */ --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816290434939.1726656640024; Thu, 28 Mar 2019 16:38:10 -0700 (PDT) Received: from localhost ([127.0.0.1]:43414 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eb1-0000Uq-Dr for importer@patchew.org; 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[66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=mkqdyW5/3Htii3Wd/GiAKdhmnJwDMiTansAHma9RvjA=; b=U8BFFBIhQZK5UIw5o64o4tNuRHoTEIeXz9wTZ6zJG2IqO9iCf9+pw79egwzitBNBL+ sOBRPgVnrghUqkP8hGWpbvwM6hU6c/ZOc6OfjJ7B3UD0/4VfaPwiXnssbkHKQi2Zb7iV lANDekogZVF0rvSxcNnwHgKfK3HF5V6TEtadGNlZX/OJOpi5LyCSZjTZEUkpU2EwZSAs FKrFRQXbFjM6pt7vF9rRXhGakV2sKyiDad5U1VwRBh1fr4T9Xh5pHTE3PZhLHTJ+yFQQ HdtvnzOuGBTSonsPPw/kYvLzdT5OB4QY74BbvKadH9qzmdXZdxxZhwFjcRWpbkZBRwB6 4KbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=mkqdyW5/3Htii3Wd/GiAKdhmnJwDMiTansAHma9RvjA=; b=uBB6F+hiM2gNDkV4WR/eIH/fb+j3If16XlhUWpGX/s6UTraUR11afrVFqF2vBfBFRL tH0UgrrwTbXgDqoc+JOZtaI+tdpcBCcOwfhyl47RYl1gr75+njoQcMyY2oRM0MMblQEM zGeE9SxNlbObFs/FpZVCzZ8hBQu71ZnLw28kbYcYCLyRUL8qyg18jiGRMs2yCVZzgVJd O/97fGSlD3n8ky1uUz7PBDw2mN+IMLJHPxEydg9QyyDE+e4UkKO3YcM06x7gAokYwEPK dsppUHZU5keOGiEJdDAEQ2+75mWFMwRd2COjDyDqHDRUVybBp+JF6KYR9mUUn8WZQLIc /U6g== X-Gm-Message-State: APjAAAUTrseQwQwNS2kUG6zoKFd2FA2ZzHWU8YkaJiAAzWYnucOg4iAF E5k0asFTSm3BxT/tcg23JhlJqn9iSKg= X-Google-Smtp-Source: APXvYqwvs49sq4PKCq7aQ8EfbNlO2egDtLiRBU+hzDGGq4+jFfmBF1MPPgUxeMEiBFpUDiYkbXQdWQ== X-Received: by 2002:a62:75d7:: with SMTP id q206mr20281085pfc.213.1553814275997; Thu, 28 Mar 2019 16:04:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:45 -1000 Message-Id: <20190328230404.12909-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.1 v2 17/36] target/moxie: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/moxie/cpu.h | 5 ----- target/moxie/helper.c | 6 +++--- target/moxie/translate.c | 2 +- 3 files changed, 4 insertions(+), 9 deletions(-) diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index c050d6e15d..71e7cf0f08 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -90,11 +90,6 @@ typedef struct MoxieCPU { CPUMoxieState env; } MoxieCPU; =20 -static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env) -{ - return container_of(env, MoxieCPU, env); -} - #define ENV_OFFSET offsetof(MoxieCPU, env) =20 void moxie_cpu_do_interrupt(CPUState *cs); diff --git a/target/moxie/helper.c b/target/moxie/helper.c index f3d8ee7d6b..a22870228c 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -42,7 +42,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, =20 void helper_raise_exception(CPUMoxieState *env, int ex) { - CPUState *cs =3D CPU(moxie_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D ex; /* Stash the exception type. */ @@ -79,7 +79,7 @@ uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint= 32_t b) =20 void helper_debug(CPUMoxieState *env) { - CPUState *cs =3D CPU(moxie_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_DEBUG; cpu_loop_exit(cs); @@ -89,7 +89,7 @@ void helper_debug(CPUMoxieState *env) =20 void moxie_cpu_do_interrupt(CPUState *cs) { - CPUState *cs =3D CPU(moxie_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D -1; } diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 68ca223e22..bb25a3dee7 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -816,7 +816,7 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx) void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { CPUMoxieState *env =3D cs->env_ptr; - MoxieCPU *cpu =3D moxie_env_get_cpu(env); + MoxieCPU *cpu =3D env_archcpu(env); DisasContext ctx; target_ulong pc_start; int num_insns, max_insns; --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816315659968.334955864939; Thu, 28 Mar 2019 16:38:35 -0700 (PDT) Received: from localhost ([127.0.0.1]:43418 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9ebN-0000ji-JV for importer@patchew.org; Thu, 28 Mar 2019 19:38:29 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKq-0001km-JG for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4h-00037S-R8 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:45 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:39154) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4f-00035y-ML for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:42 -0400 Received: by mail-pg1-x543.google.com with SMTP id k3so229669pga.6 for ; Thu, 28 Mar 2019 16:04:38 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. [66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.36 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=zb3IwtEFtozbWmQd0XMuC4pAkuKjWM7tvwO+rs6HOfo=; b=YobJelZX71gUV7s3ktbKEZHXnQnxR9s2xGa7/jEV0He3Tb47ga79Y93YxQtzGSZiIn u0tYmqtaQ5OgAOw9bAi701UVI4ODyH9llnVu3NBOhczBasWeucQteUr9jQgDBPknAKAc YjaFx46thqWYrbMreFiEDOYLDl4Jyo5GkaY1xvi/spD699VYSrCnYOCn2XQkBtyOvwuY NzFQ3tJPzfR3R6D5MW173183ljugUoSaHDmIZuYKtKKEC+HiBUGInCUF/RUIiksD/gc3 WBjwBM5qtMNMjJs1wG09uOre9p0xdqYGBIIQB5D5sJRXtfmWc1JuJPBlFq8UxH7REp2f uJtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=zb3IwtEFtozbWmQd0XMuC4pAkuKjWM7tvwO+rs6HOfo=; b=BBDqwnXIC1dK8Sr1NnLJCZdQSyX64v+HtbmujvJ73/U9cZ+pCjMBDAVtL8f46gSvRI myc4Sxx7lGrjsi1ZI2w9yijIgBL3/6aGi5PeSamNEb/117pRsmyKRqz9V+ACn9xbxUJq H8JT6IGSBoVF4Cd05YsESSTvqHSpzG9cjRI5DpitlVMZQ0Ds7pGpGbJAZVbQ10sMP4Iv qqO6xlPzrdJScQZfkylWkapRhDfNzlsYwbo00N+MfIf9jhX/eqPqMViUcPbN6fX9z5e4 ToE0bEFF/eEUTIdaT3Oq8HqA8pWn6t8bAqTqh+af9ChKT70AdWbE1x6QLEZrmZ2hQSFh qcxw== X-Gm-Message-State: APjAAAWF5qLGcevBR5GnsQ+4VtdztJJ9ffLKdmHCLzRj+7+GciA1Mdkw 82jWGRn1tEPEVtp+zyN/N1Yw/A1/yTI= X-Google-Smtp-Source: APXvYqw+ZDVRpUkkIiptIWr3yNbHX8hzownz0MqkKcJJKpSK6H5Oftc++5vT+h9afv8CoVHJSG3Mbw== X-Received: by 2002:a62:445a:: with SMTP id r87mr42876488pfa.13.1553814277572; Thu, 28 Mar 2019 16:04:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:46 -1000 Message-Id: <20190328230404.12909-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH for-4.1 v2 18/36] target/nios2: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 5 ----- hw/nios2/cpu_pic.c | 5 +---- target/nios2/mmu.c | 10 +++++----- 3 files changed, 6 insertions(+), 14 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index e0e12a910e..3fc27ead81 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -193,11 +193,6 @@ typedef struct Nios2CPU { uint32_t fast_tlb_miss_addr; } Nios2CPU; =20 -static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env) -{ - return NIOS2_CPU(container_of(env, Nios2CPU, env)); -} - #define ENV_OFFSET offsetof(Nios2CPU, env) =20 void nios2_tcg_init(void); diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c index 6bccce2f32..9e39955bd1 100644 --- a/hw/nios2/cpu_pic.c +++ b/hw/nios2/cpu_pic.c @@ -54,12 +54,9 @@ static void nios2_pic_cpu_handler(void *opaque, int irq,= int level) =20 void nios2_check_interrupts(CPUNios2State *env) { - Nios2CPU *cpu =3D nios2_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - if (env->irq_pending) { env->irq_pending =3D 0; - cpu_interrupt(cs, CPU_INTERRUPT_HARD); + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); } } =20 diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 0752699e25..173da3becc 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -72,7 +72,7 @@ unsigned int mmu_translate(CPUNios2State *env, Nios2MMULookup *lu, target_ulong vaddr, int rw, int mmu_idx) { - Nios2CPU *cpu =3D nios2_env_get_cpu(env); + Nios2CPU *cpu =3D env_archcpu(env); int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int vpn =3D vaddr >> 12; =20 @@ -114,7 +114,7 @@ unsigned int mmu_translate(CPUNios2State *env, static void mmu_flush_pid(CPUNios2State *env, uint32_t pid) { CPUState *cs =3D env_cpu(env); - Nios2CPU *cpu =3D nios2_env_get_cpu(env); + Nios2CPU *cpu =3D env_archcpu(env); int idx; MMU_LOG(qemu_log("TLB Flush PID %d\n", pid)); =20 @@ -138,7 +138,7 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t = pid) void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) { CPUState *cs =3D env_cpu(env); - Nios2CPU *cpu =3D nios2_env_get_cpu(env); + Nios2CPU *cpu =3D env_archcpu(env); =20 MMU_LOG(qemu_log("mmu_write %08X =3D %08X\n", rn, v)); =20 @@ -255,7 +255,7 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_= t v) =20 void mmu_init(CPUNios2State *env) { - Nios2CPU *cpu =3D nios2_env_get_cpu(env); + Nios2CPU *cpu =3D env_archcpu(env); Nios2MMU *mmu =3D &env->mmu; =20 MMU_LOG(qemu_log("mmu_init\n")); @@ -266,7 +266,7 @@ void mmu_init(CPUNios2State *env) =20 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUNios2State *env) { - Nios2CPU *cpu =3D nios2_env_get_cpu(env); + Nios2CPU *cpu =3D env_archcpu(env); int i; =20 cpu_fprintf(f, "MMU: ways %d, entries %d, pid bits %d\n", --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816677670830.4234525082974; Thu, 28 Mar 2019 16:44:37 -0700 (PDT) Received: from localhost ([127.0.0.1]:43521 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9ehD-0006GR-GF for importer@patchew.org; Thu, 28 Mar 2019 19:44:31 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42236) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKp-0001dn-JL for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4h-00037Y-W1 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:45 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:33302) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4h-00036R-LG for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:43 -0400 Received: by mail-pf1-x441.google.com with SMTP id i19so93864pfd.0 for ; Thu, 28 Mar 2019 16:04:40 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.1 v2 19/36] target/openrisc: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/openrisc/cpu.h | 5 ----- linux-user/openrisc/cpu_loop.c | 2 +- target/openrisc/exception_helper.c | 5 ++--- target/openrisc/sys_helper.c | 8 ++++---- 4 files changed, 7 insertions(+), 13 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 3eda7957cf..853cf633e7 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,11 +317,6 @@ typedef struct OpenRISCCPU { =20 } OpenRISCCPU; =20 -static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) -{ - return container_of(env, OpenRISCCPU, env); -} - #define ENV_OFFSET offsetof(OpenRISCCPU, env) =20 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index f496e4b48a..4b8165b261 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUOpenRISCState *env) { - CPUState *cs =3D CPU(openrisc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; abi_long ret; target_siginfo_t info; diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception= _helper.c index 6073a5b21c..dd639ba5f2 100644 --- a/target/openrisc/exception_helper.c +++ b/target/openrisc/exception_helper.c @@ -25,15 +25,14 @@ =20 void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp) { - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); + OpenRISCCPU *cpu =3D env_archcpu(env); =20 raise_exception(cpu, excp); } =20 static void QEMU_NORETURN do_range(CPUOpenRISCState *env, uintptr_t pc) { - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_RANGE; cpu_loop_exit_restore(cs, pc); diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 05f66c455b..8f11cb8202 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -30,8 +30,8 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong r= b) { #ifndef CONFIG_USER_ONLY - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + OpenRISCCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); target_ulong mr; int idx; =20 @@ -194,8 +194,8 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, targe= t_ulong rd, target_ulong spr) { #ifndef CONFIG_USER_ONLY - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + OpenRISCCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); int idx; =20 switch (spr) { --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816635954266.37509438314646; Thu, 28 Mar 2019 16:43:55 -0700 (PDT) Received: from localhost ([127.0.0.1]:43519 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9egX-0005o2-QT for importer@patchew.org; Thu, 28 Mar 2019 19:43:49 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42393) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKo-0001jU-DY for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4j-000388-H9 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:50 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:39689) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4h-000375-UR for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:44 -0400 Received: by mail-pf1-x441.google.com with SMTP id i17so80534pfo.6 for ; Thu, 28 Mar 2019 16:04:43 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.1 v2 20/36] target/ppc: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/ppc/cpu.h | 7 +- target/ppc/helper_regs.h | 4 +- hw/ppc/ppc.c | 18 ++--- hw/ppc/ppc405_uc.c | 2 +- hw/ppc/ppc_booke.c | 4 +- linux-user/ppc/cpu_loop.c | 2 +- target/ppc/excp_helper.c | 14 ++-- target/ppc/fpu_helper.c | 14 ++-- target/ppc/kvm.c | 5 +- target/ppc/misc_helper.c | 22 ++---- target/ppc/mmu-hash64.c | 14 ++-- target/ppc/mmu_helper.c | 116 +++++++++++++------------------- target/ppc/translate_init.inc.c | 87 ++++++++++++------------ 13 files changed, 137 insertions(+), 172 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a5d44d1b1f..c3fe154979 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1191,11 +1191,6 @@ struct PowerPCCPU { int32_t mig_slb_nr; }; =20 -static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) -{ - return container_of(env, PowerPCCPU, env); -} - #define ENV_OFFSET offsetof(PowerPCCPU, env) =20 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); @@ -2429,7 +2424,7 @@ static inline int booke206_tlbm_to_tlbn(CPUPPCState *= env, ppcmas_tlb_t *tlbm) } } =20 - cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id); + cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id); return 0; } =20 diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index a2205e1044..337ca93fae 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -115,7 +115,7 @@ static inline int hreg_store_msr(CPUPPCState *env, targ= et_ulong value, { int excp; #if !defined(CONFIG_USER_ONLY) - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); #endif =20 excp =3D 0; @@ -173,7 +173,7 @@ static inline int hreg_store_msr(CPUPPCState *env, targ= et_ulong value, #if !defined(CONFIG_USER_ONLY) static inline void check_tlb_flush(CPUPPCState *env, bool global) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* Handle global flushes first */ if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 49d57469fb..6beed2a918 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -385,7 +385,7 @@ void ppc40x_system_reset(PowerPCCPU *cpu) =20 void store_40x_dbcr0(CPUPPCState *env, uint32_t val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); =20 switch ((val >> 28) & 0x3) { case 0x0: @@ -785,7 +785,7 @@ target_ulong cpu_ppc_load_decr(CPUPPCState *env) =20 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); ppc_tb_t *tb_env =3D env->tb_env; uint64_t hdecr; @@ -923,7 +923,7 @@ static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu,= target_ulong decr, =20 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); int nr_bits =3D 32; =20 @@ -955,7 +955,7 @@ static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu= , target_ulong hdecr, =20 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, @@ -980,7 +980,7 @@ static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_= t value) static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) { CPUPPCState *env =3D opaque; - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc_tb_t *tb_env =3D env->tb_env; =20 tb_env->tb_freq =3D freq; @@ -1095,7 +1095,7 @@ const VMStateDescription vmstate_ppc_timebase =3D { /* Set up (once) timebase frequency (in Hz) */ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc_tb_t *tb_env; =20 tb_env =3D g_malloc0(sizeof(ppc_tb_t)); @@ -1165,7 +1165,7 @@ static void cpu_4xx_fit_cb (void *opaque) uint64_t now, next; =20 env =3D opaque; - cpu =3D ppc_env_get_cpu(env); + cpu =3D env_archcpu(env); tb_env =3D env->tb_env; ppc40x_timer =3D tb_env->opaque; now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -1235,7 +1235,7 @@ static void cpu_4xx_pit_cb (void *opaque) ppc40x_timer_t *ppc40x_timer; =20 env =3D opaque; - cpu =3D ppc_env_get_cpu(env); + cpu =3D env_archcpu(env); tb_env =3D env->tb_env; ppc40x_timer =3D tb_env->opaque; env->spr[SPR_40x_TSR] |=3D 1 << 27; @@ -1261,7 +1261,7 @@ static void cpu_4xx_wdt_cb (void *opaque) uint64_t now, next; =20 env =3D opaque; - cpu =3D ppc_env_get_cpu(env); + cpu =3D env_archcpu(env); tb_env =3D env->tb_env; ppc40x_timer =3D tb_env->opaque; now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 3ae7f6d4df..018dcca888 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -49,7 +49,7 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, uint32_t flags) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); ram_addr_t bdloc; int i, n; =20 diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index 4f11e00a17..323413e074 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -249,7 +249,7 @@ static void booke_wdt_cb(void *opaque) =20 void store_booke_tsr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc_tb_t *tb_env =3D env->tb_env; booke_timer_t *booke_timer =3D tb_env->opaque; =20 @@ -277,7 +277,7 @@ void store_booke_tsr(CPUPPCState *env, target_ulong val) =20 void store_booke_tcr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc_tb_t *tb_env =3D env->tb_env; booke_timer_t *booke_timer =3D tb_env->opaque; =20 diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 801f5ace29..24dfdba854 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -67,7 +67,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t= val) =20 void cpu_loop(CPUPPCState *env) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_siginfo_t info; int trapnr; target_ulong ret; diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index beafcf1ebd..706fc8f18b 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -49,7 +49,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) =20 static void ppc_hw_interrupt(CPUPPCState *env) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D POWERPC_EXCP_NONE; env->error_code =3D 0; @@ -778,7 +778,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) =20 static void ppc_hw_interrupt(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); bool async_deliver; =20 /* External reset */ @@ -917,7 +917,7 @@ static void ppc_hw_interrupt(CPUPPCState *env) * It generally means a discrepancy between the wakup conditions i= n the * processor has_work implementation and the logic in this functio= n. */ - cpu_abort(CPU(ppc_env_get_cpu(env)), + cpu_abort(env_cpu(env), "Wakeup from PM state but interrupt Undelivered"); } } @@ -960,7 +960,7 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong = msr) void raise_exception_err_ra(CPUPPCState *env, uint32_t exception, uint32_t error_code, uintptr_t raddr) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D exception; env->error_code =3D error_code; @@ -1001,7 +1001,7 @@ void helper_store_msr(CPUPPCState *env, target_ulong = val) uint32_t excp =3D hreg_store_msr(env, val, 0); =20 if (excp !=3D 0) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); cpu_interrupt_exittb(cs); raise_exception(env, excp); } @@ -1012,7 +1012,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_= t insn) { CPUState *cs; =20 - cs =3D CPU(ppc_env_get_cpu(env)); + cs =3D env_cpu(env); cs->halted =3D 1; =20 /* The architecture specifies that HDEC interrupts are @@ -1028,7 +1028,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_= t insn) =20 static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong= msr) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* MSR:POW cannot be set by any form of rfi */ msr &=3D ~(1ULL << MSR_POW); diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 2ed4f42275..c8bdd54d03 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -269,7 +269,7 @@ static void float_invalid_op_vxvc(CPUPPCState *env, boo= l set_fpcc, env->fpscr |=3D FP_FX; /* We must update the target FPR before raising the exception */ if (fpscr_ve !=3D 0) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D POWERPC_EXCP_PROGRAM; env->error_code =3D POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; @@ -313,7 +313,7 @@ static inline void float_zero_divide_excp(CPUPPCState *= env, uintptr_t raddr) =20 static inline void float_overflow_excp(CPUPPCState *env) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->fpscr |=3D 1 << FPSCR_OX; /* Update the floating-point exception summary */ @@ -333,7 +333,7 @@ static inline void float_overflow_excp(CPUPPCState *env) =20 static inline void float_underflow_excp(CPUPPCState *env) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->fpscr |=3D 1 << FPSCR_UX; /* Update the floating-point exception summary */ @@ -350,7 +350,7 @@ static inline void float_underflow_excp(CPUPPCState *en= v) =20 static inline void float_inexact_excp(CPUPPCState *env) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->fpscr |=3D 1 << FPSCR_FI; env->fpscr |=3D 1 << FPSCR_XX; @@ -440,7 +440,7 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) =20 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int prev; =20 prev =3D (env->fpscr >> bit) & 1; @@ -572,7 +572,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) =20 void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong prev, new; int i; =20 @@ -610,7 +610,7 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32= _t mask) =20 static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int status =3D get_float_exception_flags(&env->fp_status); bool inexact_happened =3D false; =20 diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 2427c8ee13..5e05b579c0 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1965,9 +1965,8 @@ static int kvmppc_get_dec_bits(void) } =20 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvin= fo) - { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); +{ + CPUState *cs =3D env_cpu(env); =20 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index c65d1ade15..2be1aa2e50 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -81,28 +81,24 @@ void helper_msr_facility_check(CPUPPCState *env, uint32= _t bit, =20 void helper_store_sdr1(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - if (env->spr[SPR_SDR1] !=3D val) { ppc_store_sdr1(env, val); - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 #if defined(TARGET_PPC64) void helper_store_ptcr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - if (env->spr[SPR_PTCR] !=3D val) { ppc_store_ptcr(env, val); - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 void helper_store_pcr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 env->spr[SPR_PCR] =3D value & pcc->pcr_mask; @@ -111,16 +107,12 @@ void helper_store_pcr(CPUPPCState *env, target_ulong = value) =20 void helper_store_pidr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - env->spr[SPR_BOOKS_PID] =3D val; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void helper_store_lpidr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - env->spr[SPR_LPIDR] =3D val; =20 /* @@ -129,7 +121,7 @@ void helper_store_lpidr(CPUPPCState *env, target_ulong = val) * potentially access and cache entries for the current LPID as * well. */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void helper_store_hid0_601(CPUPPCState *env, target_ulong val) @@ -151,12 +143,10 @@ void helper_store_hid0_601(CPUPPCState *env, target_u= long val) =20 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong val= ue) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - if (likely(env->pb[num] !=3D value)) { env->pb[num] =3D value; /* Should be optimized */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index a2b1ec5040..9e8d04d3fa 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -93,7 +93,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, Powe= rPCCPU *cpu) =20 void helper_slbia(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); int n; =20 /* XXX: Warning: slbia never invalidates the first segment */ @@ -114,7 +114,7 @@ void helper_slbia(CPUPPCState *env) static void __helper_slbie(CPUPPCState *env, target_ulong addr, target_ulong global) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc_slb_t *slb; =20 slb =3D slb_lookup(cpu, addr); @@ -246,7 +246,7 @@ static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ul= ong rb, =20 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); =20 if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) { raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, @@ -256,7 +256,7 @@ void helper_store_slb(CPUPPCState *env, target_ulong rb= , target_ulong rs) =20 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); target_ulong rt =3D 0; =20 if (ppc_load_slb_esid(cpu, rb, &rt) < 0) { @@ -268,7 +268,7 @@ target_ulong helper_load_slb_esid(CPUPPCState *env, tar= get_ulong rb) =20 target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); target_ulong rt =3D 0; =20 if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { @@ -280,7 +280,7 @@ target_ulong helper_find_slb_vsid(CPUPPCState *env, tar= get_ulong rb) =20 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); target_ulong rt =3D 0; =20 if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) { @@ -1132,7 +1132,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) =20 void helper_store_lpcr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); =20 ppc_store_lpcr(cpu, val); } diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 2e8ffd7aaf..af216f81be 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -237,7 +237,6 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, t= arget_ulong eaddr, =20 static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); ppc6xx_tlb_t *tlb; int nr, max; =20 @@ -251,7 +250,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCStat= e *env) tlb =3D &env->tlb.tlb6[nr]; pte_invalidate(&tlb->pte0); } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, @@ -259,7 +258,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCSt= ate *env, int is_code, int match_epn) { #if !defined(FLUSH_ALL_TLBS) - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); ppc6xx_tlb_t *tlb; int way, nr; =20 @@ -469,7 +468,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t = *ctx, static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, int rw, int type) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); hwaddr hash; target_ulong vsid; int ds, pr, target_page_bits; @@ -659,7 +658,6 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_u= long address, /* Helpers specific to PowerPC 40x implementations */ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; int i; =20 @@ -667,7 +665,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCStat= e *env) tlb =3D &env->tlb.tlbe[i]; tlb->prot &=3D ~PAGE_VALID; } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, @@ -738,11 +736,10 @@ static int mmu40x_get_physical_address(CPUPPCState *e= nv, mmu_ctx_t *ctx, =20 void store_40x_sler(CPUPPCState *env, uint32_t val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - /* XXX: TO BE FIXED */ if (val !=3D 0x00000000) { - cpu_abort(CPU(cpu), "Little-endian regions are not supported by no= w\n"); + cpu_abort(env_cpu(env), + "Little-endian regions are not supported by now\n"); } env->spr[SPR_405_SLER] =3D val; } @@ -852,7 +849,6 @@ static int mmubooke_get_physical_address(CPUPPCState *e= nv, mmu_ctx_t *ctx, static void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); int tlb_size; int i, j; ppcmas_tlb_t *tlb =3D env->tlb.tlbm; @@ -869,7 +865,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int fl= ags, tlb +=3D booke206_tlb_size(env, i); } =20 - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 static hwaddr booke206_tlb_to_page_size(CPUPPCState *env, @@ -1267,7 +1263,7 @@ static void mmu6xx_dump_BATs(FILE *f, fprintf_functio= n cpu_fprintf, static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc6xx_tlb_t *tlb; target_ulong sr; int type, way, entry, i; @@ -1339,13 +1335,13 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf= , CPUPPCState *env) case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: case POWERPC_MMU_2_07: - dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env)); + dump_slb(f, cpu_fprintf, env_archcpu(env)); break; case POWERPC_MMU_3_00: - if (ppc64_v3_radix(ppc_env_get_cpu(env))) { + if (ppc64_v3_radix(env_archcpu(env))) { /* TODO - Unsupported */ } else { - dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env)); + dump_slb(f, cpu_fprintf, env_archcpu(env)); break; } #endif @@ -1410,7 +1406,6 @@ static int get_physical_address_wtlb( target_ulong eaddr, int rw, int access_type, int mmu_idx) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); int ret =3D -1; bool real_mode =3D (access_type =3D=3D ACCESS_CODE && msr_ir =3D=3D 0) || (access_type !=3D ACCESS_CODE && msr_dr =3D=3D 0); @@ -1451,17 +1446,18 @@ static int get_physical_address_wtlb( break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); + cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_REAL: if (real_mode) { ret =3D check_physical(env, ctx, eaddr, rw); } else { - cpu_abort(CPU(cpu), "PowerPC in real mode do not do any transl= ation\n"); + cpu_abort(env_cpu(env), + "PowerPC in real mode do not do any translation\n"); } return -1; default: - cpu_abort(CPU(cpu), "Unknown or invalid MMU model\n"); + cpu_abort(env_cpu(env), "Unknown or invalid MMU model\n"); return -1; } =20 @@ -1572,7 +1568,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState = *env, target_ulong address, static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int mmu_idx) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); PowerPCCPU *cpu =3D POWERPC_CPU(cs); mmu_ctx_t ctx; int access_type; @@ -1804,7 +1800,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,= target_ulong address, static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, target_ulong mask) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong base, end, page; =20 base =3D BATu & ~0x0001FFFF; @@ -1829,7 +1825,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr= , target_ulong value) { target_ulong mask; #if defined(FLUSH_ALL_TLBS) - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); #endif =20 dump_store_bat(env, 'I', 0, nr, value); @@ -1849,7 +1845,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr= , target_ulong value) #if !defined(FLUSH_ALL_TLBS) do_invalidate_BAT(env, env->IBAT[0][nr], mask); #else - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); #endif } } @@ -1864,7 +1860,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr= , target_ulong value) { target_ulong mask; #if defined(FLUSH_ALL_TLBS) - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); #endif =20 dump_store_bat(env, 'D', 0, nr, value); @@ -1884,7 +1880,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr= , target_ulong value) #if !defined(FLUSH_ALL_TLBS) do_invalidate_BAT(env, env->DBAT[0][nr], mask); #else - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); #endif } } @@ -1899,7 +1895,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t= nr, target_ulong value) { target_ulong mask; #if defined(FLUSH_ALL_TLBS) - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); int do_inval; #endif =20 @@ -1932,7 +1928,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t= nr, target_ulong value) } #if defined(FLUSH_ALL_TLBS) if (do_inval) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } #endif } @@ -1943,7 +1939,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t= nr, target_ulong value) #if !defined(FLUSH_ALL_TLBS) target_ulong mask; #else - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); int do_inval; #endif =20 @@ -1972,7 +1968,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t= nr, target_ulong value) env->DBAT[1][nr] =3D value; #if defined(FLUSH_ALL_TLBS) if (do_inval) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } #endif } @@ -1982,12 +1978,10 @@ void helper_store_601_batl(CPUPPCState *env, uint32= _t nr, target_ulong value) /* TLB management */ void ppc_tlb_invalidate_all(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { env->tlb_need_flush =3D 0; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } else #endif /* defined(TARGET_PPC64) */ switch (env->mmu_model) { @@ -2000,14 +1994,14 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) ppc4xx_tlb_invalidate_all(env); break; case POWERPC_MMU_REAL: - cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n"); + cpu_abort(env_cpu(env), "No TLB for PowerPC 4xx in real mode\n"); break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); + cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE: - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); break; case POWERPC_MMU_BOOKE206: booke206_flush_tlb(env, -1, 0); @@ -2015,11 +2009,11 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_32B: case POWERPC_MMU_601: env->tlb_need_flush =3D 0; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); break; default: /* XXX: TODO */ - cpu_abort(CPU(cpu), "Unknown MMU model %x\n", env->mmu_model); + cpu_abort(env_cpu(env), "Unknown MMU model %x\n", env->mmu_model); break; } } @@ -2068,7 +2062,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_= ulong addr) /* Special registers manipulation */ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value); assert(!cpu->vhyp); #if defined(TARGET_PPC64) @@ -2095,7 +2089,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong va= lue) #if defined(TARGET_PPC64) void ppc_store_ptcr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); target_ulong ptcr_mask =3D PTCR_PATB | PTCR_PATS; target_ulong patbsize =3D value & PTCR_PATS; =20 @@ -2140,7 +2134,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong s= rnum, target_ulong value) (int)srnum, value, env->sr[srnum]); #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); uint64_t esid, vsid; =20 /* ESID =3D srnum */ @@ -2165,7 +2159,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong s= rnum, target_ulong value) page =3D (16 << 20) * srnum; end =3D page + (16 << 20); for (; page !=3D end; page +=3D TARGET_PAGE_SIZE) { - tlb_flush_page(CPU(cpu), page); + tlb_flush_page(env_cpu(env), page); } } #else @@ -2187,12 +2181,10 @@ void helper_tlbie(CPUPPCState *env, target_ulong ad= dr) =20 void helper_tlbiva(CPUPPCState *env, target_ulong addr) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - /* tlbiva instruction only exists on BookE */ assert(env->mmu_model =3D=3D POWERPC_MMU_BOOKE); /* XXX: TODO */ - cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n"); + cpu_abort(env_cpu(env), "BookE MMU model is not implemented\n"); } =20 /* Software driven TLBs management */ @@ -2406,8 +2398,7 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, ta= rget_ulong entry) void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); ppcemb_tlb_t *tlb; target_ulong page, end; =20 @@ -2501,7 +2492,6 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, targe= t_ulong address) void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; target_ulong EPN, RPN, size; int do_flush_tlbs; @@ -2537,13 +2527,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t wo= rd, target_ulong entry, } tlb->PID =3D env->spr[SPR_440_MMUCR] & 0x000000FF; if (do_flush_tlbs) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } break; case 1: RPN =3D value & 0xFFFFFC0F; if ((tlb->prot & PAGE_VALID) && tlb->RPN !=3D RPN) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } tlb->RPN =3D RPN; break; @@ -2637,7 +2627,6 @@ target_ulong helper_440_tlbsx(CPUPPCState *env, targe= t_ulong address) =20 static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); uint32_t tlbncfg =3D 0; int esel =3D (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_= SHIFT; int ea =3D (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK); @@ -2647,7 +2636,7 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *en= v) tlbncfg =3D env->spr[SPR_BOOKE_TLB0CFG + tlb]; =20 if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) { - cpu_abort(CPU(cpu), "we don't support HES yet\n"); + cpu_abort(env_cpu(env), "we don't support HES yet\n"); } =20 return booke206_get_tlbm(env, tlb, ea, esel); @@ -2655,40 +2644,33 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *= env) =20 void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - env->spr[pidn] =3D pid; /* changing PIDs mean we're in a different address space now */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void helper_booke_set_eplc(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); env->spr[SPR_BOOKE_EPLC] =3D val & EPID_MASK; - tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_LOAD); + tlb_flush_by_mmuidx(env_cpu(env), 1 << PPC_TLB_EPID_LOAD); } void helper_booke_set_epsc(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); env->spr[SPR_BOOKE_EPSC] =3D val & EPID_MASK; - tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_STORE); + tlb_flush_by_mmuidx(env_cpu(env), 1 << PPC_TLB_EPID_STORE); } =20 static inline void flush_page(CPUPPCState *env, ppcmas_tlb_t *tlb) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - if (booke206_tlb_to_page_size(env, tlb) =3D=3D TARGET_PAGE_SIZE) { - tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK); + tlb_flush_page(env_cpu(env), tlb->mas2 & MAS2_EPN_MASK); } else { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 void helper_booke206_tlbwe(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); uint32_t tlbncfg, tlbn; ppcmas_tlb_t *tlb; uint32_t size_tlb, size_ps; @@ -2742,7 +2724,7 @@ void helper_booke206_tlbwe(CPUPPCState *env) } =20 if (msr_gs) { - cpu_abort(CPU(cpu), "missing HV implementation\n"); + cpu_abort(env_cpu(env), "missing HV implementation\n"); } =20 if (tlb->mas1 & MAS1_VALID) { @@ -2937,7 +2919,6 @@ void helper_booke206_tlbilx0(CPUPPCState *env, target= _ulong address) =20 void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); int i, j; int tid =3D (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); ppcmas_tlb_t *tlb =3D env->tlb.tlbm; @@ -2954,12 +2935,11 @@ void helper_booke206_tlbilx1(CPUPPCState *env, targ= et_ulong address) } tlb +=3D booke206_tlb_size(env, i); } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); int i, j; ppcmas_tlb_t *tlb; int tid =3D (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); @@ -2995,7 +2975,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target= _ulong address) tlb->mas1 &=3D ~MAS1_VALID; } } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void helper_booke206_tlbflush(CPUPPCState *env, target_ulong type) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index 0bd555eb19..a4ec7d81d7 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -3403,7 +3403,7 @@ static void init_proc_401(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3457,7 +3457,7 @@ static void init_proc_401x2(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3509,7 +3509,7 @@ static void init_proc_401x3(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3568,7 +3568,7 @@ static void init_proc_IOP480(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3619,7 +3619,7 @@ static void init_proc_403(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3685,7 +3685,7 @@ static void init_proc_403GCX(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3751,7 +3751,7 @@ static void init_proc_405(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3849,7 +3849,7 @@ static void init_proc_440EP(CPUPPCState *env) init_excp_BookE(env); env->dcache_line_size =3D 32; env->icache_line_size =3D 32; - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(20, 24, 28, 32); @@ -4157,7 +4157,7 @@ static void init_proc_440x5(CPUPPCState *env) init_excp_BookE(env); env->dcache_line_size =3D 32; env->icache_line_size =3D 32; - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(20, 24, 28, 32); @@ -4363,7 +4363,7 @@ static void init_proc_G2(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) @@ -4443,7 +4443,7 @@ static void init_proc_G2LE(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) @@ -4697,7 +4697,7 @@ static void init_proc_e300(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) @@ -4775,7 +4775,6 @@ enum fsl_e500_version { =20 static void init_proc_e500(CPUPPCState *env, int version) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); uint32_t tlbncfg[2]; uint64_t ivor_mask; uint64_t ivpr_mask =3D 0xFFFF0000ULL; @@ -4847,7 +4846,8 @@ static void init_proc_e500(CPUPPCState *env, int vers= ion) tlbncfg[1] =3D 0x40028040; break; default: - cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[S= PR_PVR]); + cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", + env->spr[SPR_PVR]); } #endif /* Cache sizes */ @@ -4871,7 +4871,8 @@ static void init_proc_e500(CPUPPCState *env, int vers= ion) l1cfg1 |=3D 0x0B83820; break; default: - cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[S= PR_PVR]); + cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", + env->spr[SPR_PVR]); } gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg); /* XXX : not implemented */ @@ -4986,7 +4987,7 @@ static void init_proc_e500(CPUPPCState *env, int vers= ion) =20 init_excp_e200(env, ivpr_mask); /* Allocate hardware IRQ controller */ - ppce500_irq_init(ppc_env_get_cpu(env)); + ppce500_irq_init(env_archcpu(env)); } =20 static void init_proc_e500v1(CPUPPCState *env) @@ -5258,7 +5259,7 @@ static void init_proc_601(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 64; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(601)(ObjectClass *oc, void *data) @@ -5363,7 +5364,7 @@ static void init_proc_602(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(602)(ObjectClass *oc, void *data) @@ -5433,7 +5434,7 @@ static void init_proc_603(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) @@ -5500,7 +5501,7 @@ static void init_proc_603E(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) @@ -5561,7 +5562,7 @@ static void init_proc_604(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) @@ -5645,7 +5646,7 @@ static void init_proc_604E(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) @@ -5716,7 +5717,7 @@ static void init_proc_740(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) @@ -5795,7 +5796,7 @@ static void init_proc_750(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) @@ -5959,7 +5960,7 @@ static void init_proc_750cl(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) @@ -6080,7 +6081,7 @@ static void init_proc_750cx(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) @@ -6168,7 +6169,7 @@ static void init_proc_750fx(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) @@ -6256,7 +6257,7 @@ static void init_proc_750gx(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) @@ -6335,7 +6336,7 @@ static void init_proc_745(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) @@ -6422,7 +6423,7 @@ static void init_proc_755(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) @@ -6492,7 +6493,7 @@ static void init_proc_7400(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) @@ -6577,7 +6578,7 @@ static void init_proc_7410(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) @@ -6688,7 +6689,7 @@ static void init_proc_7440(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) @@ -6822,7 +6823,7 @@ static void init_proc_7450(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) @@ -6959,7 +6960,7 @@ static void init_proc_7445(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) @@ -7098,7 +7099,7 @@ static void init_proc_7455(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) @@ -7261,7 +7262,7 @@ static void init_proc_7457(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) @@ -7399,7 +7400,7 @@ static void init_proc_e600(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) @@ -8261,7 +8262,7 @@ static void init_proc_970(CPUPPCState *env) =20 /* Allocate hardware IRQ controller */ init_excp_970(env); - ppc970_irq_init(ppc_env_get_cpu(env)); + ppc970_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) @@ -8335,7 +8336,7 @@ static void init_proc_power5plus(CPUPPCState *env) =20 /* Allocate hardware IRQ controller */ init_excp_970(env); - ppc970_irq_init(ppc_env_get_cpu(env)); + ppc970_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) @@ -8450,7 +8451,7 @@ static void init_proc_POWER7(CPUPPCState *env) =20 /* Allocate hardware IRQ controller */ init_excp_POWER7(env); - ppcPOWER7_irq_init(ppc_env_get_cpu(env)); + ppcPOWER7_irq_init(env_archcpu(env)); } =20 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) @@ -8602,7 +8603,7 @@ static void init_proc_POWER8(CPUPPCState *env) =20 /* Allocate hardware IRQ controller */ init_excp_POWER8(env); - ppcPOWER7_irq_init(ppc_env_get_cpu(env)); + ppcPOWER7_irq_init(env_archcpu(env)); } =20 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) @@ -8801,7 +8802,7 @@ static void init_proc_POWER9(CPUPPCState *env) =20 /* Allocate hardware IRQ controller */ init_excp_POWER9(env); - ppcPOWER9_irq_init(ppc_env_get_cpu(env)); + ppcPOWER9_irq_init(env_archcpu(env)); } =20 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553815925162723.6399813171272; Thu, 28 Mar 2019 16:32:05 -0700 (PDT) Received: from localhost ([127.0.0.1]:43330 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eV7-0003ip-4e for importer@patchew.org; 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH for-4.1 v2 21/36] target/riscv: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 ----- linux-user/riscv/cpu_loop.c | 2 +- target/riscv/cpu_helper.c | 4 ++-- target/riscv/csr.c | 12 ++++++------ target/riscv/op_helper.c | 8 ++++---- 5 files changed, 13 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e97f6c4889..c18dd5eb24 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -211,11 +211,6 @@ typedef struct RISCVCPU { CPURISCVState env; } RISCVCPU; =20 -static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env) -{ - return container_of(env, RISCVCPU, env); -} - static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { return (env->misa & ext) !=3D 0; diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 31700f75d0..c1134597fd 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -25,7 +25,7 @@ =20 void cpu_loop(CPURISCVState *env) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, signum, sigcode; target_ulong sigaddr; target_ulong ret; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b17f169681..72f82c1ccf 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -191,7 +191,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } } =20 - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int va_bits =3D PGSHIFT + levels * ptidxbits; target_ulong mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; target_ulong masked_msbs =3D (addr >> (va_bits - 1)) & mask; @@ -320,7 +320,7 @@ restart: static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int page_fault_exceptions =3D (env->priv_ver >=3D PRIV_VERSION_1_10_0) && get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e1d91b6c60..97a4e10e3e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -296,7 +296,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -307,7 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -382,7 +382,7 @@ static int write_misa(CPURISCVState *env, int csrno, ta= rget_ulong val) =20 /* flush translation cache */ if (val !=3D env->misa) { - tb_flush(CPU(riscv_env_get_cpu(env))); + tb_flush(env_cpu(env)); } =20 env->misa =3D val; @@ -549,7 +549,7 @@ static int write_mbadaddr(CPURISCVState *env, int csrno= , target_ulong val) static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - RISCVCPU *cpu =3D riscv_env_get_cpu(env); + RISCVCPU *cpu =3D env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardw= are */ target_ulong mask =3D write_mask & delegable_ints & ~env->miclaim; uint32_t old_mip; @@ -712,7 +712,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) return 0; } if (env->priv_ver <=3D PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); env->sptbr =3D val & (((target_ulong) 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); } @@ -723,7 +723,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { return -1; } else { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); env->satp =3D val; } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index b7dc18a41e..f078bafbe6 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -28,7 +28,7 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); cs->exception_index =3D exception; cpu_loop_exit_restore(cs, pc); @@ -128,7 +128,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) =20 void helper_wfi(CPURISCVState *env) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && @@ -143,8 +143,8 @@ void helper_wfi(CPURISCVState *env) =20 void helper_tlb_flush(CPURISCVState *env) { - RISCVCPU *cpu =3D riscv_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); + if (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && get_field(env->mstatus, MSTATUS_TVM)) { --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553816131647164.97060438210713; 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X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PATCH for-4.1 v2 22/36] target/s390x: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/s390x/cpu.h | 5 ---- linux-user/s390x/cpu_loop.c | 2 +- target/s390x/cc_helper.c | 5 ++-- target/s390x/diag.c | 2 +- target/s390x/excp_helper.c | 6 ++--- target/s390x/fpu_helper.c | 4 +-- target/s390x/helper.c | 7 +++--- target/s390x/int_helper.c | 3 +-- target/s390x/interrupt.c | 6 ++--- target/s390x/mem_helper.c | 28 ++++++++------------- target/s390x/misc_helper.c | 50 ++++++++++++++++++------------------- target/s390x/mmu_helper.c | 8 +++--- target/s390x/sigp.c | 4 +-- 13 files changed, 56 insertions(+), 74 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 3dd60c5346..372d4c198f 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -163,11 +163,6 @@ struct S390CPU { uint32_t irqstate_saved_size; }; =20 -static inline S390CPU *s390_env_get_cpu(CPUS390XState *env) -{ - return container_of(env, S390CPU, env); -} - #define ENV_OFFSET offsetof(S390CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index 51b5412ea2..1050f6923c 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -26,7 +26,7 @@ =20 void cpu_loop(CPUS390XState *env) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, n, sig; target_siginfo_t info; target_ulong addr; diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c index 0e467bf2b6..e9732500ad 100644 --- a/target/s390x/cc_helper.c +++ b/target/s390x/cc_helper.c @@ -405,7 +405,6 @@ static uint32_t cc_calc_lcbb(uint64_t dst) static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst, uint64_t vr) { - S390CPU *cpu =3D s390_env_get_cpu(env); uint32_t r =3D 0; =20 switch (cc_op) { @@ -526,7 +525,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t= cc_op, break; =20 default: - cpu_abort(CPU(cpu), "Unknown CC operation: %s\n", cc_name(cc_op)); + cpu_abort(env_cpu(env), "Unknown CC operation: %s\n", cc_name(cc_o= p)); } =20 HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx =3D %d\n", __func__, @@ -550,7 +549,7 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t c= c_op, uint64_t src, void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr) { load_psw(env, mask, addr); - cpu_loop_exit(CPU(s390_env_get_cpu(env))); + cpu_loop_exit(env_cpu(env)); } =20 void HELPER(sacf)(CPUS390XState *env, uint64_t a1) diff --git a/target/s390x/diag.c b/target/s390x/diag.c index aafa740f61..65eabf0461 100644 --- a/target/s390x/diag.c +++ b/target/s390x/diag.c @@ -55,7 +55,7 @@ int handle_diag_288(CPUS390XState *env, uint64_t r1, uint= 64_t r3) =20 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr= _t ra) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint64_t addr =3D env->regs[r1]; uint64_t subcode =3D env->regs[r3]; IplParameterBlock *iplb; diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index f84bfb1284..b83c1e6559 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -36,7 +36,7 @@ void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, uint32_t= code, int ilen, uintptr_t ra) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cpu_restore_state(cs, ra, true); qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n", @@ -51,7 +51,7 @@ void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState = *env, uint32_t dxc, g_assert(dxc <=3D 0xff); #if !defined(CONFIG_USER_ONLY) /* Store the DXC into the lowcore */ - stl_phys(CPU(s390_env_get_cpu(env))->as, + stl_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, data_exc_code), dxc); #endif =20 @@ -261,7 +261,7 @@ static void do_svc_interrupt(CPUS390XState *env) static void do_ext_interrupt(CPUS390XState *env) { QEMUS390FLICState *flic =3D QEMU_S390_FLIC(s390_get_flic()); - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); uint64_t mask, addr; uint16_t cpu_addr; LowCore *lowcore; diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index 1be68bafea..906fa8ce99 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -114,8 +114,6 @@ static void handle_exceptions(CPUS390XState *env, bool = XxC, uintptr_t retaddr) =20 static inline int float_comp_to_cc(CPUS390XState *env, int float_compare) { - S390CPU *cpu =3D s390_env_get_cpu(env); - switch (float_compare) { case float_relation_equal: return 0; @@ -126,7 +124,7 @@ static inline int float_comp_to_cc(CPUS390XState *env, = int float_compare) case float_relation_unordered: return 3; default: - cpu_abort(CPU(cpu), "unknown return value for float compare\n"); + cpu_abort(env_cpu(env), "unknown return value for float compare\n"= ); } } =20 diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 8e9573221c..0d28482cc6 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -110,11 +110,11 @@ void load_psw(CPUS390XState *env, uint64_t mask, uint= 64_t addr) env->cc_op =3D (mask >> 44) & 3; =20 if ((old_mask ^ mask) & PSW_MASK_PER) { - s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env))); + s390_cpu_recompute_watchpoints(env_cpu(env)); } =20 if (mask & PSW_MASK_WAIT) { - s390_handle_wait(s390_env_get_cpu(env)); + s390_handle_wait(env_archcpu(env)); } } =20 @@ -136,14 +136,13 @@ uint64_t get_psw_mask(CPUS390XState *env) =20 LowCore *cpu_map_lowcore(CPUS390XState *env) { - S390CPU *cpu =3D s390_env_get_cpu(env); LowCore *lowcore; hwaddr len =3D sizeof(LowCore); =20 lowcore =3D cpu_physical_memory_map(env->psa, &len, 1); =20 if (len < sizeof(LowCore)) { - cpu_abort(CPU(cpu), "Could not map lowcore\n"); + cpu_abort(env_cpu(env), "Could not map lowcore\n"); } =20 return lowcore; diff --git a/target/s390x/int_helper.c b/target/s390x/int_helper.c index abbbc20d9c..d13cc49be6 100644 --- a/target/s390x/int_helper.c +++ b/target/s390x/int_helper.c @@ -109,10 +109,9 @@ uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t a= h, uint64_t al, s390_program_interrupt(env, PGM_FIXPT_DIVIDE, ILEN_AUTO, GETPC= ()); } #else - S390CPU *cpu =3D s390_env_get_cpu(env); /* 32-bit hosts would need special wrapper functionality - just ab= ort if we encounter such a case; it's very unlikely anyways. */ - cpu_abort(CPU(cpu), "128 -> 64/64 division not implemented\n"); + cpu_abort(env_cpu(env), "128 -> 64/64 division not implemented\n"); #endif } return ret; diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c index a17eff5ebc..a8f9b38795 100644 --- a/target/s390x/interrupt.c +++ b/target/s390x/interrupt.c @@ -23,7 +23,7 @@ /* Ensure to exit the TB after this call! */ void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ile= n) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_PGM; env->int_pgm_code =3D code; @@ -33,10 +33,8 @@ void trigger_pgm_exception(CPUS390XState *env, uint32_t = code, uint32_t ilen) void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen, uintptr_t ra) { - S390CPU *cpu =3D s390_env_get_cpu(env); - if (kvm_enabled()) { - kvm_s390_program_interrupt(cpu, code); + kvm_s390_program_interrupt(env_archcpu(env), code); } else if (tcg_enabled()) { tcg_s390_program_interrupt(env, code, ilen, ra); } else { diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index e2992deb2f..f02eb85d30 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1633,7 +1633,6 @@ uint32_t HELPER(csst_parallel)(CPUS390XState *env, ui= nt32_t r3, uint64_t a1, void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) { uintptr_t ra =3D GETPC(); - S390CPU *cpu =3D s390_env_get_cpu(env); bool PERchanged =3D false; uint64_t src =3D a2; uint32_t i; @@ -1658,16 +1657,15 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1,= uint64_t a2, uint32_t r3) } =20 if (PERchanged && env->psw.mask & PSW_MASK_PER) { - s390_cpu_recompute_watchpoints(CPU(cpu)); + s390_cpu_recompute_watchpoints(env_cpu(env)); } =20 - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r= 3) { uintptr_t ra =3D GETPC(); - S390CPU *cpu =3D s390_env_get_cpu(env); bool PERchanged =3D false; uint64_t src =3D a2; uint32_t i; @@ -1691,10 +1689,10 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, = uint64_t a2, uint32_t r3) } =20 if (PERchanged && env->psw.mask & PSW_MASK_PER) { - s390_cpu_recompute_watchpoints(CPU(cpu)); + s390_cpu_recompute_watchpoints(env_cpu(env)); } =20 - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) @@ -1753,8 +1751,8 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64= _t real_addr) =20 uint32_t HELPER(tprot)(CPUS390XState *env, uint64_t a1, uint64_t a2) { - S390CPU *cpu =3D s390_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + S390CPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 /* * TODO: we currently don't handle all access protection types @@ -1922,7 +1920,7 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l,= uint64_t a1, uint64_t a2) =20 void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m= 4) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); const uintptr_t ra =3D GETPC(); uint64_t table, entry, raddr; uint16_t entries, i, index =3D 0; @@ -1974,7 +1972,7 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, ui= nt64_t r2, uint32_t m4) void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr, uint32_t m4) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); const uintptr_t ra =3D GETPC(); uint64_t page =3D vaddr & TARGET_PAGE_MASK; uint64_t pte_addr, pte; @@ -2014,17 +2012,13 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto,= uint64_t vaddr, /* flush local tlb */ void HELPER(ptlb)(CPUS390XState *env) { - S390CPU *cpu =3D s390_env_get_cpu(env); - - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 /* flush global tlb */ void HELPER(purge)(CPUS390XState *env) { - S390CPU *cpu =3D s390_env_get_cpu(env); - - tlb_flush_all_cpus_synced(CPU(cpu)); + tlb_flush_all_cpus_synced(env_cpu(env)); } =20 /* load using real address */ @@ -2068,7 +2062,7 @@ void HELPER(sturg)(CPUS390XState *env, uint64_t addr,= uint64_t v1) /* load real address */ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t cc =3D 0; uint64_t asc =3D env->psw.mask & PSW_MASK_ASC; uint64_t ret; diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index ee67c1fa0c..c806c3ec00 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -55,7 +55,7 @@ /* Raise an exception statically from a TB. */ void HELPER(exception)(CPUS390XState *env, uint32_t excp) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 HELPER_LOG("%s: exception %d\n", __func__, excp); cs->exception_index =3D excp; @@ -150,7 +150,7 @@ void HELPER(diag)(CPUS390XState *env, uint32_t r1, uint= 32_t r3, uint32_t num) /* Set Prefix */ void HELPER(spx)(CPUS390XState *env, uint64_t a1) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t prefix =3D a1 & 0x7fffe000; =20 env->psa =3D prefix; @@ -256,7 +256,7 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, = uint64_t r0, uint64_t r1) const uint32_t sel2 =3D r1 & STSI_R1_SEL2_MASK; const MachineState *ms =3D MACHINE(qdev_get_machine()); uint16_t total_cpus =3D 0, conf_cpus =3D 0, reserved_cpus =3D 0; - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); SysIB sysib =3D { }; int i, cc =3D 0; =20 @@ -411,7 +411,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t orde= r_code, uint32_t r1, #ifndef CONFIG_USER_ONLY void HELPER(xsch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_xsch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -419,7 +419,7 @@ void HELPER(xsch)(CPUS390XState *env, uint64_t r1) =20 void HELPER(csch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_csch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -427,7 +427,7 @@ void HELPER(csch)(CPUS390XState *env, uint64_t r1) =20 void HELPER(hsch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_hsch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -435,7 +435,7 @@ void HELPER(hsch)(CPUS390XState *env, uint64_t r1) =20 void HELPER(msch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_msch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -443,7 +443,7 @@ void HELPER(msch)(CPUS390XState *env, uint64_t r1, uint= 64_t inst) =20 void HELPER(rchp)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_rchp(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -451,7 +451,7 @@ void HELPER(rchp)(CPUS390XState *env, uint64_t r1) =20 void HELPER(rsch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_rsch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -459,7 +459,7 @@ void HELPER(rsch)(CPUS390XState *env, uint64_t r1) =20 void HELPER(sal)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); ioinst_handle_sal(cpu, r1, GETPC()); @@ -468,7 +468,7 @@ void HELPER(sal)(CPUS390XState *env, uint64_t r1) =20 void HELPER(schm)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint64_t i= nst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); ioinst_handle_schm(cpu, r1, r2, inst >> 16, GETPC()); @@ -477,7 +477,7 @@ void HELPER(schm)(CPUS390XState *env, uint64_t r1, uint= 64_t r2, uint64_t inst) =20 void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_ssch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -485,7 +485,7 @@ void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint= 64_t inst) =20 void HELPER(stcrw)(CPUS390XState *env, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); ioinst_handle_stcrw(cpu, inst >> 16, GETPC()); @@ -494,7 +494,7 @@ void HELPER(stcrw)(CPUS390XState *env, uint64_t inst) =20 void HELPER(stsch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_stsch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -503,7 +503,7 @@ void HELPER(stsch)(CPUS390XState *env, uint64_t r1, uin= t64_t inst) uint32_t HELPER(tpi)(CPUS390XState *env, uint64_t addr) { const uintptr_t ra =3D GETPC(); - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); QEMUS390FlicIO *io =3D NULL; LowCore *lowcore; @@ -555,7 +555,7 @@ uint32_t HELPER(tpi)(CPUS390XState *env, uint64_t addr) =20 void HELPER(tsch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_tsch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -563,7 +563,7 @@ void HELPER(tsch)(CPUS390XState *env, uint64_t r1, uint= 64_t inst) =20 void HELPER(chsc)(CPUS390XState *env, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_chsc(cpu, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -618,7 +618,7 @@ void HELPER(per_ifetch)(CPUS390XState *env, uint64_t ad= dr) /* If the instruction has to be nullified, trigger the exception immediately. */ if (env->cregs[9] & PER_CR9_EVENT_NULLIFICATION) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->per_perc_atmid |=3D PER_CODE_EVENT_NULLIFICATION; env->int_pgm_code =3D PGM_PER; @@ -695,7 +695,7 @@ uint32_t HELPER(stfle)(CPUS390XState *env, uint64_t add= r) */ void HELPER(clp)(CPUS390XState *env, uint32_t r2) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); clp_service_call(cpu, r2, GETPC()); @@ -704,7 +704,7 @@ void HELPER(clp)(CPUS390XState *env, uint32_t r2) =20 void HELPER(pcilg)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); pcilg_service_call(cpu, r1, r2, GETPC()); @@ -713,7 +713,7 @@ void HELPER(pcilg)(CPUS390XState *env, uint32_t r1, uin= t32_t r2) =20 void HELPER(pcistg)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); pcistg_service_call(cpu, r1, r2, GETPC()); @@ -723,7 +723,7 @@ void HELPER(pcistg)(CPUS390XState *env, uint32_t r1, ui= nt32_t r2) void HELPER(stpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba, uint32_t ar) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); stpcifc_service_call(cpu, r1, fiba, ar, GETPC()); @@ -745,7 +745,7 @@ void HELPER(sic)(CPUS390XState *env, uint64_t r1, uint6= 4_t r3) =20 void HELPER(rpcit)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); rpcit_service_call(cpu, r1, r2, GETPC()); @@ -755,7 +755,7 @@ void HELPER(rpcit)(CPUS390XState *env, uint32_t r1, uin= t32_t r2) void HELPER(pcistb)(CPUS390XState *env, uint32_t r1, uint32_t r3, uint64_t gaddr, uint32_t ar) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); pcistb_service_call(cpu, r1, r3, gaddr, ar, GETPC()); @@ -765,7 +765,7 @@ void HELPER(pcistb)(CPUS390XState *env, uint32_t r1, ui= nt32_t r3, void HELPER(mpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba, uint32_t ar) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); mpcifc_service_call(cpu, r1, fiba, ar, GETPC()); diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 145b62a7ef..9669bae393 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -58,12 +58,12 @@ static void trigger_access_exception(CPUS390XState *env, uint32_t type, uint32_t ilen, uint64_t tec) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 if (kvm_enabled()) { kvm_s390_access_exception(cpu, type, tec); } else { - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); if (type !=3D PGM_ADDRESSING) { stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code),= tec); } @@ -185,7 +185,7 @@ static int mmu_translate_segment(CPUS390XState *env, ta= rget_ulong vaddr, target_ulong *raddr, int *flags, int rw, bool exc) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint64_t origin, offs, pt_entry; =20 if (st_entry & SEGMENT_ENTRY_RO) { @@ -214,7 +214,7 @@ static int mmu_translate_region(CPUS390XState *env, tar= get_ulong vaddr, target_ulong *raddr, int *flags, int rw, bool exc) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint64_t origin, offs, new_entry; const int pchks[4] =3D { PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS, diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index c1f9245797..ea5f69d5d8 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -454,7 +454,7 @@ int handle_sigp(CPUS390XState *env, uint8_t order, uint= 64_t r1, uint64_t r3) { uint64_t *status_reg =3D &env->regs[r1]; uint64_t param =3D (r1 % 2) ? env->regs[r1] : env->regs[r1 + 1]; - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); S390CPU *dst_cpu =3D NULL; int ret; =20 @@ -492,7 +492,7 @@ int s390_cpu_restart(S390CPU *cpu) =20 void do_stop_interrupt(CPUS390XState *env) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 if (s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu) =3D=3D 0) { qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=lDDnFZO5czCmaUbb1PZG7cNuDrH2EEa4yiXRXIIuvqw=; b=TgyJ1Gz42FRnyrZFuBqyT7zPriCNucYR557o0epWMbjlLapB7OxjynMkFzIKVH2G50 JB5c9xUD0pQn8NtTCv1X+SKzrkDMecvGOPboLZ6EZssoitVmQTCY9JT3YWMwCI+/L+z4 tWJRwyHQUSAb3l151bEkitt+mgViFdfifCUz4gbXZ5Su3EPjkXzUnQLXigHw8tCUHzOZ 7XdurUjwklbkRmMHx5xdoXiemptonkhCbfWZq23XKN9YkIHis48I/lbH/skTREXVbzUg MwP08/ZsYLMubatzQI3Z2kG7oX8BKLlxoqa7CywU4YhB7w5STebcW1uRa6DLu01lr48J dqvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=lDDnFZO5czCmaUbb1PZG7cNuDrH2EEa4yiXRXIIuvqw=; b=T6lReYgWyWIJQqxHXeQxTnps3lSImMfTbign+FV3rdjfOGioTXzWs3HE/x/dR4z9uI DpD9ag+0EiHIREnyvuIIiGM/U9u9JncvJXeVHxbNKSQ2Szyh9EjX4ZdlRNctBHFpxQ1d HhSp4s3sVkVMnCk82xR/VmFfQQy12kjZutCe6IgpnW08UrZ7wdT3njBwaYpNQMO2dvkl VpmGAHZpvJMW9qgb8uI41K+LjzyeAKUo+T2iVQtTulC14BiS8nFvAn8zBYFR9VZUSYLT qesGcjplt54wZzxpQkA+PadIof6AvMf5krn+l+nkzqk01Csp3wWrPIIcR6u8IcFV5VX/ ifgQ== X-Gm-Message-State: APjAAAXm5efPqqmJoWOHh5oalr4cVmSM+ayeylLFVtOtdGbbHoUmqXbX GdLPbb7hIn91Lp17UwuDXPiQv29sWWY= X-Google-Smtp-Source: APXvYqxHI+GTZaoFh2hCtKS8JpGDddenSKaNc3aJzDsJpfN349XgtBRiGkDrVCVYxqRdS4iW/jFIgw== X-Received: by 2002:a62:449b:: with SMTP id m27mr44209807pfi.79.1553814285706; Thu, 28 Mar 2019 16:04:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:51 -1000 Message-Id: <20190328230404.12909-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH for-4.1 v2 23/36] target/sh4: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/sh4/cpu.h | 5 ----- linux-user/sh4/cpu_loop.c | 2 +- target/sh4/helper.c | 26 ++++++++++++-------------- target/sh4/op_helper.c | 9 +++------ 4 files changed, 16 insertions(+), 26 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 95094a517a..1f94e7bf7b 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -207,11 +207,6 @@ struct SuperHCPU { CPUSH4State env; }; =20 -static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env) -{ - return container_of(env, SuperHCPU, env); -} - #define ENV_OFFSET offsetof(SuperHCPU, env) =20 void superh_cpu_do_interrupt(CPUState *cpu); diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 47e54b9b61..677c5a461c 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUSH4State *env) { - CPUState *cs =3D CPU(sh_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, ret; target_siginfo_t info; =20 diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 2ff0cf4060..5240da715e 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -238,8 +238,6 @@ static void update_itlb_use(CPUSH4State * env, int itlb= nb) =20 static int itlb_replacement(CPUSH4State * env) { - SuperHCPU *cpu =3D sh_env_get_cpu(env); - if ((env->mmucr & 0xe0000000) =3D=3D 0xe0000000) { return 0; } @@ -252,7 +250,7 @@ static int itlb_replacement(CPUSH4State * env) if ((env->mmucr & 0x2c000000) =3D=3D 0x00000000) { return 3; } - cpu_abort(CPU(cpu), "Unhandled itlb_replacement"); + cpu_abort(env_cpu(env), "Unhandled itlb_replacement"); } =20 /* Find the corresponding entry in the right TLB @@ -308,7 +306,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int u= tlb) itlb =3D itlb_replacement(env); ientry =3D &env->itlb[itlb]; if (ientry->v) { - tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10); + tlb_flush_page(env_cpu(env), ientry->vpn << 10); } *ientry =3D env->utlb[utlb]; update_itlb_use(env, itlb); @@ -533,14 +531,14 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, v= addr addr) =20 void cpu_load_tlb(CPUSH4State * env) { - SuperHCPU *cpu =3D sh_env_get_cpu(env); + CPUState *cs =3D env_cpu(env); int n =3D cpu_mmucr_urc(env->mmucr); tlb_t * entry =3D &env->utlb[n]; =20 if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(CPU(cpu), address); + tlb_flush_page(cs, address); } =20 /* Take values into cpu status from registers. */ @@ -563,7 +561,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->size =3D 1024 * 1024; /* 1M */ break; default: - cpu_abort(CPU(cpu), "Unhandled load_tlb"); + cpu_abort(cs, "Unhandled load_tlb"); break; } entry->sh =3D (uint8_t)cpu_ptel_sh(env->ptel); @@ -590,7 +588,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->v =3D 0; } =20 - tlb_flush(CPU(sh_env_get_cpu(s))); + tlb_flush(env_cpu(s)); } =20 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, @@ -616,7 +614,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwa= ddr addr, if (entry->v) { /* Overwriting valid entry in itlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(CPU(sh_env_get_cpu(s)), address); + tlb_flush_page(env_cpu(s), address); } entry->asid =3D asid; entry->vpn =3D vpn; @@ -658,7 +656,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwa= ddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(CPU(sh_env_get_cpu(s)), address); + tlb_flush_page(env_cpu(s), address); } entry->ppn =3D (mem_value & 0x1ffffc00) >> 10; entry->v =3D (mem_value & 0x00000100) >> 8; @@ -711,7 +709,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwa= ddr addr, if (entry->vpn =3D=3D vpn && (!use_asid || entry->asid =3D=3D asid || entry->sh)) { if (utlb_match_entry) { - CPUState *cs =3D CPU(sh_env_get_cpu(s)); + CPUState *cs =3D env_cpu(s); =20 /* Multiple TLB Exception */ cs->exception_index =3D 0x140; @@ -743,14 +741,14 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, h= waddr addr, } =20 if (needs_tlb_flush) { - tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10); + tlb_flush_page(env_cpu(s), vpn << 10); } =20 } else { int index =3D (addr & 0x00003f00) >> 8; tlb_t * entry =3D &s->utlb[index]; if (entry->v) { - CPUState *cs =3D CPU(sh_env_get_cpu(s)); + CPUState *cs =3D env_cpu(s); =20 /* Overwriting valid entry in utlb. */ target_ulong address =3D entry->vpn << 10; @@ -805,7 +803,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwa= ddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(CPU(sh_env_get_cpu(s)), address); + tlb_flush_page(env_cpu(s), address); } entry->ppn =3D (mem_value & 0x1ffffc00) >> 10; entry->v =3D (mem_value & 0x00000100) >> 8; diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 12fba6fc78..11cb68cc1c 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -58,10 +58,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, void helper_ldtlb(CPUSH4State *env) { #ifdef CONFIG_USER_ONLY - SuperHCPU *cpu =3D sh_env_get_cpu(env); - - /* XXXXX */ - cpu_abort(CPU(cpu), "Unhandled ldtlb"); + cpu_abort(env_cpu(env), "Unhandled ldtlb"); #else cpu_load_tlb(env); #endif @@ -70,7 +67,7 @@ void helper_ldtlb(CPUSH4State *env) static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int ind= ex, uintptr_t retaddr) { - CPUState *cs =3D CPU(sh_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D index; cpu_loop_exit_restore(cs, retaddr); @@ -103,7 +100,7 @@ void helper_debug(CPUSH4State *env) =20 void helper_sleep(CPUSH4State *env) { - CPUState *cs =3D CPU(sh_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->halted =3D 1; env->in_sleep =3D 1; --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15538165574100.3237974052364052; Thu, 28 Mar 2019 16:42:37 -0700 (PDT) Received: from localhost ([127.0.0.1]:43486 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9efJ-0004Qj-Cb for importer@patchew.org; Thu, 28 Mar 2019 19:42:33 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKn-0001km-Dr for qemu-devel@nongnu.org; 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[66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.45 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=NqgSOXhXolZXrIMYfvxOnHd1zMf1TJYOvXcwGU7s/3U=; b=m0GVRIUxhwqmJ/p6DybFhTLYUXy6z3elj//aZWtTmAdfk7rqNyDJ6HoQPJGObz5zTS oprpKCY2O+Nee4rpGB0+bF0rVetjBJNIi0055fSUglv0WDNC+1kTEM0E1zphIUHkMNlH laJ7DxOqZrwIl0fUUtxrFv3rbQr3R5BhHZ91AhlLXP8353ZPZ4RLbrNlEmIXI24whcB0 UhO5FZJ7FQ97gmrWQvjCpS6ChssatyycdzF0WljFbI5WIDKuDNtN0gm817WXVt+xURXu ut66fviZa/9BN0YklN671q+TiY8poKuXSn6bZxYzf/yZH+Ol+vOc3HLdQy0Dxz4HhYxR GT6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=NqgSOXhXolZXrIMYfvxOnHd1zMf1TJYOvXcwGU7s/3U=; b=DgZGs4dEsymbwb2SIi8Etuu8FYZOKX472yrZisG/XT8ASfIqxnrhZWPMFWCAKPVoAU co1B3pMyYFjGGs5TtTOIV61eo6DSPQ1KSSwF+J8ggX+e/VPlKm8BYneeYjgk/ZXL3E2T mCnXooufD0uOGyaDS7tRTLKtRzPMnA2A7Yyehpvb/6rP8wE66u1b3HcF3mOCvLl00Wpx Xs8QARWM0zdn6iQeHlUSUFJs9yvWcOplIyl6zO8jgYGSMpV4PIH6ZtjLOdk6eoEsruwG rPoz193T7uV7C8lMV4IDho8IPmrKfm1ix9ty+sxolxwiXrKOLsACfCSkeqTqQuFZAX6s LPvA== X-Gm-Message-State: APjAAAU+kuebwtm1D6qglNFgP4V1TbRDjzYk9B8ePFdViETWEj+bbFJu PcGYDIX10y1toxY+UBE3skS3dynOOBU= X-Google-Smtp-Source: APXvYqykZmUCRGzbBAkTUEnPi8BuyvQJqvKI4xcp88s5dpOHzsWi+CI3B6l4Ihu0hNr5hk5lSS54bQ== X-Received: by 2002:a63:df4d:: with SMTP id h13mr42042426pgj.220.1553814287130; Thu, 28 Mar 2019 16:04:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:52 -1000 Message-Id: <20190328230404.12909-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.1 v2 24/36] target/sparc: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/sparc/cpu.h | 5 ----- bsd-user/main.c | 2 +- hw/sparc/leon3.c | 4 ++-- hw/sparc/sun4m.c | 4 ++-- hw/sparc64/sparc64.c | 2 +- linux-user/sparc/cpu_loop.c | 2 +- target/sparc/fop_helper.c | 2 +- target/sparc/helper.c | 8 ++++---- target/sparc/ldst_helper.c | 33 +++++++++++++++------------------ target/sparc/mmu_helper.c | 10 +++++----- 10 files changed, 32 insertions(+), 40 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 77dec0d865..bf6f63d029 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -532,11 +532,6 @@ struct SPARCCPU { CPUSPARCState env; }; =20 -static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) -{ - return container_of(env, SPARCCPU, env); -} - #define ENV_OFFSET offsetof(SPARCCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/bsd-user/main.c b/bsd-user/main.c index e554ebdfb3..7a0eb316a2 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -485,7 +485,7 @@ static void flush_windows(CPUSPARCState *env) =20 void cpu_loop(CPUSPARCState *env) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, ret, syscall_nr; //target_siginfo_t info; =20 diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 774639af33..ef74bc81c2 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -91,7 +91,7 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil_i= n) =20 env->interrupt_index =3D TT_EXTINT | i; if (old_interrupt !=3D env->interrupt_index) { - cs =3D CPU(sparc_env_get_cpu(env)); + cs =3D env_cpu(env); trace_leon3_set_irq(i); cpu_interrupt(cs, CPU_INTERRUPT_HARD); } @@ -99,7 +99,7 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil_i= n) } } } else if (!env->pil_in && (env->interrupt_index & ~15) =3D=3D TT_EXTI= NT) { - cs =3D CPU(sparc_env_get_cpu(env)); + cs =3D env_cpu(env); trace_leon3_reset_irq(env->interrupt_index & 15); env->interrupt_index =3D 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index ca1e3825d5..a87bef6d4f 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -147,7 +147,7 @@ void cpu_check_irqs(CPUSPARCState *env) =20 env->interrupt_index =3D TT_EXTINT | i; if (old_interrupt !=3D env->interrupt_index) { - cs =3D CPU(sparc_env_get_cpu(env)); + cs =3D env_cpu(env); trace_sun4m_cpu_interrupt(i); cpu_interrupt(cs, CPU_INTERRUPT_HARD); } @@ -155,7 +155,7 @@ void cpu_check_irqs(CPUSPARCState *env) } } } else if (!env->pil_in && (env->interrupt_index & ~15) =3D=3D TT_EXTI= NT) { - cs =3D CPU(sparc_env_get_cpu(env)); + cs =3D env_cpu(env); trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); env->interrupt_index =3D 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index 408388945e..689801f37d 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -46,7 +46,7 @@ void cpu_check_irqs(CPUSPARCState *env) if (env->ivec_status & 0x20) { return; } - cs =3D CPU(sparc_env_get_cpu(env)); + cs =3D env_cpu(env); /* check if TM or SM in SOFTINT are set setting these also causes interrupt 14 */ if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 7d5b337b97..7a4f5792be 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -145,7 +145,7 @@ static void flush_windows(CPUSPARCState *env) =20 void cpu_loop (CPUSPARCState *env) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; abi_long ret; target_siginfo_t info; diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index b6642fd1d7..9eb9b75718 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -53,7 +53,7 @@ static target_ulong do_check_ieee_exceptions(CPUSPARCStat= e *env, uintptr_t ra) } =20 if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* Unmasked exception, generate a trap. Note that while the helper is marked as NO_WG, we can get away with diff --git a/target/sparc/helper.c b/target/sparc/helper.c index 46232788c8..1a52061fbf 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -26,7 +26,7 @@ =20 void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D tt; cpu_loop_exit_restore(cs, ra); @@ -34,7 +34,7 @@ void cpu_raise_exception_ra(CPUSPARCState *env, int tt, u= intptr_t ra) =20 void helper_raise_exception(CPUSPARCState *env, int tt) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D tt; cpu_loop_exit(cs); @@ -42,7 +42,7 @@ void helper_raise_exception(CPUSPARCState *env, int tt) =20 void helper_debug(CPUSPARCState *env) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_DEBUG; cpu_loop_exit(cs); @@ -243,7 +243,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target= _ulong src1, #ifndef TARGET_SPARC64 void helper_power_down(CPUSPARCState *env) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 5bc090213c..861b420c3e 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -122,13 +122,13 @@ static uint64_t ultrasparc_tag_target(uint64_t tag_ac= cess_register) =20 static void replace_tlb_entry(SparcTLBEntry *tlb, uint64_t tlb_tag, uint64_t tlb_tte, - CPUSPARCState *env1) + CPUSPARCState *env) { target_ulong mask, size, va, offset; =20 /* flush page range if translation is valid */ if (TTE_IS_VALID(tlb->tte)) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env1)); + CPUState *cs =3D env_cpu(env); =20 size =3D 8192ULL << 3 * TTE_PGSIZE(tlb->tte); mask =3D 1ULL + ~size; @@ -499,7 +499,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong= addr, { int size =3D 1 << (memop & MO_SIZE); int sign =3D memop & MO_SIGN; - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint64_t ret =3D 0; #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) uint32_t last_addr =3D addr; @@ -725,8 +725,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong add= r, uint64_t val, int asi, uint32_t memop) { int size =3D 1 << (memop & MO_SIZE); - SPARCCPU *cpu =3D sparc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 do_check_align(env, addr, size - 1, GETPC()); switch (asi) { @@ -874,13 +873,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, uint64_t val, DPRINTF_MMU("mmu flush level %d\n", mmulev); switch (mmulev) { case 0: /* flush page */ - tlb_flush_page(CPU(cpu), addr & 0xfffff000); + tlb_flush_page(cs, addr & 0xfffff000); break; case 1: /* flush segment (256k) */ case 2: /* flush region (16M) */ case 3: /* flush context (4G) */ case 4: /* flush entire */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; default: break; @@ -905,7 +904,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong add= r, uint64_t val, are invalid in normal mode. */ if ((oldreg ^ env->mmuregs[reg]) & (MMU_NF | env->def.mmu_bm)) { - tlb_flush(CPU(cpu)); + tlb_flush(cs); } break; case 1: /* Context Table Pointer Register */ @@ -916,7 +915,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong add= r, uint64_t val, if (oldreg !=3D env->mmuregs[reg]) { /* we flush when the MMU context changes because QEMU has no MMU context support */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); } break; case 3: /* Synchronous Fault Status Register with Clear */ @@ -1027,8 +1026,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, uint64_t val, case ASI_USERTXT: /* User code access, XXX */ case ASI_KERNELTXT: /* Supervisor code access, XXX */ default: - cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), - addr, true, false, asi, size); + cpu_unassigned_access(cs, addr, true, false, asi, size); break; =20 case ASI_USERDATA: /* User data access */ @@ -1175,7 +1173,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulo= ng addr, { int size =3D 1 << (memop & MO_SIZE); int sign =3D memop & MO_SIGN; - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint64_t ret =3D 0; #if defined(DEBUG_ASI) target_ulong last_addr =3D addr; @@ -1481,8 +1479,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, target_ulong val, int asi, uint32_t memop) { int size =3D 1 << (memop & MO_SIZE); - SPARCCPU *cpu =3D sparc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 #ifdef DEBUG_ASI dump_asi("write", addr, asi, size, val); @@ -1686,13 +1683,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong= addr, target_ulong val, env->dmmu.mmu_primary_context =3D val; /* can be optimized to only flush MMU_USER_IDX and MMU_KERNEL_IDX entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; case 2: /* Secondary context */ env->dmmu.mmu_secondary_context =3D val; /* can be optimized to only flush MMU_USER_SECONDARY_IDX and MMU_KERNEL_SECONDARY_IDX entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; case 5: /* TSB access */ DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" @@ -1768,13 +1765,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong= addr, target_ulong val, case 1: env->dmmu.mmu_primary_context =3D val; env->immu.mmu_primary_context =3D val; - tlb_flush_by_mmuidx(CPU(cpu), + tlb_flush_by_mmuidx(cs, (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_I= DX)); break; case 2: env->dmmu.mmu_secondary_context =3D val; env->immu.mmu_secondary_context =3D val; - tlb_flush_by_mmuidx(CPU(cpu), + tlb_flush_by_mmuidx(cs, (1 << MMU_USER_SECONDARY_IDX) | (1 << MMU_KERNEL_SECONDARY_IDX)); break; diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 135a9c9d9b..0366c26246 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -95,7 +95,7 @@ static int get_physical_address(CPUSPARCState *env, hwadd= r *physical, uint32_t pde; int error_code =3D 0, is_dirty, is_user; unsigned long page_offset; - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 is_user =3D mmu_idx =3D=3D MMU_USER_IDX; =20 @@ -255,7 +255,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, int rw, =20 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmule= v) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); hwaddr pde_ptr; uint32_t pde; =20 @@ -322,7 +322,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong= address, int mmulev) =20 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong va, va1, va2; unsigned int n, m, o; hwaddr pde_ptr, pa; @@ -481,7 +481,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int mmu= _idx) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); unsigned int i; uint64_t context; uint64_t sfsr =3D 0; @@ -599,7 +599,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int mmu_idx) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); unsigned int i; uint64_t context; bool is_user =3D false; --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; 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[66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.47 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=RMLV20NoAAHxOYYjZUgH2bsAP15O5mtIcw4toA3zm8E=; b=zrPea30qrJeOwe/TmP9nrdE/TnvY0POaxM0aFVPaDHEqNiAn+5C1q2RdxIV7KuwKKF KxuMjGuhiHEwm/HOoBgJHf0MHAmWjLQw646OyrYPw7hreHuCkFDRqeQUzfYTHXFelPxz aza9q/454yF46ZjLxnn70tYhrKfmDgywVPV3K/rA2s2usZDgowaO7+qbf4i3SXYNI8rw YoPO5wvW1UNdLc1BChDhOcdFePVL1kpaWFFPZzzlfMrF1OAltHhBkUgVaCbc3dWJviAS UlFea3JCxzliHYnBeskVG5DBUDtbIoK8EIX5A4tmnSL4e+60VCEnzq4gX6kFQ9WHHU4T 6I1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=RMLV20NoAAHxOYYjZUgH2bsAP15O5mtIcw4toA3zm8E=; b=uiM0y9wT4agbcyLkTGi0vNxOHocuXV23hYrbXZuLdB1PkmihDuKBCAu6WTb0a3T/Ew ve/uVYjDYoucETn7vuoUN1HVTmOT50KXlgY5JFfQww+MPd/ios6ioBXvvi04O4yB6QFv IU6otyiHOTCHADzXUfZenP9qvftRK8R5A6VFK+GrNoQuP9tTGm8zT86WgIVI2ALeJOXi fWeCcrkqtdklqZveQWITJH6u2T73KtnJlaFgc4ctGIo9DZBy1wJX5FzYHaVooG0GjpKJ LGR4/DeW2/TCZmpnJpQP8vVhidG55iCNyZFCtsGyfHbb/LIEwfEOsVwXJMI99djvDwbj aN4Q== X-Gm-Message-State: APjAAAVEX0B7IXr0rNkukLvajHAcpq3mpWEnAQx2VF9sRxgz0BYkUHVh DatEVnQEwmrsfsHCtJEBNzqindJ1thc= X-Google-Smtp-Source: APXvYqy6CKQDoEC5XJbCqgWDmbrbkIAsgDkGHe+OTjDUxV8Xex3I9JacqfqbT6FK1V6Fpz5Om1jaTg== X-Received: by 2002:a63:d304:: with SMTP id b4mr29528499pgg.300.1553814288555; Thu, 28 Mar 2019 16:04:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:53 -1000 Message-Id: <20190328230404.12909-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.1 v2 25/36] target/tilegx: Use env_cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/tilegx/cpu.h | 5 ----- linux-user/tilegx/cpu_loop.c | 2 +- target/tilegx/helper.c | 2 +- 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 135df63523..7f8fe7c513 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -138,11 +138,6 @@ typedef struct TileGXCPU { CPUTLGState env; } TileGXCPU; =20 -static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env) -{ - return container_of(env, TileGXCPU, env); -} - #define ENV_OFFSET offsetof(TileGXCPU, env) =20 /* TILE-Gx memory attributes */ diff --git a/linux-user/tilegx/cpu_loop.c b/linux-user/tilegx/cpu_loop.c index 4f39eb9ad3..d4abe29dcd 100644 --- a/linux-user/tilegx/cpu_loop.c +++ b/linux-user/tilegx/cpu_loop.c @@ -206,7 +206,7 @@ static void do_fetch(CPUTLGState *env, int trapnr, bool= quad) =20 void cpu_loop(CPUTLGState *env) { - CPUState *cs =3D CPU(tilegx_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; =20 while (1) { diff --git a/target/tilegx/helper.c b/target/tilegx/helper.c index 4964bb9111..a57a679825 100644 --- a/target/tilegx/helper.c +++ b/target/tilegx/helper.c @@ -28,7 +28,7 @@ =20 void helper_exception(CPUTLGState *env, uint32_t excp) { - CPUState *cs =3D CPU(tilegx_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; cpu_loop_exit(cs); --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553815908379366.59473137247915; Thu, 28 Mar 2019 16:31:48 -0700 (PDT) Received: from localhost ([127.0.0.1]:43328 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eUq-0003Uv-Ce for importer@patchew.org; Thu, 28 Mar 2019 19:31:44 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42236) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKn-0001dn-71 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4t-0003CT-8u for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:59 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:40541) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4r-0003AH-44 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:53 -0400 Received: by mail-pg1-x542.google.com with SMTP id u9so226312pgo.7 for ; Thu, 28 Mar 2019 16:04:51 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH for-4.1 v2 26/36] target/tricore: Use env_cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/tricore/cpu.h | 5 ----- target/tricore/op_helper.c | 4 ++-- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index ed32622388..9ea5060a87 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -208,11 +208,6 @@ struct TriCoreCPU { CPUTriCoreState env; }; =20 -static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCoreState *env) -{ - return TRICORE_CPU(container_of(env, TriCoreCPU, env)); -} - #define ENV_OFFSET offsetof(TriCoreCPU, env) =20 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index ed9dc0c83e..ba2f21a6c3 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -29,7 +29,7 @@ static void QEMU_NORETURN raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int ti= n, uintptr_t pc, uint32_t fcd_pc) { - CPUState *cs =3D CPU(tricore_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); /* in case we come from a helper-call we need to restore the PC */ cpu_restore_state(cs, pc, true); =20 @@ -2800,7 +2800,7 @@ static inline void QEMU_NORETURN do_raise_exception_e= rr(CPUTriCoreState *env, int error_code, uintptr_t pc) { - CPUState *cs =3D CPU(tricore_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); cs->exception_index =3D exception; env->error_code =3D error_code; /* now we have a real cpu fault */ --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553815579183102.49254657764618; Thu, 28 Mar 2019 16:26:19 -0700 (PDT) Received: from localhost ([127.0.0.1]:43246 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9ePa-0006nk-3S for importer@patchew.org; Thu, 28 Mar 2019 19:26:18 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42458) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKm-0001my-W0 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4z-0003EM-KI for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:05:04 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:42611) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4s-0003BU-Cq for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:56 -0400 Received: by mail-pf1-x441.google.com with SMTP id r15so74573pfn.9 for ; Thu, 28 Mar 2019 16:04:53 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. [66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=h/JYHJOvhKp/F4IlZ+qSqMSkehj6Zo7FJda3RsVFFe0=; b=V8BzuRzZ5icf7Oj7LCpWpJNLwjHkT04CyOeInE7ImetCrDQ6/EISevnLUlEIIXXk4R 73hhn5xSPo+466wrvn/Um/9KKzSCZs17soMp5U76uzCTyc3rk7fVJvllv9NXmJpJIp0i Rx6rSFHpXDs8h8KP28M2nQgrgyBY+ZCh8GyzxEVv5RBJwyT4e/EmwFoobVFd+grMYS1P NmIygFBS8rEVgGWvyXGfrUXm6gIUtAT2PwszgmeIrYXqKIBJ5YnP2CFRs+nkN3LQAzfw 98DC5jrzu4CLMIjj6QXkOWuoZ8bPCNvSbFxYCcpTBw7MEmhHeu1vlqmeIAblEhfzX9dU bHxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=h/JYHJOvhKp/F4IlZ+qSqMSkehj6Zo7FJda3RsVFFe0=; b=KGJ/Ct7LpdZgWUxX/+uxFywAG5ZsNKvlCCgOoJC1Ix7E5DpoVPTWsj4tZSvuVVBsnN eDIBXMBAsxm8cqlim2inVLLi8ohNm8mxLk54gUhbfoNFaKPpQMFFOM9f0VUEtEENpBbb 3OZqHBD0MfKGHJhQecHbW53kZ6uGMqrCZOglTgAJpnqaFglMB6X7IPyBTO0sOlJHM3nh tco9Mey0YoVWHTS4PbOiZhLZVDmcSAxUlew5pjb2MNjGTGkCydXR+y5XePUExX5ZHpOS hpkh+DZ31gBqbgSrNTCRznXd0Js89Mma4iYDKhWEZ3vk8jTwMXyj5GKpdR2ayI0FpkO9 fiow== X-Gm-Message-State: APjAAAXadli3HZaaH9djSdELpvlFjW67Fxvtgnan5bF5NYVfn6lfehf0 +uDijTiLK/XO4AfiDcpU3XZrkbgkK9c= X-Google-Smtp-Source: APXvYqxSUm9kO5p1V1CcUmBBf0xfBmM1PODfiWU0NPhCXkduiPKLbZKtiBX8fIrb6+i+ct3LdzcOkg== X-Received: by 2002:aa7:8289:: with SMTP id s9mr30827176pfm.208.1553814292676; Thu, 28 Mar 2019 16:04:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:55 -1000 Message-Id: <20190328230404.12909-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.1 v2 27/36] target/unicore32: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/unicore32/cpu.h | 5 ----- hw/unicore32/puv3.c | 2 +- target/unicore32/helper.c | 8 ++------ target/unicore32/op_helper.c | 2 +- target/unicore32/softmmu.c | 11 ++++------- target/unicore32/translate.c | 26 ++------------------------ target/unicore32/ucf64_helper.c | 2 +- 7 files changed, 11 insertions(+), 45 deletions(-) diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 162e33257d..14c2d047fd 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -76,11 +76,6 @@ struct UniCore32CPU { CPUUniCore32State env; }; =20 -static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env) -{ - return container_of(env, UniCore32CPU, env); -} - #define ENV_OFFSET offsetof(UniCore32CPU, env) =20 void uc32_cpu_do_interrupt(CPUState *cpu); diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c index b42e600f74..132e6086ee 100644 --- a/hw/unicore32/puv3.c +++ b/hw/unicore32/puv3.c @@ -56,7 +56,7 @@ static void puv3_soc_init(CPUUniCore32State *env) =20 /* Initialize interrupt controller */ cpu_intc =3D qemu_allocate_irq(puv3_intc_cpu_handler, - uc32_env_get_cpu(env), 0); + env_archcpu(env), 0); dev =3D sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, cpu_intc); for (i =3D 0; i < PUV3_IRQS_NR; i++) { irqs[i] =3D qdev_get_gpio_in(dev, i); diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index a5ff2ddb74..19ba865482 100644 --- a/target/unicore32/helper.c +++ b/target/unicore32/helper.c @@ -31,8 +31,6 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, uint32_t cop) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - /* * movc pp.nn, rn, #imm9 * rn: UCOP_REG_D @@ -101,7 +99,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val= , uint32_t creg, case 6: if ((cop <=3D 6) && (cop >=3D 2)) { /* invalid all tlb */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); return; } break; @@ -218,10 +216,8 @@ void helper_cp1_putc(target_ulong x) #ifdef CONFIG_USER_ONLY void switch_mode(CPUUniCore32State *env, int mode) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - if (mode !=3D ASR_MODE_USER) { - cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); + cpu_abort(env_cpu(env), "Tried to switch out of user mode\n"); } } =20 diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index e0a15882d3..44ff84420e 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -19,7 +19,7 @@ =20 void HELPER(exception)(CPUUniCore32State *env, uint32_t excp) { - CPUState *cs =3D CPU(uc32_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; cpu_loop_exit(cs); diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 00c7e0d028..2f31592faf 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -36,8 +36,6 @@ /* Map CPU modes onto saved register banks. */ static inline int bank_number(CPUUniCore32State *env, int mode) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - switch (mode) { case ASR_MODE_USER: case ASR_MODE_SUSR: @@ -51,7 +49,7 @@ static inline int bank_number(CPUUniCore32State *env, int= mode) case ASR_MODE_INTR: return 4; } - cpu_abort(CPU(cpu), "Bad mode %x\n", mode); + cpu_abort(env_cpu(env), "Bad mode %x\n", mode); return -1; } =20 @@ -126,8 +124,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, u= int32_t address, int access_type, int is_user, uint32_t *phys_ptr, int *prot, target_ulong *page_size) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); int code; uint32_t table; uint32_t desc; @@ -174,11 +171,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env,= uint32_t address, *page_size =3D TARGET_PAGE_SIZE; break; default: - cpu_abort(CPU(cpu), "wrong page type!"); + cpu_abort(cs, "wrong page type!"); } break; default: - cpu_abort(CPU(cpu), "wrong page type!"); + cpu_abort(cs, "wrong page type!"); } =20 *phys_ptr =3D phys_addr; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 002569ff3b..2e8341d13b 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -179,7 +179,7 @@ static void store_reg(DisasContext *s, int reg, TCGv va= r) #define UCOP_SET_L UCOP_SET(24) #define UCOP_SET_S UCOP_SET(24) =20 -#define ILLEGAL cpu_abort(CPU(cpu), \ +#define ILLEGAL cpu_abort(env_cpu(env), \ "Illegal UniCore32 instruction %x at line %d!", \ insn, __LINE__) =20 @@ -187,7 +187,6 @@ static void store_reg(DisasContext *s, int reg, TCGv va= r) static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv tmp, tmp2, tmp3; if ((insn & 0xfe000000) =3D=3D 0xe0000000) { tmp2 =3D new_tmp(); @@ -213,7 +212,6 @@ static void disas_cp0_insn(CPUUniCore32State *env, Disa= sContext *s, static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv tmp; =20 if ((insn & 0xff003fff) =3D=3D 0xe1000400) { @@ -681,7 +679,6 @@ static inline long ucf64_reg_offset(int reg) /* UniCore-F64 single load/store I_offset */ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint3= 2_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); int offset; TCGv tmp; TCGv addr; @@ -728,7 +725,6 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env, Dis= asContext *s, uint32_t in /* UniCore-F64 load/store multiple words */ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint3= 2_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); unsigned int i; int j, n, freg; TCGv tmp; @@ -814,7 +810,6 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env, Dis= asContext *s, uint32_t in /* UniCore-F64 mrc/mcr */ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32= _t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv tmp; =20 if ((insn & 0xfe0003ff) =3D=3D 0xe2000000) { @@ -879,8 +874,6 @@ static void do_ucf64_trans(CPUUniCore32State *env, Disa= sContext *s, uint32_t ins /* UniCore-F64 convert instructions */ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_= t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - if (UCOP_UCF64_FMT =3D=3D 3) { ILLEGAL; } @@ -947,8 +940,6 @@ static void do_ucf64_fcvt(CPUUniCore32State *env, Disas= Context *s, uint32_t insn /* UniCore-F64 compare instructions */ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_= t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - if (UCOP_SET(25)) { ILLEGAL; } @@ -1027,8 +1018,6 @@ static void do_ucf64_fcmp(CPUUniCore32State *env, Dis= asContext *s, uint32_t insn /* UniCore-F64 data processing */ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32= _t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - if (UCOP_UCF64_FMT =3D=3D 3) { ILLEGAL; } @@ -1062,8 +1051,6 @@ static void do_ucf64_datap(CPUUniCore32State *env, Di= sasContext *s, uint32_t ins /* Disassemble an F64 instruction */ static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint= 32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - if (!UCOP_SET(29)) { if (UCOP_SET(26)) { do_ucf64_ldst_m(env, s, insn); @@ -1161,8 +1148,6 @@ static void gen_exception_return(DisasContext *s, TCG= v pc) static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - switch (UCOP_CPNUM) { #ifndef CONFIG_USER_ONLY case 0: @@ -1177,14 +1162,13 @@ static void disas_coproc_insn(CPUUniCore32State *en= v, DisasContext *s, break; default: /* Unknown coprocessor. */ - cpu_abort(CPU(cpu), "Unknown coprocessor!"); + cpu_abort(env_cpu(env), "Unknown coprocessor!"); } } =20 /* data processing instructions */ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t ins= n) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv tmp; TCGv tmp2; int logic_cc; @@ -1418,7 +1402,6 @@ static void do_mult(CPUUniCore32State *env, DisasCont= ext *s, uint32_t insn) /* miscellaneous instructions */ static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); unsigned int val; TCGv tmp; =20 @@ -1544,7 +1527,6 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasC= ontext *s, uint32_t insn) /* SWP instruction */ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv addr; TCGv tmp; TCGv tmp2; @@ -1572,7 +1554,6 @@ static void do_swap(CPUUniCore32State *env, DisasCont= ext *s, uint32_t insn) /* load/store hw/sb */ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t= insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv addr; TCGv tmp; =20 @@ -1625,7 +1606,6 @@ static void do_ldst_hwsb(CPUUniCore32State *env, Disa= sContext *s, uint32_t insn) /* load/store multiple words */ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t in= sn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); unsigned int val, i, mmu_idx; int j, n, reg, user, loaded_base; TCGv tmp; @@ -1767,7 +1747,6 @@ static void do_ldst_m(CPUUniCore32State *env, DisasCo= ntext *s, uint32_t insn) /* branch (and link) */ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t in= sn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); unsigned int val; int32_t offset; TCGv tmp; @@ -1797,7 +1776,6 @@ static void do_branch(CPUUniCore32State *env, DisasCo= ntext *s, uint32_t insn) =20 static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); unsigned int insn; =20 insn =3D cpu_ldl_code(env, s->pc); diff --git a/target/unicore32/ucf64_helper.c b/target/unicore32/ucf64_helpe= r.c index fad3fa6618..e078e84437 100644 --- a/target/unicore32/ucf64_helper.c +++ b/target/unicore32/ucf64_helper.c @@ -78,7 +78,7 @@ static inline int ucf64_exceptbits_to_host(int target_bit= s) =20 void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.1 v2 28/36] target/xtensa: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/xtensa/cpu.h | 17 ++++++----------- hw/xtensa/pic_cpu.c | 2 +- linux-user/xtensa/cpu_loop.c | 2 +- target/xtensa/dbg_helper.c | 4 ++-- target/xtensa/exc_helper.c | 9 ++++----- target/xtensa/helper.c | 2 +- target/xtensa/mmu_helper.c | 11 ++++------- target/xtensa/xtensa-semi.c | 2 +- 8 files changed, 20 insertions(+), 29 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index e6f57e0b64..d5465c2853 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -529,11 +529,6 @@ struct XtensaCPU { CPUXtensaState env; }; =20 -static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) -{ - return container_of(env, XtensaCPU, env); -} - #define ENV_OFFSET offsetof(XtensaCPU, env) =20 =20 @@ -712,10 +707,15 @@ static inline int cpu_mmu_index(CPUXtensaState *env, = bool ifetch) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 =20 +typedef CPUXtensaState CPUArchState; +typedef XtensaCPU ArchCPU; + +#include "exec/cpu-all.h" + static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong = *pc, target_ulong *cs_base, uint32_t *flags) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 *pc =3D env->pc; *cs_base =3D 0; @@ -785,9 +785,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState = *env, target_ulong *pc, } } =20 -typedef CPUXtensaState CPUArchState; -typedef XtensaCPU ArchCPU; - -#include "exec/cpu-all.h" - #endif diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c index a8939f5e58..df3acbb541 100644 --- a/hw/xtensa/pic_cpu.c +++ b/hw/xtensa/pic_cpu.c @@ -33,7 +33,7 @@ =20 void check_interrupts(CPUXtensaState *env) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int minlevel =3D xtensa_get_cintlevel(env); uint32_t int_set_enabled =3D env->sregs[INTSET] & env->sregs[INTENABLE= ]; int level; diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index bee78edb8a..64831c9199 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -123,7 +123,7 @@ static void xtensa_underflow12(CPUXtensaState *env) =20 void cpu_loop(CPUXtensaState *env) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_siginfo_t info; abi_ulong ret; int trapnr; diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index cd8fbd653a..be1f81107b 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -71,7 +71,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i,= uint32_t v) static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, uint32_t dbreakc) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; uint32_t mask =3D dbreakc | ~DBREAKC_MASK; =20 @@ -118,7 +118,7 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t = i, uint32_t v) set_dbreak(env, i, env->sregs[DBREAKA + i], v); } else { if (env->cpu_watchpoint[i]) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); env->cpu_watchpoint[i] =3D NULL; diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 4a1f7aef5d..601341d13a 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -34,7 +34,7 @@ =20 void HELPER(exception)(CPUXtensaState *env, uint32_t excp) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; if (excp =3D=3D EXCP_YIELD) { @@ -100,7 +100,7 @@ void HELPER(debug_exception)(CPUXtensaState *env, uint3= 2_t pc, uint32_t cause) =20 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) { - CPUState *cpu; + CPUState *cpu =3D env_cpu(env); =20 env->pc =3D pc; env->sregs[PS] =3D (env->sregs[PS] & ~PS_INTLEVEL) | @@ -111,11 +111,10 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, = uint32_t intlevel) qemu_mutex_unlock_iothread(); =20 if (env->pending_irq_level) { - cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); + cpu_loop_exit(cpu); return; } =20 - cpu =3D CPU(xtensa_env_get_cpu(env)); cpu->halted =3D 1; HELPER(exception)(env, EXCP_HLT); } @@ -165,7 +164,7 @@ static void handle_interrupt(CPUXtensaState *env) (env->config->level_mask[level] & env->sregs[INTSET] & env->sregs[INTENABLE])) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (level > 1) { env->sregs[EPC1 + level - 1] =3D env->pc; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f4867a9b56..51c8d992b9 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -315,7 +315,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, vaddr addr, =20 void xtensa_runstall(CPUXtensaState *env, bool runstall) { - CPUState *cpu =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cpu =3D env_cpu(env); =20 env->runstall =3D runstall; cpu->halted =3D runstall; diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 2096fbbd9f..97dfbe00ad 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -45,12 +45,10 @@ void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_= t vaddr) =20 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) { - XtensaCPU *cpu =3D xtensa_env_get_cpu(env); - v =3D (v & 0xffffff00) | 0x1; if (v !=3D env->sregs[RASID]) { env->sregs[RASID] =3D v; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 @@ -249,7 +247,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint= 32_t dtlb) uint32_t wi; xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); if (entry->variable && entry->asid) { - tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); + tlb_flush_page(env_cpu(env), entry->vaddr); entry->asid =3D 0; } } @@ -295,8 +293,7 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, unsigned wi, unsigned ei, uint32_t vpn, uint32_t= pte) { - XtensaCPU *cpu =3D xtensa_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); xtensa_tlb_entry *entry =3D xtensa_tlb_get_entry(env, dtlb, wi, ei); =20 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { @@ -651,7 +648,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, b= ool update_tlb, =20 static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t paddr; uint32_t page_size; unsigned access; diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c index 5f5ce4f344..bb29adc921 100644 --- a/target/xtensa/xtensa-semi.c +++ b/target/xtensa/xtensa-semi.c @@ -197,7 +197,7 @@ void xtensa_sim_open_console(Chardev *chr) =20 void HELPER(simcall)(CPUXtensaState *env) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t *regs =3D env->regs; =20 switch (regs[2]) { --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH for-4.1 v2 29/36] cpu: Move ENV_OFFSET to exec/gen-icount.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that we have ArchCPU, we can define this generically, in the one place that needs it. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/exec/gen-icount.h | 2 ++ target/alpha/cpu.h | 1 - target/arm/cpu.h | 2 -- target/cris/cpu.h | 1 - target/hppa/cpu.h | 1 - target/i386/cpu.h | 1 - target/lm32/cpu.h | 1 - target/m68k/cpu.h | 1 - target/microblaze/cpu.h | 1 - target/mips/cpu.h | 1 - target/moxie/cpu.h | 1 - target/nios2/cpu.h | 1 - target/openrisc/cpu.h | 1 - target/ppc/cpu.h | 1 - target/riscv/cpu.h | 2 -- target/s390x/cpu.h | 1 - target/sh4/cpu.h | 1 - target/sparc/cpu.h | 1 - target/tilegx/cpu.h | 1 - target/tricore/cpu.h | 1 - target/unicore32/cpu.h | 1 - target/xtensa/cpu.h | 2 -- 22 files changed, 2 insertions(+), 24 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 24f7991781..9cfa6ccce5 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -5,6 +5,8 @@ =20 /* Helpers for instruction counting code generation. */ =20 +#define ENV_OFFSET offsetof(ArchCPU, env) + static TCGOp *icount_start_insn; =20 static inline void gen_tb_start(TranslationBlock *tb) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e22518871a..93919bbaa2 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -273,7 +273,6 @@ struct AlphaCPU { QEMUTimer *alarm_timer; }; =20 -#define ENV_OFFSET offsetof(AlphaCPU, env) =20 #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_alpha_cpu; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3de68c5844..df0409a703 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -907,8 +907,6 @@ void arm_cpu_post_init(Object *obj); =20 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); =20 -#define ENV_OFFSET offsetof(ARMCPU, env) - #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_arm_cpu; #endif diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 6111dbb14c..b87a559137 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -183,7 +183,6 @@ struct CRISCPU { CPUCRISState env; }; =20 -#define ENV_OFFSET offsetof(CRISCPU, env) =20 #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_cris_cpu; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 1387066324..65986dacbf 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -222,7 +222,6 @@ struct HPPACPU { QEMUTimer *alarm_timer; }; =20 -#define ENV_OFFSET offsetof(HPPACPU, env) =20 typedef CPUHPPAState CPUArchState; typedef HPPACPU ArchCPU; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7ff5ab77c1..c5351bea7e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1477,7 +1477,6 @@ struct X86CPU { int32_t hv_max_vps; }; =20 -#define ENV_OFFSET offsetof(X86CPU, env) =20 #ifndef CONFIG_USER_ONLY extern struct VMStateDescription vmstate_x86_cpu; diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 69beb16972..deb83153b3 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -195,7 +195,6 @@ struct LM32CPU { uint32_t features; }; =20 -#define ENV_OFFSET offsetof(LM32CPU, env) =20 #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_lm32_cpu; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index eb3048914e..2b180cf18d 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -163,7 +163,6 @@ struct M68kCPU { CPUM68KState env; }; =20 -#define ENV_OFFSET offsetof(M68kCPU, env) =20 void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a9748d57ad..ff3abb61af 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -310,7 +310,6 @@ struct MicroBlazeCPU { CPUMBState env; }; =20 -#define ENV_OFFSET offsetof(MicroBlazeCPU, env) =20 void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 914cc26c21..49c226b587 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1051,7 +1051,6 @@ struct MIPSCPU { CPUMIPSState env; }; =20 -#define ENV_OFFSET offsetof(MIPSCPU, env) =20 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 71e7cf0f08..00b1486659 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -90,7 +90,6 @@ typedef struct MoxieCPU { CPUMoxieState env; } MoxieCPU; =20 -#define ENV_OFFSET offsetof(MoxieCPU, env) =20 void moxie_cpu_do_interrupt(CPUState *cs); void moxie_cpu_dump_state(CPUState *cpu, FILE *f, diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 3fc27ead81..39a2471b18 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -193,7 +193,6 @@ typedef struct Nios2CPU { uint32_t fast_tlb_miss_addr; } Nios2CPU; =20 -#define ENV_OFFSET offsetof(Nios2CPU, env) =20 void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 853cf633e7..ad2118b599 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,7 +317,6 @@ typedef struct OpenRISCCPU { =20 } OpenRISCCPU; =20 -#define ENV_OFFSET offsetof(OpenRISCCPU, env) =20 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); void openrisc_cpu_do_interrupt(CPUState *cpu); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c3fe154979..038e2499ed 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1191,7 +1191,6 @@ struct PowerPCCPU { int32_t mig_slb_nr; }; =20 -#define ENV_OFFSET offsetof(PowerPCCPU, env) =20 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c18dd5eb24..9e71297ca7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -229,8 +229,6 @@ extern const char * const riscv_fpr_regnames[]; extern const char * const riscv_excp_names[]; extern const char * const riscv_intr_names[]; =20 -#define ENV_OFFSET offsetof(RISCVCPU, env) - void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 372d4c198f..3a6a5ada86 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -163,7 +163,6 @@ struct S390CPU { uint32_t irqstate_saved_size; }; =20 -#define ENV_OFFSET offsetof(S390CPU, env) =20 #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_s390_cpu; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 1f94e7bf7b..02269c09b8 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -207,7 +207,6 @@ struct SuperHCPU { CPUSH4State env; }; =20 -#define ENV_OFFSET offsetof(SuperHCPU, env) =20 void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index bf6f63d029..02e40d381b 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -532,7 +532,6 @@ struct SPARCCPU { CPUSPARCState env; }; =20 -#define ENV_OFFSET offsetof(SPARCCPU, env) =20 #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_sparc_cpu; diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 7f8fe7c513..643b7dbd17 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -138,7 +138,6 @@ typedef struct TileGXCPU { CPUTLGState env; } TileGXCPU; =20 -#define ENV_OFFSET offsetof(TileGXCPU, env) =20 /* TILE-Gx memory attributes */ #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 9ea5060a87..9e60ef981b 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -208,7 +208,6 @@ struct TriCoreCPU { CPUTriCoreState env; }; =20 -#define ENV_OFFSET offsetof(TriCoreCPU, env) =20 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void tricore_cpu_dump_state(CPUState *cpu, FILE *f, diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 14c2d047fd..12b8268f7b 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -76,7 +76,6 @@ struct UniCore32CPU { CPUUniCore32State env; }; =20 -#define ENV_OFFSET offsetof(UniCore32CPU, env) =20 void uc32_cpu_do_interrupt(CPUState *cpu); bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d5465c2853..6fddac3a2b 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -529,8 +529,6 @@ struct XtensaCPU { CPUXtensaState env; }; =20 -#define ENV_OFFSET offsetof(XtensaCPU, env) - =20 int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int s= ize, int mmu_idx); --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH for-4.1 v2 30/36] cpu: Introduce cpu_set_cpustate_pointers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Consolidate some boilerplate from foo_cpu_initfn. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/exec/cpu-all.h | 12 +++++++++++- target/alpha/cpu.c | 3 +-- target/arm/cpu.c | 3 +-- target/cris/cpu.c | 3 +-- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 3 +-- target/lm32/cpu.c | 3 +-- target/m68k/cpu.c | 4 +--- target/microblaze/cpu.c | 3 +-- target/mips/cpu.c | 3 +-- target/moxie/cpu.c | 3 +-- target/nios2/cpu.c | 6 ++---- target/openrisc/cpu.c | 3 +-- target/ppc/translate_init.inc.c | 3 +-- target/riscv/cpu.c | 3 +-- target/s390x/cpu.c | 9 +++++---- target/sh4/cpu.c | 3 +-- target/sparc/cpu.c | 3 +-- target/tilegx/cpu.c | 4 +--- target/tricore/cpu.c | 4 +--- target/unicore32/cpu.c | 3 +-- target/xtensa/cpu.c | 3 +-- 22 files changed, 37 insertions(+), 49 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 0951fd9053..1ed7d1e005 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -371,6 +371,17 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong ad= dr, =20 int cpu_exec(CPUState *cpu); =20 +/** + * cpu_set_cpustate_pointers(cpu) + * @cpu: The cpu object + * + * Set the generic pointers in CPUState into the outer object. + */ +static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) +{ + cpu->parent_obj.env_ptr =3D &cpu->env; +} + /** * env_archcpu(env) * @env: The architecture environment @@ -392,5 +403,4 @@ static inline CPUState *env_cpu(CPUArchState *env) { return &env_archcpu(env)->parent_obj; } - #endif /* CPU_ALL_H */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 1fd95d6c0f..82a37e0371 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -196,11 +196,10 @@ static void ev67_cpu_initfn(Object *obj) =20 static void alpha_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); AlphaCPU *cpu =3D ALPHA_CPU(obj); CPUAlphaState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 env->lock_addr =3D -1; #if defined(CONFIG_USER_ONLY) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4155782197..4138fa8112 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -694,10 +694,9 @@ static void cpreg_hashtable_data_destroy(gpointer data) =20 static void arm_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); ARMCPU *cpu =3D ARM_CPU(obj); =20 - cs->env_ptr =3D &cpu->env; + cpu_set_cpustate_pointers(cpu); cpu->cp_regs =3D g_hash_table_new_full(g_int_hash, g_int_equal, g_free, cpreg_hashtable_data_dest= roy); =20 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index a23aba2688..15717712eb 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -176,12 +176,11 @@ static void cris_disas_set_info(CPUState *cpu, disass= emble_info *info) =20 static void cris_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); CRISCPU *cpu =3D CRIS_CPU(obj); CRISCPUClass *ccc =3D CRIS_CPU_GET_CLASS(obj); CPUCRISState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 env->pregs[PR_VR] =3D ccc->vr; =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 00bf444620..544b4e2e4c 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -138,7 +138,7 @@ static void hppa_cpu_initfn(Object *obj) HPPACPU *cpu =3D HPPA_CPU(obj); CPUHPPAState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); cs->exception_index =3D -1; cpu_hppa_loaded_fr0(env); cpu_hppa_put_psw(env, PSW_W); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cdec1db05e..35824c8f8d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5539,13 +5539,12 @@ static void x86_cpu_get_crash_info_qom(Object *obj,= Visitor *v, =20 static void x86_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); X86CPU *cpu =3D X86_CPU(obj); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(obj); CPUX86State *env =3D &cpu->env; FeatureWord w; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 object_property_add(obj, "family", "int", x86_cpuid_version_get_family, diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index b7499cb627..b5c213183c 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -146,11 +146,10 @@ static void lm32_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 static void lm32_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); LM32CPU *cpu =3D LM32_CPU(obj); CPULM32State *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 env->flags =3D 0; } diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 582e3a73b3..930e1be59f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -238,11 +238,9 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error= **errp) =20 static void m68k_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); } =20 static const VMStateDescription vmstate_m68k_cpu =3D { diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 5596cd5485..db4dcdb4ad 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -221,11 +221,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error = **errp) =20 static void mb_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(obj); CPUMBState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e217fb3e36..3d1b693eef 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -152,12 +152,11 @@ static void mips_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 static void mips_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); MIPSCPU *cpu =3D MIPS_CPU(obj); CPUMIPSState *env =3D &cpu->env; MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(obj); =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); env->cpu_model =3D mcc->cpu_def; } =20 diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 46434e65ba..316ee9c534 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -74,10 +74,9 @@ static void moxie_cpu_realizefn(DeviceState *dev, Error = **errp) =20 static void moxie_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); MoxieCPU *cpu =3D MOXIE_CPU(obj); =20 - cs->env_ptr =3D &cpu->env; + cpu_set_cpustate_pointers(cpu); } =20 static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index fbfaa2ce26..43677fa802 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -66,14 +66,12 @@ static void nios2_cpu_reset(CPUState *cs) =20 static void nios2_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); Nios2CPU *cpu =3D NIOS2_CPU(obj); - CPUNios2State *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 #if !defined(CONFIG_USER_ONLY) - mmu_init(env); + mmu_init(&cpu->env); #endif } =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 541b2a66c7..c01f0fa0cc 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -91,10 +91,9 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 static void openrisc_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 - cs->env_ptr =3D &cpu->env; + cpu_set_cpustate_pointers(cpu); } =20 /* CPU models */ diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index a4ec7d81d7..a6c3a3488a 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10428,12 +10428,11 @@ static bool ppc_cpu_is_big_endian(CPUState *cs) =20 static void ppc_cpu_instance_init(Object *obj) { - CPUState *cs =3D CPU(obj); PowerPCCPU *cpu =3D POWERPC_CPU(obj); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); cpu->vcpu_id =3D UNASSIGNED_CPU_INDEX; =20 env->msr_mask =3D pcc->msr_mask; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d61bce6d55..09eff1e880 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -315,10 +315,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) =20 static void riscv_cpu_init(Object *obj) { - CPUState *cs =3D CPU(obj); RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - cs->env_ptr =3D &cpu->env; + cpu_set_cpustate_pointers(cpu); } =20 static const VMStateDescription vmstate_riscv_cpu =3D { diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 698dd9cb82..790670ebeb 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -282,17 +282,18 @@ static void s390_cpu_initfn(Object *obj) { CPUState *cs =3D CPU(obj); S390CPU *cpu =3D S390_CPU(obj); - CPUS390XState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; object_property_add(obj, "crash-information", "GuestPanicInformation", s390_cpu_get_crash_info_qom, NULL, NULL, NULL, NUL= L); s390_cpu_model_register_props(obj); #if !defined(CONFIG_USER_ONLY) - env->tod_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, c= pu); - env->cpu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, c= pu); + cpu->env.tod_timer =3D + timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); + cpu->env.cpu_timer =3D + timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu); #endif } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index b9f393b7c7..4794418e38 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -203,11 +203,10 @@ static void superh_cpu_realizefn(DeviceState *dev, Er= ror **errp) =20 static void superh_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); SuperHCPU *cpu =3D SUPERH_CPU(obj); CPUSH4State *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 env->movcal_backup_tail =3D &(env->movcal_backup); } diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 4a4445bdf5..dfabd12e31 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -779,12 +779,11 @@ static void sparc_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 static void sparc_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); SPARCCPU *cpu =3D SPARC_CPU(obj); SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(obj); CPUSPARCState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 if (scc->cpu_def) { env->def =3D *scc->cpu_def; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index bfe9be59b5..9988243d8c 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -99,11 +99,9 @@ static void tilegx_cpu_realizefn(DeviceState *dev, Error= **errp) =20 static void tilegx_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); TileGXCPU *cpu =3D TILEGX_CPU(obj); - CPUTLGState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); } =20 static void tilegx_cpu_do_interrupt(CPUState *cs) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index e8d37e4040..fc3c3075b3 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -104,11 +104,9 @@ static void tricore_cpu_realizefn(DeviceState *dev, Er= ror **errp) =20 static void tricore_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); TriCoreCPU *cpu =3D TRICORE_CPU(obj); - CPUTriCoreState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); } =20 static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model) diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 2b49d1ca40..700c5c5585 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -103,11 +103,10 @@ static void uc32_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 static void uc32_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); UniCore32CPU *cpu =3D UNICORE32_CPU(obj); CPUUniCore32State *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 #ifdef CONFIG_USER_ONLY env->uncached_asr =3D ASR_MODE_USER; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a54dbe4260..9461ebad02 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -138,12 +138,11 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Er= ror **errp) =20 static void xtensa_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); XtensaCPU *cpu =3D XTENSA_CPU(obj); XtensaCPUClass *xcc =3D XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); env->config =3D xcc->config; =20 #ifndef CONFIG_USER_ONLY --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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X-Received-From: 2607:f8b0:4864:20::436 Subject: [Qemu-devel] [PATCH for-4.1 v2 31/36] cpu: Introduce CPUNegativeOffsetState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/exec/cpu-all.h | 25 +++++++++++++++++++++++++ include/exec/cpu-defs.h | 8 ++++++++ target/alpha/cpu.h | 1 + target/arm/cpu.h | 1 + target/cris/cpu.h | 1 + target/hppa/cpu.h | 1 + target/i386/cpu.h | 1 + target/lm32/cpu.h | 1 + target/m68k/cpu.h | 1 + target/microblaze/cpu.h | 5 +++-- target/mips/cpu.h | 1 + target/moxie/cpu.h | 1 + target/nios2/cpu.h | 2 ++ target/openrisc/cpu.h | 2 +- target/ppc/cpu.h | 2 ++ target/riscv/cpu.h | 1 + target/s390x/cpu.h | 1 + target/sh4/cpu.h | 1 + target/sparc/cpu.h | 1 + target/tilegx/cpu.h | 1 + target/tricore/cpu.h | 1 + target/unicore32/cpu.h | 1 + target/xtensa/cpu.h | 1 + 23 files changed, 58 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 1ed7d1e005..b42741f273 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -403,4 +403,29 @@ static inline CPUState *env_cpu(CPUArchState *env) { return &env_archcpu(env)->parent_obj; } + +/** + * env_neg(env) + * @env: The architecture environment + * + * Return the CPUNegativeOffsetState associated with the environment. + */ +static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) +{ + ArchCPU *arch_cpu =3D container_of(env, ArchCPU, env); + return &arch_cpu->neg; +} + +/** + * cpu_neg(cpu) + * @cpu: The generic CPUState + * + * Return the CPUNegativeOffsetState associated with the cpu. + */ +static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) +{ + ArchCPU *arch_cpu =3D container_of(cpu, ArchCPU, parent_obj); + return &arch_cpu->neg; +} + #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index fbe8945606..ad97991faf 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -227,4 +227,12 @@ typedef struct CPUTLB { =20 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 +/* + * This structure must be placed in ArchCPU immedately + * before CPUArchState, as a field named "neg". + */ +typedef struct CPUNegativeOffsetState { + /* Empty */ +} CPUNegativeOffsetState; + #endif diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 93919bbaa2..c63fa929f6 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -267,6 +267,7 @@ struct AlphaCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUAlphaState env; =20 /* This alarm doesn't exist in real hardware; we wish it did. */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df0409a703..cae0f509fc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -711,6 +711,7 @@ struct ARMCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUARMState env; =20 /* Coprocessor information */ diff --git a/target/cris/cpu.h b/target/cris/cpu.h index b87a559137..9191553cd7 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -180,6 +180,7 @@ struct CRISCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUCRISState env; }; =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 65986dacbf..21395c115c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -218,6 +218,7 @@ struct HPPACPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUHPPAState env; QEMUTimer *alarm_timer; }; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c5351bea7e..239f907f76 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1366,6 +1366,7 @@ struct X86CPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUX86State env; =20 bool hyperv_vapic; diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index deb83153b3..ff5c6893bc 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -186,6 +186,7 @@ struct LM32CPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPULM32State env; =20 uint32_t revision; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 2b180cf18d..087e73f9e2 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -160,6 +160,7 @@ struct M68kCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUM68KState env; }; =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index ff3abb61af..618fc8ff1f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -287,6 +287,9 @@ struct MicroBlazeCPU { =20 /*< public >*/ =20 + CPUNegativeOffsetState neg; + CPUMBState env; + /* Microblaze Configuration Settings */ struct { bool stackprot; @@ -306,8 +309,6 @@ struct MicroBlazeCPU { char *version; uint8_t pvr; } cfg; - - CPUMBState env; }; =20 =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 49c226b587..0cb8c94be5 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1048,6 +1048,7 @@ struct MIPSCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUMIPSState env; }; =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 00b1486659..9be228c383 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -87,6 +87,7 @@ typedef struct MoxieCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUMoxieState env; } MoxieCPU; =20 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 39a2471b18..875daa2d55 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -181,7 +181,9 @@ typedef struct Nios2CPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUNios2State env; + bool mmu_present; uint32_t pid_num_bits; uint32_t tlb_num_ways; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index ad2118b599..20bc673dda 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -313,8 +313,8 @@ typedef struct OpenRISCCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUOpenRISCState env; - } OpenRISCCPU; =20 =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 038e2499ed..f2f5a498a4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1172,7 +1172,9 @@ struct PowerPCCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUPPCState env; + int vcpu_id; uint32_t compat_pvr; PPCVirtualHypervisor *vhyp; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e71297ca7..dd5d6a59ee 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -208,6 +208,7 @@ typedef struct RISCVCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPURISCVState env; } RISCVCPU; =20 diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 3a6a5ada86..6020de558e 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -156,6 +156,7 @@ struct S390CPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUS390XState env; S390CPUModel *model; /* needed for live migration */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 02269c09b8..249b11bda2 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -204,6 +204,7 @@ struct SuperHCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUSH4State env; }; =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 02e40d381b..3c2b849b5a 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -529,6 +529,7 @@ struct SPARCCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUSPARCState env; }; =20 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 643b7dbd17..deb3e836ea 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -135,6 +135,7 @@ typedef struct TileGXCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUTLGState env; } TileGXCPU; =20 diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 9e60ef981b..8106c4be37 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -205,6 +205,7 @@ struct TriCoreCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUTriCoreState env; }; =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 12b8268f7b..83f9f36058 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -73,6 +73,7 @@ struct UniCore32CPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUUniCore32State env; }; =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 6fddac3a2b..8cb041c93d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -526,6 +526,7 @@ struct XtensaCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUXtensaState env; }; =20 --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.1 v2 32/36] cpu: Move icount_decr to CPUNegativeOffsetState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Amusingly, we had already ignored the comment to keep this value at the end of CPUState. This restores the minimum negative offset from TCG_AREG0 for code generation. For the couple of uses within qom/cpu.c, add a pointer from the CPUState object to the IcountDecr object within CPUNegativeOffsetState. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 1 + include/exec/cpu-defs.h | 3 ++- include/exec/gen-icount.h | 16 ++++++++++------ include/qom/cpu.h | 40 ++++++++++++++++++--------------------- accel/tcg/cpu-exec.c | 23 +++++++++++----------- accel/tcg/tcg-all.c | 6 ++---- accel/tcg/translate-all.c | 8 ++++---- cpus.c | 9 +++++---- qom/cpu.c | 4 ++-- 9 files changed, 56 insertions(+), 54 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b42741f273..be975acdb2 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -380,6 +380,7 @@ int cpu_exec(CPUState *cpu); static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) { cpu->parent_obj.env_ptr =3D &cpu->env; + cpu->parent_obj.icount_decr_ptr =3D &cpu->neg.icount_decr; } =20 /** diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ad97991faf..3971910653 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -33,6 +33,7 @@ #include "exec/hwaddr.h" #endif #include "exec/memattrs.h" +#include "qom/cpu.h" =20 #include "cpu-param.h" =20 @@ -232,7 +233,7 @@ typedef struct CPUTLB { * before CPUArchState, as a field named "neg". */ typedef struct CPUNegativeOffsetState { - /* Empty */ + IcountDecr icount_decr; } CPUNegativeOffsetState; =20 #endif diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 9cfa6ccce5..f7669b6841 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -5,8 +5,6 @@ =20 /* Helpers for instruction counting code generation. */ =20 -#define ENV_OFFSET offsetof(ArchCPU, env) - static TCGOp *icount_start_insn; =20 static inline void gen_tb_start(TranslationBlock *tb) @@ -21,7 +19,8 @@ static inline void gen_tb_start(TranslationBlock *tb) } =20 tcg_gen_ld_i32(count, cpu_env, - -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); + offsetof(ArchCPU, neg.icount_decr.u32) - + offsetof(ArchCPU, env)); =20 if (tb_cflags(tb) & CF_USE_ICOUNT) { imm =3D tcg_temp_new_i32(); @@ -39,7 +38,8 @@ static inline void gen_tb_start(TranslationBlock *tb) =20 if (tb_cflags(tb) & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, cpu_env, - -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.= low)); + offsetof(ArchCPU, neg.icount_decr.u16.low) - + offsetof(ArchCPU, env)); } =20 tcg_temp_free_i32(count); @@ -60,14 +60,18 @@ static inline void gen_tb_end(TranslationBlock *tb, int= num_insns) static inline void gen_io_start(void) { TCGv_i32 tmp =3D tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_i= o)); + tcg_gen_st_i32(tmp, cpu_env, + offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, env)); tcg_temp_free_i32(tmp); } =20 static inline void gen_io_end(void) { TCGv_i32 tmp =3D tcg_const_i32(0); - tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_i= o)); + tcg_gen_st_i32(tmp, cpu_env, + offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, env)); tcg_temp_free_i32(tmp); } =20 diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 1d6099e5d4..6431b0bf8b 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -229,17 +229,25 @@ typedef struct CPUClass { bool gdb_stop_before_watchpoint; } CPUClass; =20 +/* + * Low 16 bits: number of cycles left, used only in icount mode. + * High 16 bits: Set to -1 to force TCG to stop executing linked TBs + * for this CPU and return to its top level loop (even in non-icount mode). + * This allows a single read-compare-cbranch-write sequence to test + * for both decrementer underflow and exceptions. + */ +typedef union IcountDecr { + uint32_t u32; + struct { #ifdef HOST_WORDS_BIGENDIAN -typedef struct icount_decr_u16 { - uint16_t high; - uint16_t low; -} icount_decr_u16; + uint16_t high; + uint16_t low; #else -typedef struct icount_decr_u16 { - uint16_t low; - uint16_t high; -} icount_decr_u16; + uint16_t low; + uint16_t high; #endif + } u16; +} IcountDecr; =20 typedef struct CPUBreakpoint { vaddr pc; @@ -311,11 +319,6 @@ struct qemu_work_item; * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU * @singlestep_enabled: Flags for single-stepping. * @icount_extra: Instructions until next timer event. - * @icount_decr: Low 16 bits: number of cycles left, only used in icount m= ode. - * High 16 bits: Set to -1 to force TCG to stop executing linked TBs for t= his - * CPU and return to its top level loop (even in non-icount mode). - * This allows a single read-compare-cbranch-write sequence to test - * for both decrementer underflow and exceptions. * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution * requires that IO only be performed on the last instruction of a TB * so that interrupts take effect immediately. @@ -325,6 +328,7 @@ struct qemu_work_item; * @as: Pointer to the first AddressSpace, for the convenience of targets = which * only have a single AddressSpace * @env_ptr: Pointer to subclass-specific CPUArchState field. + * @icount_decr_ptr: Pointer to IcountDecr field within subclass. * @gdb_regs: Additional GDB registers. * @gdb_num_regs: Number of total registers accessible to GDB. * @gdb_num_g_regs: Number of registers in GDB 'g' packets. @@ -383,6 +387,7 @@ struct CPUState { MemoryRegion *memory; =20 void *env_ptr; /* CPUArchState */ + IcountDecr *icount_decr_ptr; =20 /* Accessed in parallel; all accesses must be atomic */ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; @@ -437,15 +442,6 @@ struct CPUState { =20 bool ignore_memory_transaction_failures; =20 - /* Note that this is accessed at the start of every TB via a negative - offset from AREG0. Leave this field at the end so as to make the - (absolute value) offset as small as possible. This reduces code - size, especially for hosts without large memory offsets. */ - union { - uint32_t u32; - icount_decr_u16 u16; - } icount_decr; - struct hax_vcpu_state *hax_vcpu; =20 int hvf_fd; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 45ef41ebb2..032a62672e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -54,7 +54,7 @@ typedef struct SyncClocks { #define MAX_DELAY_PRINT_RATE 2000000000LL #define MAX_NB_PRINTS 100 =20 -static void align_clocks(SyncClocks *sc, const CPUState *cpu) +static void align_clocks(SyncClocks *sc, CPUState *cpu) { int64_t cpu_icount; =20 @@ -62,7 +62,7 @@ static void align_clocks(SyncClocks *sc, const CPUState *= cpu) return; } =20 - cpu_icount =3D cpu->icount_extra + cpu->icount_decr.u16.low; + cpu_icount =3D cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; sc->diff_clk +=3D cpu_icount_to_ns(sc->last_cpu_icount - cpu_icount); sc->last_cpu_icount =3D cpu_icount; =20 @@ -105,15 +105,15 @@ static void print_delay(const SyncClocks *sc) } } =20 -static void init_delay_params(SyncClocks *sc, - const CPUState *cpu) +static void init_delay_params(SyncClocks *sc, CPUState *cpu) { if (!icount_align_option) { return; } sc->realtime_clock =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT); sc->diff_clk =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_= clock; - sc->last_cpu_icount =3D cpu->icount_extra + cpu->icount_decr.u16.low; + sc->last_cpu_icount + =3D cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; if (sc->diff_clk < max_delay) { max_delay =3D sc->diff_clk; } @@ -467,7 +467,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) if (cpu->exception_index < 0) { #ifndef CONFIG_USER_ONLY if (replay_has_exception() - && cpu->icount_decr.u16.low + cpu->icount_extra =3D=3D 0) { + && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra =3D= =3D 0) { /* try to cause an exception pending in the log */ cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()),= true); } @@ -525,7 +525,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * Ensure zeroing happens before reading cpu->exit_request or * cpu->interrupt_request (see also smp_wmb in cpu_exit()) */ - atomic_mb_set(&cpu->icount_decr.u16.high, 0); + atomic_mb_set(&cpu_neg(cpu)->icount_decr.u16.high, 0); =20 if (unlikely(atomic_read(&cpu->interrupt_request))) { int interrupt_request; @@ -596,8 +596,9 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, } =20 /* Finally, check if we need to exit to the main loop. */ - if (unlikely(atomic_read(&cpu->exit_request) - || (use_icount && cpu->icount_decr.u16.low + cpu->icount_extra =3D= =3D 0))) { + if (unlikely(atomic_read(&cpu->exit_request)) + || (use_icount + && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra =3D= =3D 0)) { atomic_set(&cpu->exit_request, 0); if (cpu->exception_index =3D=3D -1) { cpu->exception_index =3D EXCP_INTERRUPT; @@ -624,7 +625,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, Tran= slationBlock *tb, } =20 *last_tb =3D NULL; - insns_left =3D atomic_read(&cpu->icount_decr.u32); + insns_left =3D atomic_read(&cpu_neg(cpu)->icount_decr.u32); if (insns_left < 0) { /* Something asked us to stop executing chained TBs; just * continue round the main loop. Whatever requested the exit @@ -643,7 +644,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, Tran= slationBlock *tb, cpu_update_icount(cpu); /* Refill decrementer and continue execution. */ insns_left =3D MIN(0xffff, cpu->icount_budget); - cpu->icount_decr.u16.low =3D insns_left; + cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; cpu->icount_extra =3D cpu->icount_budget - insns_left; if (!cpu->icount_extra) { /* Execute any remaining instructions, then let the main loop diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 3d25bdcc17..9b215dcc5a 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -28,13 +28,12 @@ #include "sysemu/sysemu.h" #include "qom/object.h" #include "qemu-common.h" -#include "qom/cpu.h" +#include "cpu.h" #include "sysemu/cpus.h" #include "qemu/main-loop.h" =20 unsigned long tcg_tb_size; =20 -#ifndef CONFIG_USER_ONLY /* mask must never be zero, except for A20 change call */ static void tcg_handle_interrupt(CPUState *cpu, int mask) { @@ -51,7 +50,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) if (!qemu_cpu_is_self(cpu)) { qemu_cpu_kick(cpu); } else { - atomic_set(&cpu->icount_decr.u16.high, -1); + atomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); if (use_icount && !cpu->can_do_io && (mask & ~old_mask) !=3D 0) { @@ -59,7 +58,6 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) } } } -#endif =20 static int tcg_init(MachineState *ms) { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 2cc5d3c59f..ed19a41d55 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -363,7 +363,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, assert(use_icount); /* Reset the cycle counter to the start of the block and shift if to the number of actually executed instructions */ - cpu->icount_decr.u16.low +=3D num_insns - i; + cpu_neg(cpu)->icount_decr.u16.low +=3D num_insns - i; } restore_state_to_opc(env, tb, data); =20 @@ -2162,7 +2162,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 && env->active_tc.PC !=3D tb->pc) { env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - cpu->icount_decr.u16.low++; + cpu_neg(cpu)->icount_decr.u16.low++; env->hflags &=3D ~MIPS_HFLAG_BMASK; n =3D 2; } @@ -2170,7 +2170,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) !=3D 0 && env->pc !=3D tb->pc) { env->pc -=3D 2; - cpu->icount_decr.u16.low++; + cpu_neg(cpu)->icount_decr.u16.low++; env->flags &=3D ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); n =3D 2; } @@ -2344,7 +2344,7 @@ void cpu_interrupt(CPUState *cpu, int mask) { g_assert(qemu_mutex_iothread_locked()); cpu->interrupt_request |=3D mask; - atomic_set(&cpu->icount_decr.u16.high, -1); + atomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); } =20 /* diff --git a/cpus.c b/cpus.c index e83f72b48b..b123ef541e 100644 --- a/cpus.c +++ b/cpus.c @@ -237,7 +237,8 @@ void qemu_tcg_configure(QemuOpts *opts, Error **errp) */ static int64_t cpu_get_icount_executed(CPUState *cpu) { - return cpu->icount_budget - (cpu->icount_decr.u16.low + cpu->icount_ex= tra); + return (cpu->icount_budget - + (cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra)); } =20 /* @@ -1385,12 +1386,12 @@ static void prepare_icount_for_run(CPUState *cpu) * each vCPU execution. However u16.high can be raised * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt */ - g_assert(cpu->icount_decr.u16.low =3D=3D 0); + g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); g_assert(cpu->icount_extra =3D=3D 0); =20 cpu->icount_budget =3D tcg_get_icount_limit(); insns_left =3D MIN(0xffff, cpu->icount_budget); - cpu->icount_decr.u16.low =3D insns_left; + cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; cpu->icount_extra =3D cpu->icount_budget - insns_left; =20 replay_mutex_lock(); @@ -1404,7 +1405,7 @@ static void process_icount_data(CPUState *cpu) cpu_update_icount(cpu); =20 /* Reset the counters */ - cpu->icount_decr.u16.low =3D 0; + cpu_neg(cpu)->icount_decr.u16.low =3D 0; cpu->icount_extra =3D 0; cpu->icount_budget =3D 0; =20 diff --git a/qom/cpu.c b/qom/cpu.c index a8d2958956..07a5ab688e 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -114,7 +114,7 @@ void cpu_exit(CPUState *cpu) atomic_set(&cpu->exit_request, 1); /* Ensure cpu_exec will see the exit request after TCG has exited. */ smp_wmb(); - atomic_set(&cpu->icount_decr.u16.high, -1); + atomic_set(&cpu->icount_decr_ptr->u16.high, -1); } =20 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, @@ -265,7 +265,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->mem_io_pc =3D 0; cpu->mem_io_vaddr =3D 0; cpu->icount_extra =3D 0; - atomic_set(&cpu->icount_decr.u32, 0); + atomic_set(&cpu->icount_decr_ptr->u32, 0); cpu->can_do_io =3D 1; cpu->exception_index =3D -1; cpu->crash_occurred =3D false; --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553815592220738.7231691356744; Thu, 28 Mar 2019 16:26:32 -0700 (PDT) Received: from localhost ([127.0.0.1]:43248 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9ePl-0006sh-3A for importer@patchew.org; Thu, 28 Mar 2019 19:26:29 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42236) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKg-0001dn-IC for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e5F-0003ME-P5 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:05:23 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:41224) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e5E-0003Ep-Sq for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:05:17 -0400 Received: by mail-pg1-x543.google.com with SMTP id f6so224762pgs.8 for ; Thu, 28 Mar 2019 16:05:03 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH for-4.1 v2 33/36] cpu: Move the softmmu tlb to CPUNegativeOffsetState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have for some time had code within the tcg backends to handle large positive offsets from env. This move makes sure that need not happen. Indeed, we are able to assert at build time that simple offsets suffice for all hosts. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/exec/cpu-defs.h | 22 +++++++++++++------- tcg/aarch64/tcg-target.inc.c | 29 ++++++-------------------- tcg/arm/tcg-target.inc.c | 40 ++++++++---------------------------- tcg/i386/tcg-target.inc.c | 6 ++++-- tcg/mips/tcg-target.inc.c | 39 ++++++++--------------------------- tcg/ppc/tcg-target.inc.c | 30 ++++++++------------------- tcg/riscv/tcg-target.inc.c | 31 +++++++--------------------- tcg/s390/tcg-target.inc.c | 11 +++++----- tcg/sparc/tcg-target.inc.c | 32 +++++++++-------------------- 9 files changed, 74 insertions(+), 166 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 3971910653..4cde7d611c 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -178,13 +178,14 @@ typedef struct CPUTLBDesc { =20 /* * Data elements that are per MMU mode, accessed by the fast path. + * The structure is aligned to aid loading the pair with one insn. */ typedef struct CPUTLBDescFast { /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ uintptr_t mask; /* The array of tlb entries itself. */ CPUTLBEntry *table; -} CPUTLBDescFast; +} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); =20 /* * Data elements that are shared between all MMU modes. @@ -211,28 +212,35 @@ typedef struct CPUTLBCommon { /* * The entire softmmu tlb, for all MMU modes. * The meaning of each of the MMU modes is defined in the target code. + * Since this is placed within CPUNegativeOffsetState, the smallest + * negative offsets are at the end of the struct. */ typedef struct CPUTLB { - CPUTLBDescFast f[NB_MMU_MODES]; - CPUTLBDesc d[NB_MMU_MODES]; CPUTLBCommon c; + CPUTLBDesc d[NB_MMU_MODES]; + CPUTLBDescFast f[NB_MMU_MODES]; } CPUTLB; =20 -/* There are target-specific members named "tlb". This is temporary. */ -#define CPU_COMMON CPUTLB tlb_; -#define env_tlb(ENV) (&(ENV)->tlb_) +#define env_tlb(ENV) (&env_neg(ENV)->tlb) + +/* This will be used by TCG backends to compute offsets. */ +#define TLB_MASK_TABLE_OFS(IDX) \ + ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) =20 #else =20 -#define CPU_COMMON /* Nothing */ +typedef struct CPUTLB { } CPUTLB; =20 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 +#define CPU_COMMON /* Nothing */ + /* * This structure must be placed in ArchCPU immedately * before CPUArchState, as a field named "neg". */ typedef struct CPUNegativeOffsetState { + CPUTLB tlb; IcountDecr icount_decr; } CPUNegativeOffsetState; =20 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 5e6af10faf..ac765137ae 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1451,9 +1451,9 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr; } =20 -/* We expect to use a 24-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0xffffff); +/* We expect to use a 7-bit scaled negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); =20 /* Load and compare a TLB entry, emitting the conditional jump to the slow path for the failure case, which will be patched later when finali= zing @@ -1463,8 +1463,9 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg ad= dr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int mask_ofs =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_ofs =3D offsetof(CPUArchState, tlb_.f[mem_index].table); + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); unsigned a_bits =3D get_alignment_bits(opc); unsigned s_bits =3D opc & MO_SIZE; unsigned a_mask =3D (1u << a_bits) - 1; @@ -1473,24 +1474,6 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg a= ddr_reg, TCGMemOp opc, TCGType mask_type; uint64_t compare_mask; =20 - if (table_ofs > 0xfff) { - int table_hi =3D table_ofs & ~0xfff; - int mask_hi =3D mask_ofs & ~0xfff; - - table_base =3D TCG_REG_X1; - if (mask_hi =3D=3D table_hi) { - mask_base =3D table_base; - } else if (mask_hi) { - mask_base =3D TCG_REG_X0; - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, - mask_base, TCG_AREG0, mask_hi); - } - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, - table_base, TCG_AREG0, table_hi); - mask_ofs -=3D mask_hi; - table_ofs -=3D table_hi; - } - mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); =20 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 04c2eebb41..4a8c12e9a4 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1235,9 +1235,9 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg= argreg, =20 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) =20 -/* We expect to use a 20-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0xfffff); +/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); =20 /* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ @@ -1247,39 +1247,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, { int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 - if (table_off > 0xfff) { - int mask_hi =3D mask_off & ~0xfff; - int table_hi =3D table_off & ~0xfff; - int rot; - - table_base =3D TCG_REG_R2; - if (mask_hi =3D=3D table_hi) { - mask_base =3D table_base; - } else if (mask_hi) { - mask_base =3D TCG_REG_TMP; - rot =3D encode_imm(mask_hi); - assert(rot >=3D 0); - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, mask_base, TCG_AREG0, - rotl(mask_hi, rot) | (rot << 7)); - } - rot =3D encode_imm(table_hi); - assert(rot >=3D 0); - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, table_base, TCG_AREG0, - rotl(table_hi, rot) | (rot << 7)); - - mask_off -=3D mask_hi; - table_off -=3D table_hi; - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_AREG0, table_off); =20 /* Extract the tlb index from the address into TMP. */ tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrl= o, diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 1bd33389c9..f9598b7593 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1654,10 +1654,12 @@ static inline void tcg_out_tlb_load(TCGContext *s, = TCGReg addrlo, TCGReg addrhi, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); =20 tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_.f[mem_index].mask)); + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, mask)); =20 tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_.f[mem_index].table)); + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, table)); =20 /* If the required alignment is at least as large as the access, simply copy the address and mask. For lesser alignments, check that we do= n't diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index b827579317..55d8cdf4c9 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1201,6 +1201,10 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int= i, TCGReg al, TCGReg ah) return i; } =20 +/* We expect to use a 16-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + /* * Perform the tlb comparison operation. * The complete host address is placed in BASE. @@ -1214,42 +1218,17 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg = base, TCGReg addrl, unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); int mem_index =3D get_mmuidx(oi); - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); int add_off =3D offsetof(CPUTLBEntry, addend); int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; target_ulong mask; =20 - if (table_off > 0x7fff) { - int mask_hi =3D mask_off - (int16_t)mask_off; - int table_hi =3D table_off - (int16_t)table_off; - - table_base =3D TCG_TMP1; - if (likely(mask_hi =3D=3D table_hi)) { - mask_base =3D table_base; - tcg_out_opc_imm(s, OPC_LUI, mask_base, TCG_REG_ZERO, mask_hi >= > 16); - tcg_out_opc_reg(s, ALIAS_PADD, mask_base, mask_base, TCG_AREG0= ); - mask_off -=3D mask_hi; - table_off -=3D mask_hi; - } else { - if (mask_hi !=3D 0) { - mask_base =3D TCG_TMP0; - tcg_out_opc_imm(s, OPC_LUI, - mask_base, TCG_REG_ZERO, mask_hi >> 16); - tcg_out_opc_reg(s, ALIAS_PADD, - mask_base, mask_base, TCG_AREG0); - } - table_off -=3D mask_off; - mask_off -=3D mask_hi; - tcg_out_opc_imm(s, ALIAS_PADDI, table_base, mask_base, mask_of= f); - } - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); =20 /* Extract the TLB index from the address into TMP3. */ tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 1f717745c1..7e7343bb7b 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1505,6 +1505,10 @@ static void * const qemu_st_helpers[16] =3D { [MO_BEQ] =3D helper_be_stq_mmu, }; =20 +/* We expect to use a 16-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + /* Perform the TLB load and compare. Places the result of the comparison in CR7, loads the addend of the TLB into R3, and returns the register containing the guest address (zero-extended into R4). Clobbers R0 and = R2. */ @@ -1517,31 +1521,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMe= mOp opc, =3D (is_read ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 - if (table_off > 0x7fff) { - int mask_hi =3D mask_off - (int16_t)mask_off; - int table_hi =3D table_off - (int16_t)table_off; - - table_base =3D TCG_REG_R4; - if (mask_hi =3D=3D table_hi) { - mask_base =3D table_base; - } else if (mask_hi) { - mask_base =3D TCG_REG_R3; - tcg_out32(s, ADDIS | TAI(mask_base, TCG_AREG0, mask_hi >> 16)); - } - tcg_out32(s, ADDIS | TAI(table_base, TCG_AREG0, table_hi >> 16)); - mask_off -=3D mask_hi; - table_off -=3D table_hi; - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index c1f9c784bc..3198e16486 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -961,6 +961,10 @@ static void * const qemu_st_helpers[16] =3D { /* We don't support oversize guests */ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); =20 +/* We expect to use a 12-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) @@ -970,32 +974,11 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg ad= drl, unsigned a_bits =3D get_alignment_bits(opc); tcg_target_long compare_mask; int mem_index =3D get_mmuidx(oi); - int mask_off, table_off; + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; =20 - mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - if (table_off > 0x7ff) { - int mask_hi =3D mask_off - sextreg(mask_off, 0, 12); - int table_hi =3D table_off - sextreg(table_off, 0, 12); - - if (likely(mask_hi =3D=3D table_hi)) { - mask_base =3D table_base =3D TCG_REG_TMP1; - tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi); - tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0); - mask_off -=3D mask_hi; - table_off -=3D mask_hi; - } else { - mask_base =3D TCG_REG_TMP0; - table_base =3D TCG_REG_TMP1; - tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi); - tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0); - table_off -=3D mask_off; - mask_off -=3D mask_hi; - tcg_out_opc_imm(s, OPC_ADDI, table_base, mask_base, mask_off); - } - } - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off); =20 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 3a8794d9bd..6eefef53a1 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1537,9 +1537,9 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= MemOp opc, TCGReg data, #if defined(CONFIG_SOFTMMU) #include "tcg-ldst.inc.c" =20 -/* We're expecting to use a 20-bit signed offset on the tlb memory ops. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0x7ffff); +/* We're expecting to use a 20-bit negative offset on the tlb memory ops. = */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); =20 /* Load and compare a TLB entry, leaving the flags set. Loads the TLB addend into R2. Returns a register with the santitized guest address. = */ @@ -1550,8 +1550,9 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg = addr_reg, TCGMemOp opc, unsigned a_bits =3D get_alignment_bits(opc); unsigned s_mask =3D (1 << s_bits) - 1; unsigned a_mask =3D (1 << a_bits) - 1; - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); int ofs, a_off; uint64_t tlb_mask; =20 diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index be10124e11..fe7524a802 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1061,6 +1061,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int c= ount) } =20 #if defined(CONFIG_SOFTMMU) + +/* We expect to use a 13-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); + /* Perform the TLB load and compare. =20 Inputs: @@ -1077,9 +1082,9 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int co= unt) static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, TCGMemOp opc, int which) { - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg base =3D TCG_AREG0; + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); const TCGReg r0 =3D TCG_REG_O0; const TCGReg r1 =3D TCG_REG_O1; const TCGReg r2 =3D TCG_REG_O2; @@ -1087,26 +1092,9 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg= addr, int mem_index, unsigned a_bits =3D get_alignment_bits(opc); tcg_target_long compare_mask; =20 - if (!check_fit_i32(table_off, 13)) { - int table_hi; - - base =3D r1; - if (table_off <=3D 2 * 0xfff) { - table_hi =3D 0xfff; - tcg_out_arithi(s, base, TCG_AREG0, table_hi, ARITH_ADD); - } else { - table_hi =3D table_off & ~0x3ff; - tcg_out_sethi(s, base, table_hi); - tcg_out_arith(s, base, TCG_AREG0, base, ARITH_ADD); - } - mask_off -=3D table_hi; - table_off -=3D table_hi; - tcg_debug_assert(check_fit_i32(mask_off, 13)); - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, r0, base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, r1, base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553815558229443.3552099094402; Thu, 28 Mar 2019 16:25:58 -0700 (PDT) Received: from localhost ([127.0.0.1]:43241 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eP9-0006LN-WB for importer@patchew.org; Thu, 28 Mar 2019 19:25:52 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42393) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKk-0001jU-3x for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e5F-0003Lb-3Q for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:05:18 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:37822) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e5E-0003FE-N6 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:05:17 -0400 Received: by mail-pf1-x429.google.com with SMTP id 8so85538pfr.4 for ; Thu, 28 Mar 2019 16:05:04 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. [66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.05.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:05:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=7ck5Yi11H9+7Tr2R/vReXNRigmwOrQ9XQ3CLVljTrXQ=; b=g/B1gL53GLumr0V9Uo0I9I3gbC7VhL7i/tYYRUT/0pe7kuYv6BJHA+MStg8RV3Vrh2 rd8Stc1O8SVkir2PN9hSA18j7H96N5ug4pqPzN6JIvu5kuHzXTwxH9i0SF3HPNk92dI9 eLOPoRNtozR9bF0PxTzV7rw6yxVHOpe3KsSj8zFBfTCHl9qpJu+UqJ1kjRgTBXnITrPP RqSZeLTsxxRifLMpWG+rhziE8UdtDtXZ5xVySmxx/DTNX3t6t1QeZxyGDNpKB+iJ6EUq 4AvhxGYnLvoReCuKoFuABtzG236XcE/7YNRAgn8rGQvB9TuAtdjbNdwc/laBNF721XTg T1fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=7ck5Yi11H9+7Tr2R/vReXNRigmwOrQ9XQ3CLVljTrXQ=; b=Ir85uXlLnP0aeD2tpFIbm1keXXDxWmMDGth76xyqv8EwYEWKhrY5T7Qk9oyaEpqpj2 25Nvh4uRTe5CvxatGZ8I715iMfLjxDljV2Or1uMp/JYcRg3Cr/SsjrYlGtc0M5jNgkeK bTvJnY9nhiEO7CALKTPFjIVYSe/M8V9fCxPMri4nr19m/LnwWMVfDoUEmHFxYcjsgASB vC0kwrTWwKgryRBZNwdOykRsPnSW0rDRwtOW4+5RjYX/MuXjLzu0EbecAtaevFEk5ZrC +imXLgP0nKTyRljQFTaHqwUsTwr3YuhfrZknH75D5hQx7iOtUfvaEmRHp1MbD6ZKX+P4 Z6EA== X-Gm-Message-State: APjAAAUo4b2evD04DvcHN90b6rnMPsCeVjBIxYMV+bJlR+EHtvtL+ooo JjtU3G01i7sDZLgNaYJy0O8Y2HSB644= X-Google-Smtp-Source: APXvYqxo8JRavHeQh6gOWSeLBIzlbXYpRWuft/44SyUVjURHjkcy28nsVj0NVFqudMihyDDU3KVKfQ== X-Received: by 2002:a63:4e57:: with SMTP id o23mr40211352pgl.368.1553814303704; Thu, 28 Mar 2019 16:05:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:04:02 -1000 Message-Id: <20190328230404.12909-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PATCH for-4.1 v2 34/36] cpu: Remove CPU_COMMON X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This macro is now always empty, so remove it. This leaves the entire contents of CPUArchState under the control of the guest architecture. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/exec/cpu-defs.h | 2 -- target/alpha/cpu.h | 3 --- target/arm/cpu.h | 4 +--- target/cris/cpu.h | 2 -- target/hppa/cpu.h | 3 --- target/i386/cpu.h | 4 +--- target/lm32/cpu.h | 2 -- target/m68k/cpu.h | 2 -- target/microblaze/cpu.h | 2 -- target/mips/cpu.h | 2 -- target/moxie/cpu.h | 3 --- target/nios2/cpu.h | 2 -- target/openrisc/cpu.h | 2 -- target/ppc/cpu.h | 2 -- target/riscv/cpu.h | 4 ---- target/s390x/cpu.h | 2 -- target/sh4/cpu.h | 2 -- target/sparc/cpu.h | 2 -- target/tilegx/cpu.h | 2 -- target/tricore/cpu.h | 2 -- target/unicore32/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- 22 files changed, 2 insertions(+), 51 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 4cde7d611c..1f75a97701 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -233,8 +233,6 @@ typedef struct CPUTLB { } CPUTLB; =20 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 -#define CPU_COMMON /* Nothing */ - /* * This structure must be placed in ArchCPU immedately * before CPUArchState, as a field named "neg". diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index c63fa929f6..3b2751a45c 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -246,9 +246,6 @@ struct CPUAlphaState { /* This alarm doesn't exist in real hardware; we wish it did. */ uint64_t alarm_expire; =20 - /* Those resources are used only in QEMU core */ - CPU_COMMON - int error_code; =20 uint32_t features; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cae0f509fc..d7a444a5ff 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -635,9 +635,7 @@ typedef struct CPUARMState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - - /* Fields after CPU_COMMON are preserved across CPU reset. */ + /* Fields after this point are preserved across CPU reset. */ =20 /* Internal CPU feature flags. */ uint64_t features; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 9191553cd7..d63d5c29f6 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -163,8 +163,6 @@ typedef struct CPUCRISState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Members from load_info on are preserved across resets. */ void *load_info; } CPUCRISState; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 21395c115c..93e64414a0 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -197,9 +197,6 @@ struct CPUHPPAState { target_ureg cr_back[2]; /* back of cr17/cr18 */ target_ureg shadow[7]; /* shadow registers */ =20 - /* Those resources are used only in QEMU core */ - CPU_COMMON - /* ??? The number of entries isn't specified by the architecture. */ /* ??? Implement a unified itlb/dtlb for the moment. */ /* ??? We should use a more intelligent data structure. */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 239f907f76..8e167dc2a8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1286,9 +1286,7 @@ typedef struct CPUX86State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - - /* Fields after CPU_COMMON are preserved across CPU reset. */ + /* Fields after this point are preserved across CPU reset. */ =20 /* processor features (e.g. for CPUID insn) */ /* Minimum level/xlevel/xlevel2, based on CPU model + features */ diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index ff5c6893bc..473809257b 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -159,8 +159,6 @@ struct CPULM32State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t eba; /* exception base address */ uint32_t deba; /* debug exception base address */ diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 087e73f9e2..3efd038df9 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -143,8 +143,6 @@ typedef struct CPUM68KState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t features; } CPUM68KState; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 618fc8ff1f..aa84480913 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -266,8 +266,6 @@ struct CPUMBState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* These fields are preserved on reset. */ =20 struct { diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 0cb8c94be5..f2bf81f4ee 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1021,8 +1021,6 @@ struct CPUMIPSState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 9be228c383..ac35507db6 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -45,9 +45,6 @@ typedef struct CPUMoxieState { =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - - CPU_COMMON - } CPUMoxieState; =20 #include "qom/cpu.h" diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 875daa2d55..326ce16a9b 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -166,8 +166,6 @@ struct CPUNios2State { =20 uint32_t irq_pending; #endif - - CPU_COMMON }; =20 /** diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 20bc673dda..963c3be65e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -286,8 +286,6 @@ typedef struct CPUOpenRISCState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t cpucfgr; /* CPU configure register */ =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f2f5a498a4..55099564db 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -993,8 +993,6 @@ struct CPUPPCState { int access_type; /* when a memory exception occurs, the access type is stored here */ =20 - CPU_COMMON - /* MMU context - only relevant for full system emulation */ #if !defined(CONFIG_USER_ONLY) #if defined(TARGET_PPC64) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dd5d6a59ee..b3800daed6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -169,10 +169,6 @@ struct CPURISCVState { =20 float_status fp_status; =20 - /* QEMU */ - CPU_COMMON - - /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ }; =20 diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 6020de558e..a543acffa8 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -114,8 +114,6 @@ struct CPUS390XState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - #if !defined(CONFIG_USER_ONLY) uint32_t core_id; /* PoP "CPU address", same as cpu_index */ uint64_t cpuid; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 249b11bda2..a67efb83b5 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -179,8 +179,6 @@ typedef struct CPUSH4State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved over CPU reset. */ int id; /* CPU model */ =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 3c2b849b5a..c085d5e8f1 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -446,8 +446,6 @@ struct CPUSPARCState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ target_ulong version; uint32_t nwindows; diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index deb3e836ea..c2acb43c2b 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -93,8 +93,6 @@ typedef struct CPUTLGState { =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - - CPU_COMMON } CPUTLGState; =20 #include "qom/cpu.h" diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 8106c4be37..5ceb801a11 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -184,8 +184,6 @@ struct CPUTriCoreState { int error_code; uint32_t hflags; /* CPU State */ =20 - CPU_COMMON - /* Internal CPU feature flags. */ uint64_t features; =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 83f9f36058..046d4fedb4 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -55,8 +55,6 @@ typedef struct CPUUniCore32State { float_status fp_status; } ucf64; =20 - CPU_COMMON - /* Internal CPU feature flags. */ uint32_t features; =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 8cb041c93d..52ee31a53d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -511,8 +511,6 @@ typedef struct CPUXtensaState { =20 /* Watchpoints for DBREAK registers */ struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; - - CPU_COMMON } CPUXtensaState; =20 /** --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553815756255643.3527402889348; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.1 v2 35/36] tcg/aarch64: Use LDP to load tlb mask+table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index ac765137ae..979efbcfe4 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1463,14 +1463,11 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); unsigned a_bits =3D get_alignment_bits(opc); unsigned s_bits =3D opc & MO_SIZE; unsigned a_mask =3D (1u << a_bits) - 1; unsigned s_mask =3D (1u << s_bits) - 1; - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0, x3; + TCGReg x3; TCGType mask_type; uint64_t compare_mask; =20 @@ -1478,8 +1475,8 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg ad= dr_reg, TCGMemOp opc, ? TCG_TYPE_I64 : TCG_TYPE_I32); =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, mask_type, TCG_REG_X0, mask_base, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, table_base, table_ofs); + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index), 1, 0); =20 /* Extract the TLB index from the address into X0. */ tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, --=20 2.17.1 From nobody Fri May 3 04:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553815413078145.67947452236695; Thu, 28 Mar 2019 16:23:33 -0700 (PDT) Received: from localhost ([127.0.0.1]:43187 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eMr-00038L-Nv for importer@patchew.org; Thu, 28 Mar 2019 19:23:29 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKk-0001km-6C for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e5D-0003J9-5c for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:05:16 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:37594) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e5B-0003G7-P9 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:05:14 -0400 Received: by mail-pl1-x642.google.com with SMTP id q6so67838pll.4 for ; Thu, 28 Mar 2019 16:05:08 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH for-4.1 v2 36/36] tcg/arm: Use LDRD to load tlb mask+table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 109 +++++++++++++++++++-------------------- 1 file changed, 52 insertions(+), 57 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 4a8c12e9a4..7601eff16e 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -278,6 +278,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); #endif break; @@ -1253,75 +1254,69 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_AREG0, table_off); - - /* Extract the tlb index from the address into TMP. */ - tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrl= o, - SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); - /* - * Add the tlb_table pointer, creating the CPUTLBEntry address in R2. - * Load the tlb comparator into R0/R1 and the fast path addend into R2. + * We don't support inline unaligned acceses, but we can easily + * support overalignment checks. */ - if (cmp_off =3D=3D 0) { - if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_T= MP); - } else { - tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_T= MP); - } - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, - TCG_REG_R2, TCG_REG_R2, TCG_REG_TMP, 0); - if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off); - } else { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off); - } - } - if (!use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2, cmp_off + 4); - } - - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, - offsetof(CPUTLBEntry, addend)); - - /* Check alignment. We don't support inline unaligned acceses, - but we can easily support overalignment checks. */ if (a_bits < s_bits) { a_bits =3D s_bits; } =20 - if (use_armv7_instructions) { - tcg_target_ulong mask =3D ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1)= ); - int rot =3D encode_imm(mask); - - if (rot >=3D 0) {=20 - tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo, - rotl(mask, rot) | (rot << 7)); - } else { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - addrlo, TCG_REG_TMP, 0); - } - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP,= 0); + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + if (use_armv6_instructions) { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); } else { - if (a_bits) { - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, - (1 << a_bits) - 1); - } - tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, - 0, TCG_REG_R0, TCG_REG_TMP, - SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R1, TCG_AREG0, table_off); } =20 + /* Extract the tlb index from the address into R0. */ + tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, + SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); + + /* + * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. + * Load the tlb comparator into R2/R3 and the fast path addend into R1. + */ + if (cmp_off =3D=3D 0) { + if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } else { + tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, + TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); + if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } else { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } + } + if (!use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R3, TCG_REG_R1, cmp_off + 4); + } + + /* Shift the non-page bits out. */ + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, addrlo, + SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, + offsetof(CPUTLBEntry, addend)); + + /* Check alignment, check comparators. */ + if (a_bits) { + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, (1 << a_bits) - = 1); + } + tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, 0, + TCG_REG_R2, TCG_REG_R0, SHIFT_IMM_LSL(TARGET_PAGE_BITS= )); + if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0); + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); } =20 - return TCG_REG_R2; + return TCG_REG_R1; } =20 /* Record the context of a call to the out of line helper code for the slow --=20 2.17.1