From nobody Sun May 5 20:22:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553767549819381.12645634167757; Thu, 28 Mar 2019 03:05:49 -0700 (PDT) Received: from localhost ([127.0.0.1]:33747 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9Ruk-0001kd-8d for importer@patchew.org; Thu, 28 Mar 2019 06:05:38 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39378) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9Rsa-0008Sd-RQ for qemu-devel@nongnu.org; Thu, 28 Mar 2019 06:03:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9RqI-00031R-Hx for qemu-devel@nongnu.org; Thu, 28 Mar 2019 06:01:03 -0400 Received: from 7.mo2.mail-out.ovh.net ([188.165.48.182]:39962) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h9RqI-00030g-BM for qemu-devel@nongnu.org; Thu, 28 Mar 2019 06:01:02 -0400 Received: from player731.ha.ovh.net (unknown [10.109.159.140]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id 0711418C8A8 for ; Thu, 28 Mar 2019 11:00:59 +0100 (CET) Received: from kaod.org (lfbn-1-2226-17.w90-76.abo.wanadoo.fr [90.76.48.17]) (Authenticated sender: clg@kaod.org) by player731.ha.ovh.net (Postfix) with ESMTPSA id 39FD940B1DAF; Thu, 28 Mar 2019 10:00:49 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 28 Mar 2019 11:00:44 +0100 Message-Id: <20190328100044.11408-1-clg@kaod.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Ovh-Tracer-Id: 11194541302555380710 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedutddrkeeggdduvdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 188.165.48.182 Subject: [Qemu-devel] [PATCH] spapr/irq: Add XIVE sanity checks on non-P9 machines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" On non-P9 machines, the XIVE interrupt mode is not advertised, see spapr_dt_ov5_platform_support(). Add a couple of checks on the machine configuration to filter bogus setups and prevent OS failures : Interrupt modes CPU/Compat XICS XIVE dual P8/P8 OK QEMU failure (1) OK (3) P9/P8 OK QEMU failure (2) OK (3) P9/P9 OK OK OK (1) CPU exception model is incompatible with XIVE and the presenters will fail to realize. (2) CPU exception model is compatible with XIVE, but the XIVE CAS advertisement is dropped when in POWER8 mode. So we could ended up booting with the XIVE DT properties but without the HCALLs. Avoid confusing Linux with such settings and fail under QEMU. (3) force XICS in machine init Remove the check on XIVE-only machines in spapr_machine_init(), which has now become redundant. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 8 +------- hw/ppc/spapr_irq.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 7 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index adde36a01da3..33ab7b683ba2 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2806,13 +2806,7 @@ static void spapr_machine_init(MachineState *machine) =20 /* advertise XIVE on POWER9 machines */ if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) { - if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3= _00, - 0, spapr->max_compat_pvr)) { - spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); - } else if (spapr->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) { - error_report("XIVE-only machines require a POWER9 CPU"); - exit(1); - } + spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); } =20 /* init CPUs */ diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 5809c955501c..b1f79ea9def6 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -16,6 +16,7 @@ #include "hw/ppc/spapr_xive.h" #include "hw/ppc/xics.h" #include "hw/ppc/xics_spapr.h" +#include "cpu-models.h" #include "sysemu/kvm.h" =20 #include "trace.h" @@ -566,12 +567,55 @@ SpaprIrq spapr_irq_dual =3D { .get_nodename =3D spapr_irq_get_nodename_dual, }; =20 + +static void spapr_irq_check(SpaprMachineState *spapr, Error **errp) +{ + MachineState *machine =3D MACHINE(spapr); + + /* + * Sanity checks on non-P9 machines. On these, XIVE is not + * advertised, see spapr_dt_ov5_platform_support() + */ + if (!ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, + 0, spapr->max_compat_pvr)) { + /* + * If the 'dual' interrupt mode is selected, force XICS as CAS + * negotiation is useless. + */ + if (spapr->irq =3D=3D &spapr_irq_dual) { + spapr->irq =3D &spapr_irq_xics; + return; + } + + /* + * Non-P9 machines using only XIVE is a bogus setup. We have two + * scenarios to take into account because of the compat mode: + * + * 1. POWER7/8 machines should fail to init later on when creating + * the XIVE interrupt presenters because a POWER9 exception + * model is required. + + * 2. POWER9 machines using the POWER8 compat mode won't fail and + * will let the OS boot with a partial XIVE setup : DT + * properties but no hcalls. + * + * To cover both and not confuse the OS, add an early failure in + * QEMU. + */ + if (spapr->irq =3D=3D &spapr_irq_xive) { + error_setg(errp, "XIVE-only machines require a POWER9 CPU"); + return; + } + } +} + /* * sPAPR IRQ frontend routines for devices */ void spapr_irq_init(SpaprMachineState *spapr, Error **errp) { MachineState *machine =3D MACHINE(spapr); + Error *local_err =3D NULL; =20 if (machine_kernel_irqchip_split(machine)) { error_setg(errp, "kernel_irqchip split mode not supported on pseri= es"); @@ -584,6 +628,12 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **= errp) return; } =20 + spapr_irq_check(spapr, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + /* Initialize the MSI IRQ allocator. */ if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { spapr_irq_msi_init(spapr, spapr->irq->nr_msis); --=20 2.20.1