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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id w3sm1382127lji.59.2019.03.23.14.41.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Mar 2019 14:41:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KzOwyRtlhOKTMNSgGwqHzwDMnwqXpPYvFQdOwoJSSOY=; b=PhiSY4TRvSrNsUJnZLA87xJOWOZT5TaQshUPbbrgXJZOQXgvpQq8WWu/ApTPyt+mck 5nHjWBYVTM6giw+WPmYMg8XeG02Iw9gVh28PiWP9+55crEB2PnP3pLw2B4IUWqG8ZgrO EVwU9eHzbauj4z3QZe17WPCJmKDju2LgGDBfCEYrdb5xJaUar04MRVYoH6MJwdjUh/C8 ZI53zAObmYluwZk1WzudSVHa/i6MeRu2jpI021DpTAU3OCt9ultNfWqATK7VfSvJRpDu 1p9gNZECCZgD65QlLNENvWlcT5bNXSAUiB9gIwGNvjqRnXnbrSO7oeA4yVywOrbSavYW QjGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KzOwyRtlhOKTMNSgGwqHzwDMnwqXpPYvFQdOwoJSSOY=; b=a3lf4IRYj9ruQiGpT0Drw9u4PK06b0jq5Jb69HDbw/IjJtOloC725eOfxZfKjAI3EJ Kb3hWMSUj36ofehgCmBz89LE19mLoZJQDOo2vE4I1h5exEBnnETnOlQ74w7PCxodErFh cziSTSo4K3Jyyab3n+G6k8A4TVaTy1GIgVec3GEjfECYNlMqP5AsM4zfL80G1pT66yw9 tYEoEp5fwpCF2y9eBgylYXa/fkctFFu8h8cl+AinveGI11QNkZ5B0cHr+p5RH2+2RnyN AnMi1+kbvWdZkjxNTeFfyf5I0RDQrX2NsG7FhPj74GNO7BJqo28m3VO0AAsJsKtklCt3 4cuw== X-Gm-Message-State: APjAAAUrhzQHvzNwTYueJ3byQ0FaPjylX1BrMNiFp/ToOqn6IONA4Llx qjQWI8xb6QOPmVr3FmN84T2CV82TuU8= X-Google-Smtp-Source: APXvYqy2dE8suNV+PuaFo1ENL5CayiHIaeA28NblVw3K0VwUtvLIaQwCUr9R4jpnY7JZxkqoLhIuow== X-Received: by 2002:a2e:91cb:: with SMTP id u11mr3612066ljg.64.1553377265146; Sat, 23 Mar 2019 14:41:05 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Sat, 23 Mar 2019 14:40:42 -0700 Message-Id: <20190323214043.28997-5-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190323214043.28997-1-jcmvbkbc@gmail.com> References: <20190323214043.28997-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::242 Subject: [Qemu-devel] [PATCH for-4.1 4/5] target/xtensa: add parity/ECC option SRs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add SRs and rsr/wsr/xsr opcodes defined by the parity/ECC xtensa option. The implementation is trivial since we don't emulate parity/ECC yet. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 6 ++ target/xtensa/overlay_tool.h | 2 + target/xtensa/translate.c | 162 +++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 170 insertions(+) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index e43dfb8447e4..549f34e43092 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -144,6 +144,12 @@ enum { CACHEATTR =3D 98, ATOMCTL =3D 99, DDR =3D 104, + MEPC =3D 106, + MEPS =3D 107, + MESAVE =3D 108, + MESR =3D 109, + MECR =3D 110, + MEVADDR =3D 111, IBREAKA =3D 128, DBREAKA =3D 144, DBREAKC =3D 160, diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index 8b380ce5e329..ffaab4b094cc 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -112,6 +112,8 @@ XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \ XTENSA_OPTION_DCACHE_INDEX_LOCK) | \ XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \ + XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \ + XTENSA_OPTION_MEMORY_ECC_PARITY) | \ /* Memory protection and translation */ \ XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \ XTENSA_OPTION_REGION_PROTECTION) | \ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index c50f6f8d02ec..40c8934f9cc1 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -4216,6 +4216,60 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "rsr.mecr", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MECR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rsr.mepc", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPC, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rsr.meps", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPS, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rsr.mesave", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESAVE, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rsr.mesr", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rsr.mevaddr", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "rsr.misc0", .translate =3D translate_rsr, .test_ill =3D test_ill_sr, @@ -5036,6 +5090,60 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "wsr.mecr", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MECR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "wsr.mepc", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPC, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "wsr.meps", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPS, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "wsr.mesave", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESAVE, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "wsr.mesr", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "wsr.mevaddr", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "wsr.misc0", .translate =3D translate_wsr, .test_ill =3D test_ill_sr, @@ -5702,6 +5810,60 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "xsr.mecr", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MECR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "xsr.mepc", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPC, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "xsr.meps", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPS, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "xsr.mesave", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESAVE, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "xsr.mesr", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "xsr.mevaddr", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "xsr.misc0", .translate =3D translate_xsr, .test_ill =3D test_ill_sr, --=20 2.11.0