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[174.21.5.201]) by smtp.gmail.com with ESMTPSA id h184sm25990703pfc.78.2019.03.23.12.09.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Mar 2019 12:09:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=6XaxbF1WwD9rkCaDt8xX3o20scnBoBxq7g1Q660W3DQ=; b=oDLPpqFLMMJhLNORT27P5tqOHBGE5uOP0vzN1y3uphaycK3zF1YA8T+Ucv30Rxvpoy M1SUs8eKxo7yo/RoBLAZSh/60FGEHYw7Or24rPoa9nv7MlHw2GjOYy4NhZ7rXvvOp7h3 gQJ7K0U5dItMwGdpVasuc/6on8+wyiAoMILPlPu8b0uOS4c6vzkJVz1ECcHb31KzRIzS MxMp9/To5XRBU4x6dhNexrX0Qgh9epSXud5JSGUFWmpX/ZctptL1/GJ1CcrOQqv4KxIs e74citga1ZIhwT/uuTM2Mx99RIfX3wgqJ707NOD5TFah2+Hq7I6vcKOFV1Gm9KQtM7py UyIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=6XaxbF1WwD9rkCaDt8xX3o20scnBoBxq7g1Q660W3DQ=; b=GRbVWyWSaQK3XbcGxL0dj48DQyhTFFbWgh/dxhGevcVbS1XXtjK9Da36AzfOnn7Ewi hOcoQnUlqc69MbBJYSW3OeFaClnW81hd5FpU7R7VJrbLNxKpXDfHVMV+qYaRayp3Bz9K 0Jl6PwT4vNz244TsWZGCDzXtatyU+pGaJdUppnPYJmTJVtiFrBRk931a5MafuteiEpZo CbF9FBOGqp5dltejZaO3UB4J/kVtoCRFu509xOcV8hQ8CsTkY4Lo1isQgGC5NWwEov45 dlWtj2BsZ37hbBkfq2Duv35KwWcFOL5wxFn5cyWrY9iqRTcXCJHCUCG0iwJ+zZuTdh3r lzBg== X-Gm-Message-State: APjAAAXBGvmWdU8uMCN5Ut4LI7by75t9R4dxpj7F6ldp6iU2HL5LSyl2 wfnDgUDw3d8EnwPt4yGOzVXEJ10rOkc= X-Google-Smtp-Source: APXvYqyx2RH9nHKyKVzbCkt7vIquiRDcfcjSL0/ocxVRYJa2awuIsdqH0XUev6UFvmO3+nb7npGPsg== X-Received: by 2002:a65:6119:: with SMTP id z25mr15183445pgu.402.1553368175361; Sat, 23 Mar 2019 12:09:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 23 Mar 2019 12:08:55 -0700 Message-Id: <20190323190925.21324-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190323190925.21324-1-richard.henderson@linaro.org> References: <20190323190925.21324-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PATCH 05/35] cpu: Define ArchCPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For all targets, do this just before including exec/cpu-all.h. Signed-off-by: Richard Henderson Acked-by: Alistair Francis --- target/alpha/cpu.h | 1 + target/arm/cpu.h | 1 + target/cris/cpu.h | 1 + target/hppa/cpu.h | 1 + target/i386/cpu.h | 1 + target/lm32/cpu.h | 1 + target/m68k/cpu.h | 1 + target/microblaze/cpu.h | 1 + target/mips/cpu.h | 1 + target/moxie/cpu.h | 1 + target/nios2/cpu.h | 1 + target/openrisc/cpu.h | 1 + target/ppc/cpu.h | 1 + target/riscv/cpu.h | 1 + target/s390x/cpu.h | 1 + target/sh4/cpu.h | 1 + target/sparc/cpu.h | 1 + target/tilegx/cpu.h | 1 + target/tricore/cpu.h | 1 + target/unicore32/cpu.h | 1 + target/xtensa/cpu.h | 1 + 21 files changed, 21 insertions(+) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index fac622aa02..6629b869d2 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -301,6 +301,7 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, #define cpu_signal_handler cpu_alpha_signal_handler =20 typedef CPUAlphaState CPUArchState; +typedef AlphaCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 89fb92a032..5a8a3f7f7d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3055,6 +3055,7 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMS= tate *env) } =20 typedef CPUARMState CPUArchState; +typedef ARMCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 95662c36b2..bcd17bf88b 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -285,6 +285,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int size, int rw, #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 =20 typedef CPUCRISState CPUArchState; +typedef CRISCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7c1d1e0a0e..f90b11dd0b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -231,6 +231,7 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *e= nv) #define ENV_OFFSET offsetof(HPPACPU, env) =20 typedef CPUHPPAState CPUArchState; +typedef HPPACPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 84ca69ea1a..bb1464d451 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1750,6 +1750,7 @@ static inline target_long lshift(target_long x, int n) void tcg_x86_init(void); =20 typedef CPUX86State CPUArchState; +typedef X86CPU ArchCPU; =20 #include "exec/cpu-all.h" #include "svm.h" diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 5b24cfcc1f..5eef4ccfc5 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -257,6 +257,7 @@ int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int size, int rw, int mmu_idx); =20 typedef CPULM32State CPUArchState; +typedef LM32CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 48c051c7d2..5db18909cc 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -536,6 +536,7 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr ad= dr, unsigned size); =20 typedef CPUM68KState CPUArchState; +typedef M68kCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index dddd58e165..d7c1846e49 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -366,6 +366,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr addres= s, int size, int rw, int mmu_idx); =20 typedef CPUMBState CPUArchState; +typedef MicroBlazeCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 608ae23289..8c5a40b5ad 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1091,6 +1091,7 @@ static inline int cpu_mmu_index (CPUMIPSState *env, b= ool ifetch) } =20 typedef CPUMIPSState CPUArchState; +typedef MIPSCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 10ba6aa7be..4bc5e07af9 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -119,6 +119,7 @@ static inline int cpu_mmu_index(CPUMoxieState *env, boo= l ifetch) } =20 typedef CPUMoxieState CPUArchState; +typedef MoxieCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2b4bd25d65..272ab10e67 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -244,6 +244,7 @@ static inline int cpu_interrupts_enabled(CPUNios2State = *env) } =20 typedef CPUNios2State CPUArchState; +typedef Nios2CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 9bd583f13a..20ea1ca973 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -364,6 +364,7 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU =20 typedef CPUOpenRISCState CPUArchState; +typedef OpenRISCCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 18825ebafc..c5ea29a949 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1365,6 +1365,7 @@ void ppc_compat_add_property(Object *obj, const char = *name, #endif /* defined(TARGET_PPC64) */ =20 typedef CPUPPCState CPUArchState; +typedef PowerPCCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index df71872a82..1fdac0c8d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -324,6 +324,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations = *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 typedef CPURISCVState CPUArchState; +typedef RISCVCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 00b9e6d3b8..762184c62d 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -793,6 +793,7 @@ void s390_init_sigp(void); S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); =20 typedef CPUS390XState CPUArchState; +typedef S390CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 788de6e22a..926cf63825 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -281,6 +281,7 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool= ifetch) } =20 typedef CPUSH4State CPUArchState; +typedef SuperHCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 41c39578c2..55c0004887 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -730,6 +730,7 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, = int pil) } =20 typedef CPUSPARCState CPUArchState; +typedef SPARCCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 2fbf14d508..042a7a0c71 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -151,6 +151,7 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState= *env) #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ =20 typedef CPUTLGState CPUArchState; +typedef TileGXCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index c958deedd9..dc4bcea955 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -380,6 +380,7 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, b= ool ifetch) } =20 typedef CPUTriCoreState CPUArchState; +typedef TriCoreCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 68323b9541..968154e6fa 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -153,6 +153,7 @@ static inline int cpu_mmu_index(CPUUniCore32State *env,= bool ifetch) } =20 typedef CPUUniCore32State CPUArchState; +typedef UniCore32CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 40e4f1f568..6f9721bc28 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -788,6 +788,7 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState = *env, target_ulong *pc, } =20 typedef CPUXtensaState CPUArchState; +typedef XtensaCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 --=20 2.17.1