From nobody Tue Feb 10 08:41:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553369586843430.8684993141726; Sat, 23 Mar 2019 12:33:06 -0700 (PDT) Received: from localhost ([127.0.0.1]:47057 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h7mO7-0005oC-OT for importer@patchew.org; Sat, 23 Mar 2019 15:33:03 -0400 Received: from eggs.gnu.org ([209.51.188.92]:50871) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h7mFq-0007kB-AP for qemu-devel@nongnu.org; Sat, 23 Mar 2019 15:24:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h7m2U-0007Va-T9 for qemu-devel@nongnu.org; Sat, 23 Mar 2019 15:10:45 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46363) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h7m2O-0007Bi-OD for qemu-devel@nongnu.org; Sat, 23 Mar 2019 15:10:37 -0400 Received: by mail-pg1-x541.google.com with SMTP id a22so3677297pgg.13 for ; Sat, 23 Mar 2019 12:10:15 -0700 (PDT) Received: from localhost.localdomain (174-21-5-201.tukw.qwest.net. [174.21.5.201]) by smtp.gmail.com with ESMTPSA id h184sm25990703pfc.78.2019.03.23.12.10.12 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Mar 2019 12:10:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=cc1jCXoSiL6PkyCZ2iThZrQshcETmU13coryc0m7C9c=; b=HWkfmcbgBfquJgCyr8r2n6kFxXIoEBxraoTWCSE9VZ0n5np/5iB/RMT5TsDD32H3+A jpcyzEmmDEcvm416ehIpwAMOkjKQzeGaHj8VRbgedx5brDGr1zodeUW7VfWQ+2XafKvq UKHToEDVCxSb9C6iSGbsULNYEGvRLEhIIUkpIYXM1PlCbumC2kjIFJxzk9kZyuSymtNn wgR3w+2ArhIRJsw6tZoNLdBUmdHafl9C5jKZiSZxn0K0j2ucB6CMx0yIKVuMpUXIk3Wi 7W1vCsdg/pUHDqVDayp9t3tXsFagEomG6MM/h8hcvNq2zB/Ya7zUSMI2ro19tTV4OQ0Y BSEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=cc1jCXoSiL6PkyCZ2iThZrQshcETmU13coryc0m7C9c=; b=kDrvLFm0WmOZfhk3xzykjYXT3frjacEna40/KU7FhTJ3WFWT3Xeb5IhSzbEu5x5SMC TFGL0Zj9zaFrWAIhr0j5vuGUhcbZRX1lMbjPXufLH81ZsguuHHVxlEF0dgqfXd5qTmjh b7SpYmMsC6z7KCY7ROJr/MJjy61j6S6l33WQ0XHTwKn9NFseIyvezqULn8bvWk3nDSah xutgMg4491avfAnwGLqqevt3POUNCaviY9WjFkow7hsD9h8MNW2/TnqcPvFjoWUf3gIp 8zWCedPIO0kxFOdn5LliJU1ujPwEwO2AuzvAjcP1Gd+SC3BlQ56otAHVCT6j/Srcpp1z H+EQ== X-Gm-Message-State: APjAAAUhs79oag2TWyz8VF82c/7GavmB0PDT2cpbgGhggoElD5xYa8fo /U+7uvL2URB+vgPnAhA9pQRpcUDhkHA= X-Google-Smtp-Source: APXvYqyJ/dNgKClnQtJVsxy4Qkmk3GO1zcpJlGTBtNrHEkvWsfQCqfR4lnBVXaFf7I6GPaA5R4bXaw== X-Received: by 2002:a63:1003:: with SMTP id f3mr6624628pgl.227.1553368214013; Sat, 23 Mar 2019 12:10:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 23 Mar 2019 12:09:25 -0700 Message-Id: <20190323190925.21324-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190323190925.21324-1-richard.henderson@linaro.org> References: <20190323190925.21324-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 35/35] tcg/arm: Use LDRD to load tlb mask+table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 109 +++++++++++++++++++-------------------- 1 file changed, 52 insertions(+), 57 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 4a8c12e9a4..e2fd42e218 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -278,6 +278,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); #endif break; @@ -1253,75 +1254,69 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_AREG0, table_off); - - /* Extract the tlb index from the address into TMP. */ - tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrl= o, - SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); - /* - * Add the tlb_table pointer, creating the CPUTLBEntry address in R2. - * Load the tlb comparator into R0/R1 and the fast path addend into R2. + * We don't support inline unaligned acceses, but we can easily + * support overalignment checks. */ - if (cmp_off =3D=3D 0) { - if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_T= MP); - } else { - tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_T= MP); - } - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, - TCG_REG_R2, TCG_REG_R2, TCG_REG_TMP, 0); - if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off); - } else { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off); - } - } - if (!use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2, cmp_off + 4); - } - - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, - offsetof(CPUTLBEntry, addend)); - - /* Check alignment. We don't support inline unaligned acceses, - but we can easily support overalignment checks. */ if (a_bits < s_bits) { a_bits =3D s_bits; } =20 - if (use_armv7_instructions) { - tcg_target_ulong mask =3D ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1)= ); - int rot =3D encode_imm(mask); - - if (rot >=3D 0) {=20 - tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo, - rotl(mask, rot) | (rot << 7)); - } else { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - addrlo, TCG_REG_TMP, 0); - } - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP,= 0); + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + if (use_armv6_instructions) { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); } else { - if (a_bits) { - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, - (1 << a_bits) - 1); - } - tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, - 0, TCG_REG_R0, TCG_REG_TMP, - SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R1, TCG_AREG0, table_off); } =20 + /* Extract the tlb index from the address into R0. */ + tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, + SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); + + /* + * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. + * Load the tlb comparator into R2/R3 and the fast path addend into R1. + */ + if (cmp_off =3D=3D 0) { + if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } else { + tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, + TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); + if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } else { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } + } + if (!use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R3, TCG_REG_R1, cmp_off + 4); + } + + /* Shift the non-page bits out. */ + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, addrlo, + SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, + offsetof(CPUTLBEntry, addend)); + + /* Check alignment, check comparators. */ + if (a_bits) { + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, (1 << a_bits) - = 1); + } + tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, 0, + TCG_REG_R2, TCG_REG_R0, SHIFT_IMM_LSL(TARGET_PAGE_BITS= )); + if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0); + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); } =20 - return TCG_REG_R2; + return TCG_REG_R1; } =20 /* Record the context of a call to the out of line helper code for the slow --=20 2.17.1