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[174.21.5.201]) by smtp.gmail.com with ESMTPSA id h184sm25990703pfc.78.2019.03.23.12.10.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Mar 2019 12:10:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=krHezrIYLph3OBRIj+NlmbtjpuhVo5wBivXbEm2UB9A=; b=f7FwGkUfBvXVib1DC7Rh4g5lSBTPSQjN2rbIXcy6rAySQGlO5Wl8L3vP7hBvfcfmJx 7wwWdi/5ECj9RBe+0otVDRJyQ+2qlsu/8NJThmSUOktPonGk5Tf8f7I1jaLG8hWfEzEK cI/wrJWDm0mkAEvkgv5/XXcCWV0iOITyqDKOJVBeM9aWAagTvwWBsI3oV7Chi/n7vNYj hvddLv6XP5NkjAWQMwQwY6QZOfre6oUEDODyZ4MZqHl7aUjpvxEDXxB9NFZA4OIUME4v U3JqICCKJqCKBqoO3RwYFFfpiTnFakunzfTwkUQClwjjqJ8wHE/lUR1Bu14CkhQ3z8JU hYoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=krHezrIYLph3OBRIj+NlmbtjpuhVo5wBivXbEm2UB9A=; b=nPKrd8J9lTb3/3tXCKxgkkbteDNuoAsQ098b1eoNTbMMkHwrNlU+xVufElKffWrsb0 5xN5TZP0UK1k/51JG1Oa9mDnAmw3EQ4TYfWq0UoWXsc1meczM1j377zCajNYwV8XfJDA Cs15ZrjBkyfFzC0YT3L/vZNhOE7Th63bDABYyuVyBf9430HcDoVlP/kGd7juU3Jz3zS5 KMuCfcNYkU41s5SqfHQv/KDgrZnB7umluLcR4U8QlGkD1khhFN4JPSPDBspMqqCmO0/o aMb02gD6HHh/Vb+v47bcKJU/VcSlSpDy88I1EB+y4KJWIpNr/CsD99bp2vfg3qZ1GfHz GshA== X-Gm-Message-State: APjAAAWcEei9F8KdfZuh38QI2X6VWk4CjgDtTyeRh+jq7rZnTgrujdUr Yp8DQUgv5/yAe7OjtNS4gJ8jaGUBgIM= X-Google-Smtp-Source: APXvYqy1PcwPTxgUvfjQlI41hhLxvGXifidm7SK15xVB1y8UWIB73KU0LKprRCkU2iFyOnvwux+3ug== X-Received: by 2002:a17:902:274a:: with SMTP id j10mr16219730plg.277.1553368209855; Sat, 23 Mar 2019 12:10:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 23 Mar 2019 12:09:22 -0700 Message-Id: <20190323190925.21324-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190323190925.21324-1-richard.henderson@linaro.org> References: <20190323190925.21324-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 32/35] cpu: Move the softmmu tlb to CPUNegativeOffsetState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have for some time had code within the tcg backends to handle large positive offsets from env. This move makes sure that need not happen. Indeed, we are able to assert at build time that simple offsets suffice for all hosts. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 22 +++++++++++++------- tcg/aarch64/tcg-target.inc.c | 29 ++++++-------------------- tcg/arm/tcg-target.inc.c | 40 ++++++++---------------------------- tcg/i386/tcg-target.inc.c | 6 ++++-- tcg/mips/tcg-target.inc.c | 39 ++++++++--------------------------- tcg/ppc/tcg-target.inc.c | 30 ++++++++------------------- tcg/riscv/tcg-target.inc.c | 31 +++++++--------------------- tcg/s390/tcg-target.inc.c | 11 +++++----- tcg/sparc/tcg-target.inc.c | 32 +++++++++-------------------- 9 files changed, 74 insertions(+), 166 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 73de706342..2a774bdaba 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -178,13 +178,14 @@ typedef struct CPUTLBDesc { =20 /* * Data elements that are per MMU mode, accessed by the fast path. + * The structure is aligned to aid loading the pair with one insn. */ typedef struct CPUTLBDescFast { /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ uintptr_t mask; /* The array of tlb entries itself. */ CPUTLBEntry *table; -} CPUTLBDescFast; +} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); =20 /* * Data elements that are shared between all MMU modes. @@ -211,28 +212,35 @@ typedef struct CPUTLBCommon { /* * The entire softmmu tlb, for all MMU modes. * The meaning of each of the MMU modes is defined in the target code. + * Since this is placed within CPUNegativeOffsetState, the smallest + * negative offsets are at the end of the struct. */ typedef struct CPUTLB { - CPUTLBDescFast f[NB_MMU_MODES]; - CPUTLBDesc d[NB_MMU_MODES]; CPUTLBCommon c; + CPUTLBDesc d[NB_MMU_MODES]; + CPUTLBDescFast f[NB_MMU_MODES]; } CPUTLB; =20 -/* There are target-specific members named "tlb". This is temporary. */ -#define CPU_COMMON CPUTLB tlb_; -#define env_tlb(ENV) (&(ENV)->tlb_) +#define env_tlb(ENV) (&env_neg(ENV)->tlb) + +/* This will be used by TCG backends to compute offsets. */ +#define TLB_MASK_TABLE_OFS(IDX) \ + ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) =20 #else =20 -#define CPU_COMMON /* Nothing */ +typedef struct CPUTLB { } CPUTLB; =20 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 +#define CPU_COMMON /* Nothing */ + /* * This structure must be placed in ArchCPU immedately * before CPUArchState, as a field named "neg". */ typedef struct CPUNegativeOffsetState { + CPUTLB tlb; icount_decr icount_decr; } CPUNegativeOffsetState; =20 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 5e6af10faf..ac765137ae 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1451,9 +1451,9 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr; } =20 -/* We expect to use a 24-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0xffffff); +/* We expect to use a 7-bit scaled negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); =20 /* Load and compare a TLB entry, emitting the conditional jump to the slow path for the failure case, which will be patched later when finali= zing @@ -1463,8 +1463,9 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg ad= dr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int mask_ofs =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_ofs =3D offsetof(CPUArchState, tlb_.f[mem_index].table); + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); unsigned a_bits =3D get_alignment_bits(opc); unsigned s_bits =3D opc & MO_SIZE; unsigned a_mask =3D (1u << a_bits) - 1; @@ -1473,24 +1474,6 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg a= ddr_reg, TCGMemOp opc, TCGType mask_type; uint64_t compare_mask; =20 - if (table_ofs > 0xfff) { - int table_hi =3D table_ofs & ~0xfff; - int mask_hi =3D mask_ofs & ~0xfff; - - table_base =3D TCG_REG_X1; - if (mask_hi =3D=3D table_hi) { - mask_base =3D table_base; - } else if (mask_hi) { - mask_base =3D TCG_REG_X0; - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, - mask_base, TCG_AREG0, mask_hi); - } - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, - table_base, TCG_AREG0, table_hi); - mask_ofs -=3D mask_hi; - table_ofs -=3D table_hi; - } - mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); =20 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 04c2eebb41..4a8c12e9a4 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1235,9 +1235,9 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg= argreg, =20 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) =20 -/* We expect to use a 20-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0xfffff); +/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); =20 /* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ @@ -1247,39 +1247,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, { int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 - if (table_off > 0xfff) { - int mask_hi =3D mask_off & ~0xfff; - int table_hi =3D table_off & ~0xfff; - int rot; - - table_base =3D TCG_REG_R2; - if (mask_hi =3D=3D table_hi) { - mask_base =3D table_base; - } else if (mask_hi) { - mask_base =3D TCG_REG_TMP; - rot =3D encode_imm(mask_hi); - assert(rot >=3D 0); - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, mask_base, TCG_AREG0, - rotl(mask_hi, rot) | (rot << 7)); - } - rot =3D encode_imm(table_hi); - assert(rot >=3D 0); - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, table_base, TCG_AREG0, - rotl(table_hi, rot) | (rot << 7)); - - mask_off -=3D mask_hi; - table_off -=3D table_hi; - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_AREG0, table_off); =20 /* Extract the tlb index from the address into TMP. */ tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrl= o, diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 1bd33389c9..f63f39822c 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1654,10 +1654,12 @@ static inline void tcg_out_tlb_load(TCGContext *s, = TCGReg addrlo, TCGReg addrhi, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); =20 tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_.f[mem_index].mask)); + TLB_MASK_TABLE_OFS(mem_index) +=20 + offsetof(CPUTLBDescFast, mask)); =20 tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_.f[mem_index].table)); + TLB_MASK_TABLE_OFS(mem_index) +=20 + offsetof(CPUTLBDescFast, table)); =20 /* If the required alignment is at least as large as the access, simply copy the address and mask. For lesser alignments, check that we do= n't diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index b827579317..55d8cdf4c9 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1201,6 +1201,10 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int= i, TCGReg al, TCGReg ah) return i; } =20 +/* We expect to use a 16-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + /* * Perform the tlb comparison operation. * The complete host address is placed in BASE. @@ -1214,42 +1218,17 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg = base, TCGReg addrl, unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); int mem_index =3D get_mmuidx(oi); - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); int add_off =3D offsetof(CPUTLBEntry, addend); int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; target_ulong mask; =20 - if (table_off > 0x7fff) { - int mask_hi =3D mask_off - (int16_t)mask_off; - int table_hi =3D table_off - (int16_t)table_off; - - table_base =3D TCG_TMP1; - if (likely(mask_hi =3D=3D table_hi)) { - mask_base =3D table_base; - tcg_out_opc_imm(s, OPC_LUI, mask_base, TCG_REG_ZERO, mask_hi >= > 16); - tcg_out_opc_reg(s, ALIAS_PADD, mask_base, mask_base, TCG_AREG0= ); - mask_off -=3D mask_hi; - table_off -=3D mask_hi; - } else { - if (mask_hi !=3D 0) { - mask_base =3D TCG_TMP0; - tcg_out_opc_imm(s, OPC_LUI, - mask_base, TCG_REG_ZERO, mask_hi >> 16); - tcg_out_opc_reg(s, ALIAS_PADD, - mask_base, mask_base, TCG_AREG0); - } - table_off -=3D mask_off; - mask_off -=3D mask_hi; - tcg_out_opc_imm(s, ALIAS_PADDI, table_base, mask_base, mask_of= f); - } - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); =20 /* Extract the TLB index from the address into TMP3. */ tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 1f717745c1..7e7343bb7b 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1505,6 +1505,10 @@ static void * const qemu_st_helpers[16] =3D { [MO_BEQ] =3D helper_be_stq_mmu, }; =20 +/* We expect to use a 16-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + /* Perform the TLB load and compare. Places the result of the comparison in CR7, loads the addend of the TLB into R3, and returns the register containing the guest address (zero-extended into R4). Clobbers R0 and = R2. */ @@ -1517,31 +1521,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMe= mOp opc, =3D (is_read ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 - if (table_off > 0x7fff) { - int mask_hi =3D mask_off - (int16_t)mask_off; - int table_hi =3D table_off - (int16_t)table_off; - - table_base =3D TCG_REG_R4; - if (mask_hi =3D=3D table_hi) { - mask_base =3D table_base; - } else if (mask_hi) { - mask_base =3D TCG_REG_R3; - tcg_out32(s, ADDIS | TAI(mask_base, TCG_AREG0, mask_hi >> 16)); - } - tcg_out32(s, ADDIS | TAI(table_base, TCG_AREG0, table_hi >> 16)); - mask_off -=3D mask_hi; - table_off -=3D table_hi; - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index c1f9c784bc..3198e16486 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -961,6 +961,10 @@ static void * const qemu_st_helpers[16] =3D { /* We don't support oversize guests */ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); =20 +/* We expect to use a 12-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) @@ -970,32 +974,11 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg ad= drl, unsigned a_bits =3D get_alignment_bits(opc); tcg_target_long compare_mask; int mem_index =3D get_mmuidx(oi); - int mask_off, table_off; + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; =20 - mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - if (table_off > 0x7ff) { - int mask_hi =3D mask_off - sextreg(mask_off, 0, 12); - int table_hi =3D table_off - sextreg(table_off, 0, 12); - - if (likely(mask_hi =3D=3D table_hi)) { - mask_base =3D table_base =3D TCG_REG_TMP1; - tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi); - tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0); - mask_off -=3D mask_hi; - table_off -=3D mask_hi; - } else { - mask_base =3D TCG_REG_TMP0; - table_base =3D TCG_REG_TMP1; - tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi); - tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0); - table_off -=3D mask_off; - mask_off -=3D mask_hi; - tcg_out_opc_imm(s, OPC_ADDI, table_base, mask_base, mask_off); - } - } - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off); =20 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 3a8794d9bd..6eefef53a1 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1537,9 +1537,9 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= MemOp opc, TCGReg data, #if defined(CONFIG_SOFTMMU) #include "tcg-ldst.inc.c" =20 -/* We're expecting to use a 20-bit signed offset on the tlb memory ops. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0x7ffff); +/* We're expecting to use a 20-bit negative offset on the tlb memory ops. = */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); =20 /* Load and compare a TLB entry, leaving the flags set. Loads the TLB addend into R2. Returns a register with the santitized guest address. = */ @@ -1550,8 +1550,9 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg = addr_reg, TCGMemOp opc, unsigned a_bits =3D get_alignment_bits(opc); unsigned s_mask =3D (1 << s_bits) - 1; unsigned a_mask =3D (1 << a_bits) - 1; - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); int ofs, a_off; uint64_t tlb_mask; =20 diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index be10124e11..fe7524a802 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1061,6 +1061,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int c= ount) } =20 #if defined(CONFIG_SOFTMMU) + +/* We expect to use a 13-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); + /* Perform the TLB load and compare. =20 Inputs: @@ -1077,9 +1082,9 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int co= unt) static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, TCGMemOp opc, int which) { - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg base =3D TCG_AREG0; + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); const TCGReg r0 =3D TCG_REG_O0; const TCGReg r1 =3D TCG_REG_O1; const TCGReg r2 =3D TCG_REG_O2; @@ -1087,26 +1092,9 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg= addr, int mem_index, unsigned a_bits =3D get_alignment_bits(opc); tcg_target_long compare_mask; =20 - if (!check_fit_i32(table_off, 13)) { - int table_hi; - - base =3D r1; - if (table_off <=3D 2 * 0xfff) { - table_hi =3D 0xfff; - tcg_out_arithi(s, base, TCG_AREG0, table_hi, ARITH_ADD); - } else { - table_hi =3D table_off & ~0x3ff; - tcg_out_sethi(s, base, table_hi); - tcg_out_arith(s, base, TCG_AREG0, base, ARITH_ADD); - } - mask_off -=3D table_hi; - table_off -=3D table_hi; - tcg_debug_assert(check_fit_i32(mask_off, 13)); - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, r0, base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, r1, base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, --=20 2.17.1