From nobody Tue Feb 10 02:55:25 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553215093390429.664319973719; Thu, 21 Mar 2019 17:38:13 -0700 (PDT) Received: from localhost ([127.0.0.1]:48781 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h78CG-0002Kw-1r for importer@patchew.org; Thu, 21 Mar 2019 20:38:08 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h7833-0002zS-4C for qemu-devel@nongnu.org; Thu, 21 Mar 2019 20:28:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h77qr-00012w-Pg for qemu-devel@nongnu.org; Thu, 21 Mar 2019 20:16:04 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:44529) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h77qp-0000qe-M4; Thu, 21 Mar 2019 20:16:01 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 44QPMC1LRpz9sS6; Fri, 22 Mar 2019 11:15:50 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1553213751; bh=CFPa322RdutHLK1lgLmzp0YFxRShSw+u48118v/fiyA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q91eYbDKTBKFWv9uTaUAKyXOOY3zIi8hZqeG2riH6kC/11z76XTxNYJLgEEsIFYBu vae3Galjpw01iAhiIUMjsuG2/hrwTCJORZCfOcEMTYrinV13Qr99S8CDFBvEQ9lz6e na0MRUO2jUBu4a/FaDF5DQLPfjvmiS218f2AhDgk= From: David Gibson To: richard.henderson@linaro.org, qemu-devel@nongnu.org, groug@nongnu.org, qemu-ppc@nongnu.org Date: Fri, 22 Mar 2019 11:15:37 +1100 Message-Id: <20190322001544.9794-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190322001544.9794-1-david@gibson.dropbear.id.au> References: <20190322001544.9794-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [RFC for-4.1 18/25] target/ppc: Style fixes for mmu_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, Alex Williamson , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , clg@kaod.org, aik@ozlabs.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/mmu_helper.c | 131 ++++++++++++++++++++++++---------------- 1 file changed, 80 insertions(+), 51 deletions(-) diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 4a6be4d63b..a01a12a4af 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -32,11 +32,11 @@ #include "mmu-book3s-v3.h" #include "mmu-radix64.h" =20 -//#define DEBUG_MMU -//#define DEBUG_BATS -//#define DEBUG_SOFTWARE_TLB -//#define DUMP_PAGE_TABLES -//#define FLUSH_ALL_TLBS +/* #define DEBUG_MMU */ +/* #define DEBUG_BATS */ +/* #define DEBUG_SOFTWARE_TLB */ +/* #define DUMP_PAGE_TABLES */ +/* #define FLUSH_ALL_TLBS */ =20 #ifdef DEBUG_MMU # define LOG_MMU_STATE(cpu) log_cpu_state_mask(CPU_LOG_MMU, (cpu), 0) @@ -151,7 +151,8 @@ static int check_prot(int prot, int rw, int access_type) } =20 static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0, - target_ulong pte1, int h, int rw, i= nt type) + target_ulong pte1, int h, + int rw, int type) { target_ulong ptem, mmask; int access, ret, pteh, ptev, pp; @@ -331,7 +332,8 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, mm= u_ctx_t *ctx, pte_is_valid(tlb->pte0) ? "valid" : "inval", tlb->EPN, eaddr, tlb->pte1, rw ? 'S' : 'L', access_type =3D=3D ACCESS_CODE ? 'I' : '= D'); - switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw, acc= ess_type)) { + switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1, + 0, rw, access_type)) { case -3: /* TLB inconsistency */ return -1; @@ -346,9 +348,11 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, m= mu_ctx_t *ctx, break; case 0: /* access granted */ - /* XXX: we should go on looping to check all TLBs consistency - * but we can speed-up the whole thing as the - * result would be undefined if TLBs are not consistent. + /* + * XXX: we should go on looping to check all TLBs + * consistency but we can speed-up the whole thing as + * the result would be undefined if TLBs are not + * consistent. */ ret =3D 0; best =3D nr; @@ -549,14 +553,17 @@ static inline int get_segment_6xx_tlb(CPUPPCState *en= v, mmu_ctx_t *ctx, qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); /* Direct-store segment : absolutely *BUGGY* for now */ =20 - /* Direct-store implies a 32-bit MMU. + /* + * Direct-store implies a 32-bit MMU. * Check the Segment Register's bus unit ID (BUID). */ sr =3D env->sr[eaddr >> 28]; if ((sr & 0x1FF00000) >> 20 =3D=3D 0x07f) { /* Memory-forced I/O controller interface access */ - /* If T=3D1 and BUID=3Dx'07F', the 601 performs a memory access - * to SR[28-31] LA[4-31], bypassing all protection mechanisms. + /* + * If T=3D1 and BUID=3Dx'07F', the 601 performs a memory + * access to SR[28-31] LA[4-31], bypassing all protection + * mechanisms. */ ctx->raddr =3D ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF); ctx->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -578,8 +585,9 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env,= mmu_ctx_t *ctx, return -4; case ACCESS_CACHE: /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */ - /* Should make the instruction do no-op. - * As it already do no-op, it's quite easy :-) + /* + * Should make the instruction do no-op. As it already do + * no-op, it's quite easy :-) */ ctx->raddr =3D eaddr; return 0; @@ -941,12 +949,14 @@ static uint32_t mmubooke206_esr(int mmu_idx, bool rw) return esr; } =20 -/* Get EPID register given the mmu_idx. If this is regular load, - * construct the EPID access bits from current processor state */ - -/* Get the effective AS and PR bits and the PID. The PID is returned only = if - * EPID load is requested, otherwise the caller must detect the correct EP= ID. - * Return true if valid EPID is returned. */ +/* + * Get EPID register given the mmu_idx. If this is regular load, + * construct the EPID access bits from current processor state + * + * Get the effective AS and PR bits and the PID. The PID is returned + * only if EPID load is requested, otherwise the caller must detect + * the correct EPID. Return true if valid EPID is returned. + */ static bool mmubooke206_get_as(CPUPPCState *env, int mmu_idx, uint32_t *epid_out, bool *as_out, bool *pr_out) @@ -1373,8 +1383,9 @@ static inline int check_physical(CPUPPCState *env, mm= u_ctx_t *ctx, =20 case POWERPC_MMU_SOFT_4xx_Z: if (unlikely(msr_pe !=3D 0)) { - /* 403 family add some particular protections, - * using PBL/PBU registers for accesses with no translation. + /* + * 403 family add some particular protections, using + * PBL/PBU registers for accesses with no translation. */ in_plb =3D /* Check PLB validity */ @@ -1457,7 +1468,8 @@ static int get_physical_address_wtlb( if (real_mode) { ret =3D check_physical(env, ctx, eaddr, rw); } else { - cpu_abort(CPU(cpu), "PowerPC in real mode do not do any transl= ation\n"); + cpu_abort(CPU(cpu), + "PowerPC in real mode do not do any translation\n"); } return -1; default: @@ -1502,9 +1514,10 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr) =20 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) !=3D= 0)) { =20 - /* Some MMUs have separate TLBs for code and data. If we only try = an - * ACCESS_INT, we may not be able to read instructions mapped by c= ode - * TLBs, so we also try a ACCESS_CODE. + /* + * Some MMUs have separate TLBs for code and data. If we only + * try an ACCESS_INT, we may not be able to read instructions + * mapped by code TLBs, so we also try a ACCESS_CODE. */ if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_CODE) !=3D 0)) { @@ -1838,8 +1851,9 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr= , target_ulong value) #if !defined(FLUSH_ALL_TLBS) do_invalidate_BAT(env, env->IBAT[0][nr], mask); #endif - /* When storing valid upper BAT, mask BEPI and BRPN - * and invalidate all TLBs covered by this BAT + /* + * When storing valid upper BAT, mask BEPI and BRPN and + * invalidate all TLBs covered by this BAT */ mask =3D (value << 15) & 0x0FFE0000UL; env->IBAT[0][nr] =3D (value & 0x00001FFFUL) | @@ -1869,8 +1883,9 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr= , target_ulong value) =20 dump_store_bat(env, 'D', 0, nr, value); if (env->DBAT[0][nr] !=3D value) { - /* When storing valid upper BAT, mask BEPI and BRPN - * and invalidate all TLBs covered by this BAT + /* + * When storing valid upper BAT, mask BEPI and BRPN and + * invalidate all TLBs covered by this BAT */ mask =3D (value << 15) & 0x0FFE0000UL; #if !defined(FLUSH_ALL_TLBS) @@ -1917,8 +1932,9 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t= nr, target_ulong value) do_inval =3D 1; #endif } - /* When storing valid upper BAT, mask BEPI and BRPN - * and invalidate all TLBs covered by this BAT + /* + * When storing valid upper BAT, mask BEPI and BRPN and + * invalidate all TLBs covered by this BAT */ env->IBAT[0][nr] =3D (value & 0x00001FFFUL) | (value & ~0x0001FFFFUL & ~mask); @@ -2031,7 +2047,8 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_= ulong addr) #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { /* tlbie invalidate TLBs for all segments */ - /* XXX: given the fact that there are too many segments to invalid= ate, + /* + * XXX: given the fact that there are too many segments to invalid= ate, * and we still don't have a tlb_flush_mask(env, n, mask) in = QEMU, * we just invalidate all TLBs */ @@ -2048,10 +2065,11 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, targe= t_ulong addr) break; case POWERPC_MMU_32B: case POWERPC_MMU_601: - /* Actual CPUs invalidate entire congruence classes based on the - * geometry of their TLBs and some OSes take that into account, - * we just mark the TLB to be flushed later (context synchronizing - * event or sync instruction on 32-bit). + /* + * Actual CPUs invalidate entire congruence classes based on + * the geometry of their TLBs and some OSes take that into + * account, we just mark the TLB to be flushed later (context + * synchronizing event or sync instruction on 32-bit). */ env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; break; @@ -2156,8 +2174,10 @@ void helper_store_sr(CPUPPCState *env, target_ulong = srnum, target_ulong value) #endif if (env->sr[srnum] !=3D value) { env->sr[srnum] =3D value; -/* Invalidating 256MB of virtual memory in 4kB pages is way longer than - flusing the whole TLB. */ + /* + * Invalidating 256MB of virtual memory in 4kB pages is way + * longer than flusing the whole TLB. + */ #if !defined(FLUSH_ALL_TLBS) && 0 { target_ulong page, end; @@ -2268,10 +2288,12 @@ target_ulong helper_rac(CPUPPCState *env, target_ul= ong addr) int nb_BATs; target_ulong ret =3D 0; =20 - /* We don't have to generate many instances of this instruction, + /* + * We don't have to generate many instances of this instruction, * as rac is supervisor only. + * + * XXX: FIX THIS: Pretend we have no BAT */ - /* XXX: FIX THIS: Pretend we have no BAT */ nb_BATs =3D env->nb_BATs; env->nb_BATs =3D 0; if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) =3D=3D 0) { @@ -2426,7 +2448,8 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulo= ng entry, } tlb->size =3D booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT) & PPC4XX_TLBHI_SIZE_MASK); - /* We cannot handle TLB size < TARGET_PAGE_SIZE. + /* + * We cannot handle TLB size < TARGET_PAGE_SIZE. * If this ever occurs, we should implement TARGET_PAGE_BITS_VARY */ if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) { @@ -2746,7 +2769,8 @@ void helper_booke206_tlbwe(CPUPPCState *env) } =20 if (tlb->mas1 & MAS1_VALID) { - /* Invalidate the page in QEMU TLB if it was a valid entry. + /* + * Invalidate the page in QEMU TLB if it was a valid entry. * * In "PowerPC e500 Core Family Reference Manual, Rev. 1", * Section "12.4.2 TLB Write Entry (tlbwe) Instruction": @@ -2755,7 +2779,8 @@ void helper_booke206_tlbwe(CPUPPCState *env) * "Note that when an L2 TLB entry is written, it may be displacin= g an * already valid entry in the same L2 TLB location (a victim). If a * valid L1 TLB entry corresponds to the L2 MMU victim entry, that= L1 - * TLB entry is automatically invalidated." */ + * TLB entry is automatically invalidated." + */ flush_page(env, tlb); } =20 @@ -2781,8 +2806,9 @@ void helper_booke206_tlbwe(CPUPPCState *env) mask |=3D MAS2_ACM | MAS2_VLE | MAS2_W | MAS2_I | MAS2_M | MAS2_G | MA= S2_E; =20 if (!msr_cm) { - /* Executing a tlbwe instruction in 32-bit mode will set - * bits 0:31 of the TLB EPN field to zero. + /* + * Executing a tlbwe instruction in 32-bit mode will set bits + * 0:31 of the TLB EPN field to zero. */ mask &=3D 0xffffffff; } @@ -3026,10 +3052,13 @@ void helper_check_tlb_flush_global(CPUPPCState *env) =20 /*************************************************************************= ****/ =20 -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ +/* + * try to fill the TLB and return an exception if error. If retaddr is + * NULL, it means that the function was called in C code (i.e. not + * from generated code or from helper.c) + * + * XXX: fix it to restore all registers + */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { --=20 2.20.1