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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id w68sm5616666pfb.176.2019.03.19.10.21.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Mar 2019 10:21:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JB64GhE0tqhCRxnSjkMcq+mPZMqJHRX7NnKGNtPhbPE=; b=glOmbVskQNnuet+J5J7Cw6fnjPmWnWMC0I8czAee18iy0VKYMGcxi1LsTqBRbBFSes RAiy0laZAJ2RrGfxYboPai6baFjV8yA+iLOCkoM/npV1hTKypNuxFWlxQ348pC4k4kcR tyLWTODqPivkD1HV5lmFtzJtynLrMYODgulC/aNyG0l2LY9tJJU33wqR6nTSa8gXwwza BXy26zIpOUCNsGGGYzUlFGAm5dBl+dUvtI2tXn9HUGf4oduBrsA/jY1eNHd53npDwuNy wUjDnFPChNtUgBy9+8eK2xxBdvjLmIAgCglVRVAAM8UAyT0Htq5ieE9chWZryCUS5vJl tNdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JB64GhE0tqhCRxnSjkMcq+mPZMqJHRX7NnKGNtPhbPE=; b=nFdShD1APY0ZPVoOgjlVbgr5oUPkoKq+cOyIRgYOdPOr8wVNQUCs9tSKaXc6+GVKm7 v1baDeE86ofXgV+Otkm53+xl82fk++MxYZ/HmJjGVgP1cKK3GdBzQ0SR5bPCd7e9xY1n KPNcTZdz72QtLV6xz77Mdd4dnA+v7vJiTWfHZ4HWl8vukDOiFqniaIyYMZJGgsp4EDsF LmG3lKwNTaxZqPh6XeoaQf/Vhoo175i2zQyZ9ZeGajCyBxfuc0osqFcVTnhnKWuEtQ/u 8oZmMQVdBGNATg/cEctafYBpgD9Dv7ES5B34HLxsokUbQ0x9ZOf2dUNTfr6RR44EY6pc QXCQ== X-Gm-Message-State: APjAAAUnQVDezVCSvTZXUyIH1h72i4cnqvyteTEqShn+/Lm3q3IQ/1QX woPNDGptA1Zd1MfkeEIecCGMx1jwtzs= X-Google-Smtp-Source: APXvYqzpXJV8FFbhKd9ToL+KQ+lrW9zkpSRjLs7mNxBJe5/JH4Ubl7eyRjMfeolFDSA7x3/LcC14sw== X-Received: by 2002:a17:902:b609:: with SMTP id b9mr3177272pls.134.1553016107544; Tue, 19 Mar 2019 10:21:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Mar 2019 10:21:22 -0700 Message-Id: <20190319172126.7502-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190319172126.7502-1-richard.henderson@linaro.org> References: <20190319172126.7502-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH for-4.1 v3 13/17] tcg/ppc: Support vector shift by immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For Altivec, this is done via vector shift by vector, and loading the immediate into a register. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 58 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 3f669de7a7..14af24b7e4 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -148,7 +148,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 0 #define TCG_TARGET_HAS_sat_vec 1 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 70a64dd214..465e56a83b 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -517,6 +517,16 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define VCMPGTUH VX4(582) #define VCMPGTUW VX4(646) =20 +#define VSLB VX4(260) +#define VSLH VX4(324) +#define VSLW VX4(388) +#define VSRB VX4(516) +#define VSRH VX4(580) +#define VSRW VX4(644) +#define VSRAB VX4(772) +#define VSRAH VX4(836) +#define VSRAW VX4(900) + #define VAND VX4(1028) #define VANDC VX4(1092) #define VNOR VX4(1284) @@ -2871,8 +2881,14 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return vece <=3D MO_32; case INDEX_op_cmp_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: return vece <=3D MO_32 ? -1 : 0; default: return 0; @@ -2980,7 +2996,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, umin_op[4] =3D { VMINUB, VMINUH, VMINUW, 0 }, smin_op[4] =3D { VMINSB, VMINSH, VMINSW, 0 }, umax_op[4] =3D { VMAXUB, VMAXUH, VMAXUW, 0 }, - smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }; + smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }, + shlv_op[4] =3D { VSLB, VSLH, VSLW, 0 }, + shrv_op[4] =3D { VSRB, VSRH, VSRW, 0 }, + sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, 0 }; =20 TCGType type =3D vecl + TCG_TYPE_V64; TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; @@ -3027,6 +3046,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_umax_vec: insn =3D umax_op[vece]; break; + case INDEX_op_shlv_vec: + insn =3D shlv_op[vece]; + break; + case INDEX_op_shrv_vec: + insn =3D shrv_op[vece]; + break; + case INDEX_op_sarv_vec: + insn =3D sarv_op[vece]; + break; case INDEX_op_and_vec: insn =3D VAND; break; @@ -3071,6 +3099,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); } =20 +static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGArg imm, TCGOpcode opci) +{ + TCGv_vec t1 =3D tcg_temp_new_vec(type); + + /* Splat w/bytes for xxspltib. */ + tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1)); + vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); +} + static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2, TCGCond cond) { @@ -3122,14 +3162,25 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,= unsigned vece, { va_list va; TCGv_vec v0, v1, v2; + TCGArg a2; =20 va_start(va, a0); v0 =3D temp_tcgv_vec(arg_temp(a0)); v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - v2 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 =3D va_arg(va, TCGArg); =20 switch (opc) { + case INDEX_op_shli_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); + break; + case INDEX_op_shri_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); + break; + case INDEX_op_sari_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); + break; case INDEX_op_cmp_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; default: @@ -3330,6 +3381,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: --=20 2.17.2