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X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PULL] target/riscv: Fix manually parsed 16 bit insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Bastian Koppelmann during the refactor to decodetree we removed the manual decoding that is necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld and c.fsw/c.sd. This reintroduces the manual parsing and the omited implementation. Signed-off-by: Bastian Koppelmann Tested-by: Palmer Dabbelt Reviewed-by: Alistair Francis Tested-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvc.inc.c | 30 ++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index bcdf64d3b705..5819f53f900e 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -44,10 +44,19 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw= _ld *a) { #ifdef TARGET_RISCV32 /* C.FLW ( RV32FC-only ) */ - return false; + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + arg_c_lw tmp; + decode_insn16_extract_cl_w(&tmp, ctx->opcode); + arg_flw arg =3D { .rd =3D tmp.rd, .rs1 =3D tmp.rs1, .imm =3D tmp.uimm = }; + return trans_flw(ctx, &arg); #else /* C.LD ( RV64C/RV128C-only ) */ - return false; + arg_c_fld tmp; + decode_insn16_extract_cl_d(&tmp, ctx->opcode); + arg_ld arg =3D { .rd =3D tmp.rd, .rs1 =3D tmp.rs1, .imm =3D tmp.uimm }; + return trans_ld(ctx, &arg); #endif } =20 @@ -67,10 +76,19 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw= _sd *a) { #ifdef TARGET_RISCV32 /* C.FSW ( RV32FC-only ) */ - return false; + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + arg_c_sw tmp; + decode_insn16_extract_cs_w(&tmp, ctx->opcode); + arg_fsw arg =3D { .rs1 =3D tmp.rs1, .rs2 =3D tmp.rs2, .imm =3D tmp.uim= m }; + return trans_fsw(ctx, &arg); #else /* C.SD ( RV64C/RV128C-only ) */ - return false; + arg_c_fsd tmp; + decode_insn16_extract_cs_d(&tmp, ctx->opcode); + arg_sd arg =3D { .rs1 =3D tmp.rs1, .rs2 =3D tmp.rs2, .imm =3D tmp.uimm= }; + return trans_sd(ctx, &arg); #endif } =20 @@ -88,7 +106,9 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_j= al_addiw *a) { #ifdef TARGET_RISCV32 /* C.JAL */ - arg_jal arg =3D { .rd =3D 1, .imm =3D a->imm }; + arg_c_j tmp; + decode_insn16_extract_cj(&tmp, ctx->opcode); + arg_jal arg =3D { .rd =3D 1, .imm =3D tmp.imm }; return trans_jal(ctx, &arg); #else /* C.ADDIW */ --=20 2.19.2