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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id s3sm2604497wrt.81.2019.03.15.04.39.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 Mar 2019 04:39:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=h9SCJfs8Kqk6ZFQXqt81KlLK+Mcih/UNoLo0rtCxk14=; b=PuEAaPVz29/iW9cnzf8XUKPCvPoSbwEcCiz/g2ia8arTcTHU9g7KvLWk0l/69QiRBS SQGLZx5voI6C046Wn+b5Mf1vfCi1Sn/dxifNrjqA8b2dSpwuGTFcsXHeN4cn6eJljTbD rT9pc5437PhsgiboXvP2i6IqGZmaMCuZUo3kvyA9OgU9ocLictFDbtCwKKeuOlZplphx u08t1Rf0KbAFFOdbS2QAj4yrd9GmpbAlGiZFBzP8pgGhORYGKytUHFDPj+JIUDRMlLWu AVTtfA4fQYZru185uOUymZ38LtLvztdmdSE2n4UZhHwX2MVXYtsyO1GMVMuGInQnsE9I 27yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h9SCJfs8Kqk6ZFQXqt81KlLK+Mcih/UNoLo0rtCxk14=; b=Reii1t8mmmG0OqBiRg64sz2jnjmuM2464LvxzuW2CDQsCsQeHv1R4Sf0Tp6B2I3Wda s8kWpPbNcBpSimbRcgHaCk0QiHCKt83q/eMDl72bf5IlrLDcGRIeeo1wYrfWrDqPjHT/ dJAhOaiL8shhgRm13TOnU2I2Z1QG552CdV49kVueGunaT7qZceYuMv1mupzI5YkgCz41 qg9ZKwsk0zyRVbljSEVezDAqIKUjlpSvEm7SwhjCGSJ8g28DjPbmG7VTPtqSYlbNViEc VAMg2ZAH1QRD9mhN1H/zuS6tnNIcL4W1/Jda5XlICqzBKz7b+xOfv46YrqTAvut+jK3s 5qdA== X-Gm-Message-State: APjAAAV/6fUQ50YLz78CpM4AVN/PSwQrbCKoCOoPA/7/Nx5+FyyaTpQu WMw83XpzQW7qST7Pq+hqfwmzLDgMKaA= X-Google-Smtp-Source: APXvYqwDDJOZi6AuTwQitSsXgMvaM6iRRQLvuYzaNSlGgpwbq+N9y+AALN2bBt7PFRgR7zC3L2gRoQ== X-Received: by 2002:a5d:6288:: with SMTP id k8mr2245085wru.173.1552649950099; Fri, 15 Mar 2019 04:39:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 15 Mar 2019 11:39:02 +0000 Message-Id: <20190315113906.6585-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190315113906.6585-1-peter.maydell@linaro.org> References: <20190315113906.6585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 1/5] hw/intc/bcm2836_control: Implement local timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Zolt=C3=A1n Baldaszti The BCM2836 control logic module includes a simple "local timer" which is a programmable down-counter that can generates an interrupt. Implement this functionality. Signed-off-by: Zolt=C3=A1n Baldaszti [PMM: wrote commit message; wrapped long line; tweaked some comments to match the final version of the code] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/intc/bcm2836_control.h | 9 +++ hw/intc/bcm2836_control.c | 101 +++++++++++++++++++++++++++++- 2 files changed, 108 insertions(+), 2 deletions(-) diff --git a/include/hw/intc/bcm2836_control.h b/include/hw/intc/bcm2836_co= ntrol.h index 613f3c4186f..de061b8929a 100644 --- a/include/hw/intc/bcm2836_control.h +++ b/include/hw/intc/bcm2836_control.h @@ -5,6 +5,9 @@ * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft * Written by Andrew Baumann * + * ARM Local Timer IRQ Copyright (c) 2019. Zolt=C3=A1n Baldaszti + * Added basic IRQ_TIMER interrupt support + * * This code is licensed under the GNU GPLv2 and later. */ =20 @@ -12,6 +15,7 @@ #define BCM2836_CONTROL_H =20 #include "hw/sysbus.h" +#include "qemu/timer.h" =20 /* 4 mailboxes per core, for 16 total */ #define BCM2836_NCORES 4 @@ -39,6 +43,11 @@ typedef struct BCM2836ControlState { bool gpu_irq, gpu_fiq; uint8_t timerirqs[BCM2836_NCORES]; =20 + /* local timer */ + QEMUTimer timer; + uint32_t local_timer_control; + uint8_t route_localtimer; + /* interrupt source registers, post-routing (also input-derived; visib= le) */ uint32_t irqsrc[BCM2836_NCORES]; uint32_t fiqsrc[BCM2836_NCORES]; diff --git a/hw/intc/bcm2836_control.c b/hw/intc/bcm2836_control.c index cfa5bc73659..421469f2ef5 100644 --- a/hw/intc/bcm2836_control.c +++ b/hw/intc/bcm2836_control.c @@ -7,7 +7,9 @@ * This code is licensed under the GNU GPLv2 and later. * * At present, only implements interrupt routing, and mailboxes (i.e., - * not local timer, PMU interrupt, or AXI counters). + * not PMU interrupt, or AXI counters). + * + * ARM Local Timer IRQ Copyright (c) 2019. Zolt=C3=A1n Baldaszti * * Ref: * https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/= QA7_rev3.4.pdf @@ -18,6 +20,9 @@ #include "qemu/log.h" =20 #define REG_GPU_ROUTE 0x0c +#define REG_LOCALTIMERROUTING 0x24 +#define REG_LOCALTIMERCONTROL 0x34 +#define REG_LOCALTIMERACK 0x38 #define REG_TIMERCONTROL 0x40 #define REG_MBOXCONTROL 0x50 #define REG_IRQSRC 0x60 @@ -43,6 +48,13 @@ #define IRQ_TIMER 11 #define IRQ_MAX IRQ_TIMER =20 +#define LOCALTIMER_FREQ 38400000 +#define LOCALTIMER_INTFLAG (1 << 31) +#define LOCALTIMER_RELOAD (1 << 30) +#define LOCALTIMER_INTENABLE (1 << 29) +#define LOCALTIMER_ENABLE (1 << 28) +#define LOCALTIMER_VALUE(x) ((x) & 0xfffffff) + static void deliver_local(BCM2836ControlState *s, uint8_t core, uint8_t ir= q, uint32_t controlreg, uint8_t controlidx) { @@ -78,6 +90,20 @@ static void bcm2836_control_update(BCM2836ControlState *= s) s->fiqsrc[s->route_gpu_fiq] |=3D (uint32_t)1 << IRQ_GPU; } =20 + /* + * handle the control module 'local timer' interrupt for one of the + * cores' IRQ/FIQ; this is distinct from the per-CPU timer + * interrupts handled below. + */ + if ((s->local_timer_control & LOCALTIMER_INTENABLE) && + (s->local_timer_control & LOCALTIMER_INTFLAG)) { + if (s->route_localtimer & 4) { + s->fiqsrc[(s->route_localtimer & 3)] |=3D (uint32_t)1 << IRQ_T= IMER; + } else { + s->irqsrc[(s->route_localtimer & 3)] |=3D (uint32_t)1 << IRQ_T= IMER; + } + } + for (i =3D 0; i < BCM2836_NCORES; i++) { /* handle local timer interrupts for this core */ if (s->timerirqs[i]) { @@ -162,6 +188,54 @@ static void bcm2836_control_set_gpu_fiq(void *opaque, = int irq, int level) bcm2836_control_update(s); } =20 +static void bcm2836_control_local_timer_set_next(void *opaque) +{ + BCM2836ControlState *s =3D opaque; + uint64_t next_event; + + assert(LOCALTIMER_VALUE(s->local_timer_control) > 0); + + next_event =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + muldiv64(LOCALTIMER_VALUE(s->local_timer_control), + NANOSECONDS_PER_SECOND, LOCALTIMER_FREQ); + timer_mod(&s->timer, next_event); +} + +static void bcm2836_control_local_timer_tick(void *opaque) +{ + BCM2836ControlState *s =3D opaque; + + bcm2836_control_local_timer_set_next(s); + + s->local_timer_control |=3D LOCALTIMER_INTFLAG; + bcm2836_control_update(s); +} + +static void bcm2836_control_local_timer_control(void *opaque, uint32_t val) +{ + BCM2836ControlState *s =3D opaque; + + s->local_timer_control =3D val; + if (val & LOCALTIMER_ENABLE) { + bcm2836_control_local_timer_set_next(s); + } else { + timer_del(&s->timer); + } +} + +static void bcm2836_control_local_timer_ack(void *opaque, uint32_t val) +{ + BCM2836ControlState *s =3D opaque; + + if (val & LOCALTIMER_INTFLAG) { + s->local_timer_control &=3D ~LOCALTIMER_INTFLAG; + } + if ((val & LOCALTIMER_RELOAD) && + (s->local_timer_control & LOCALTIMER_ENABLE)) { + bcm2836_control_local_timer_set_next(s); + } +} + static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned= size) { BCM2836ControlState *s =3D opaque; @@ -170,6 +244,12 @@ static uint64_t bcm2836_control_read(void *opaque, hwa= ddr offset, unsigned size) assert(s->route_gpu_fiq < BCM2836_NCORES && s->route_gpu_irq < BCM2836_NCORES); return ((uint32_t)s->route_gpu_fiq << 2) | s->route_gpu_irq; + } else if (offset =3D=3D REG_LOCALTIMERROUTING) { + return s->route_localtimer; + } else if (offset =3D=3D REG_LOCALTIMERCONTROL) { + return s->local_timer_control; + } else if (offset =3D=3D REG_LOCALTIMERACK) { + return 0; } else if (offset >=3D REG_TIMERCONTROL && offset < REG_MBOXCONTROL) { return s->timercontrol[(offset - REG_TIMERCONTROL) >> 2]; } else if (offset >=3D REG_MBOXCONTROL && offset < REG_IRQSRC) { @@ -195,6 +275,12 @@ static void bcm2836_control_write(void *opaque, hwaddr= offset, if (offset =3D=3D REG_GPU_ROUTE) { s->route_gpu_irq =3D val & 0x3; s->route_gpu_fiq =3D (val >> 2) & 0x3; + } else if (offset =3D=3D REG_LOCALTIMERROUTING) { + s->route_localtimer =3D val & 7; + } else if (offset =3D=3D REG_LOCALTIMERCONTROL) { + bcm2836_control_local_timer_control(s, val); + } else if (offset =3D=3D REG_LOCALTIMERACK) { + bcm2836_control_local_timer_ack(s, val); } else if (offset >=3D REG_TIMERCONTROL && offset < REG_MBOXCONTROL) { s->timercontrol[(offset - REG_TIMERCONTROL) >> 2] =3D val & 0xff; } else if (offset >=3D REG_MBOXCONTROL && offset < REG_IRQSRC) { @@ -227,6 +313,10 @@ static void bcm2836_control_reset(DeviceState *d) =20 s->route_gpu_irq =3D s->route_gpu_fiq =3D 0; =20 + timer_del(&s->timer); + s->route_localtimer =3D 0; + s->local_timer_control =3D 0; + for (i =3D 0; i < BCM2836_NCORES; i++) { s->timercontrol[i] =3D 0; s->mailboxcontrol[i] =3D 0; @@ -263,11 +353,15 @@ static void bcm2836_control_init(Object *obj) /* outputs to CPU cores */ qdev_init_gpio_out_named(dev, s->irq, "irq", BCM2836_NCORES); qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES); + + /* create a qemu virtual timer */ + timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL, + bcm2836_control_local_timer_tick, s); } =20 static const VMStateDescription vmstate_bcm2836_control =3D { .name =3D TYPE_BCM2836_CONTROL, - .version_id =3D 1, + .version_id =3D 2, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(mailboxes, BCM2836ControlState, @@ -277,6 +371,9 @@ static const VMStateDescription vmstate_bcm2836_control= =3D { VMSTATE_UINT32_ARRAY(timercontrol, BCM2836ControlState, BCM2836_NC= ORES), VMSTATE_UINT32_ARRAY(mailboxcontrol, BCM2836ControlState, BCM2836_NCORES), + VMSTATE_TIMER_V(timer, BCM2836ControlState, 2), + VMSTATE_UINT32_V(local_timer_control, BCM2836ControlState, 2), + VMSTATE_UINT8_V(route_localtimer, BCM2836ControlState, 2), VMSTATE_END_OF_LIST() } }; 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X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PULL 2/5] hw/arm/virt-acpi-build: Fix SMMUv3 GSIV values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Eric Auger The GSIV numbers of the SPI based interrupts is not correct as ARM_SPI_BASE was not added to the irqmap[VIRT_SMMU] value. So this may collide with VIRTIO_MMIO irq window. Signed-off-by: Eric Auger Message-id: 20190312091031.5185-1-eric.auger@redhat.com Reviewed-by: Shannon Zhao Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index d7e2e4885b8..aa02d8d74ec 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -405,7 +405,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) its->identifiers[0] =3D 0; /* MADT translation_id */ =20 if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - int irq =3D vms->irqmap[VIRT_SMMU]; + int irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; =20 /* SMMUv3 node */ smmu_offset =3D iort_node_offset + node_size; --=20 2.20.1 From nobody Thu May 9 00:50:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552660446756565.0019702277673; Fri, 15 Mar 2019 07:34:06 -0700 (PDT) Received: from localhost ([127.0.0.1]:56269 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h4nuK-0001wg-Gj for importer@patchew.org; Fri, 15 Mar 2019 10:34:00 -0400 Received: from eggs.gnu.org ([209.51.188.92]:60219) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h4n3G-0007Nw-05 for qemu-devel@nongnu.org; Fri, 15 Mar 2019 09:39:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h4mxl-0007N7-5w for qemu-devel@nongnu.org; Fri, 15 Mar 2019 09:33:31 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:38376) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h4mxi-0007LH-4u for qemu-devel@nongnu.org; Fri, 15 Mar 2019 09:33:27 -0400 Received: by mail-wr1-x441.google.com with SMTP id g12so9608547wrm.5 for ; Fri, 15 Mar 2019 06:33:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id s3sm2604497wrt.81.2019.03.15.04.39.11 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 Mar 2019 04:39:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5SmZWiOdmBkMY8kCDOw7qAGP73bVmcHdlxxKJFh2r+g=; b=vReN1/4jHT1RVQPCjjgCxETiOPlbsLpKZrm6WzuR3TLmgbEC6/H8kGnRR+tz48+Gzp oJunkIMGhu+EOpIfsbCaNynH3eWo7gTAob4PZxJqYb0puRrcNI35IBi0UFu180ZxNw6V eQNDTAV2v78uEuj8rRKBh6BDlTsy+jJoS+Ec+X/MGIGD/S6bXn8GITZdUQAg8FXPOZVo s6rVNMYV9lP2rl97ccPRXzqTRbZR6xH0ji/8nmdBdVBFCohyITBT/ZzeKaabRZJVhuAS jUYbTYCqhTE3P+6Dh0YxI+IGbbQ/NWt3Lpq05zMT75jZMOWQ9IveYxC33fdwp1hyXiP9 /vxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5SmZWiOdmBkMY8kCDOw7qAGP73bVmcHdlxxKJFh2r+g=; b=LHlaYJ0xD8RORzwKPx7zgcRLDthJLWVkbpZMY+Eju0c4837naHlRiBI409lm4vCsFe qOsdioxIUgVK7eF8aatv3rfoug0nY77Eueaq7r2rvQJKKy33c0HaE/gvHKWZDWD0hEBC oh1Vzp8iT3YuMMVy7z3yIGAyVlVnG4021vQb38TsKKjY3LEfixqFhJmVhLKytssaY9bf JOa3tAIG3hY6+yj27jj3aD1myxffUjLfgGSwIJrh2vTEvj+uCqGOeFeRhMP6ZnRX1jQH q3DsC5uihDSTPKYguTZDxfR8s6s6P5CXmFaq2im+l1grkpDAricjrvlbsdLiOAnbKRw+ btGg== X-Gm-Message-State: APjAAAV7t6U8vNXkRiwGUqoTGpNksaqioAXa6uxxvnF9RNc1Q/XhSYbm UMO7M8kGEbQ+Fy8GMqkFF0VzgtIDQr0= X-Google-Smtp-Source: APXvYqyGohQEVzGsXPxeNlRaDmhBteaQcIQHc1ow/4RVlpdqkUw/kgsSyvtnXvx/jofUS4p0+Cbwpw== X-Received: by 2002:adf:ed86:: with SMTP id c6mr2163217wro.146.1552649952881; Fri, 15 Mar 2019 04:39:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 15 Mar 2019 11:39:04 +0000 Message-Id: <20190315113906.6585-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190315113906.6585-1-peter.maydell@linaro.org> References: <20190315113906.6585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 3/5] target/arm: change arch timer registers access permission X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Dongjiu Geng Some generic arch timer registers are Config-RW in the EL0, which means the EL0 exception level can have write permission if it is appropriately configured. When VM access registers, QEMU firstly checks whether they have RW permission, then check whether it is appropriately configured. If they are defined to read only in EL0, even though they have been appropriately configured, they still do not have write permission. So need to add the write permission according to ARMV8 spec when define it. Signed-off-by: Dongjiu Geng Message-id: 1552395177-12608-1-git-send-email-gengdongjiu@huawei.com Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2607d39ad1c..c8d3c213b6b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2665,7 +2665,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { /* per-timer control */ { .name =3D "CNTP_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D= 0, .opc2 =3D 1, .secure =3D ARM_CP_SECSTATE_NS, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), @@ -2674,7 +2674,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { { .name =3D "CNTP_CTL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, .secure =3D ARM_CP_SECSTATE_S, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), @@ -2682,14 +2682,14 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { }, { .name =3D "CNTP_CTL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .type =3D ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), .resetvalue =3D 0, .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 =3D= 0, .opc2 =3D 1, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), @@ -2697,7 +2697,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { }, { .name =3D "CNTV_CTL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), .resetvalue =3D 0, @@ -2706,31 +2706,31 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { /* TimerValue views: a 32 bit downcounting view of the underlying stat= e */ { .name =3D "CNTP_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 = =3D 0, .opc2 =3D 0, .secure =3D ARM_CP_SECSTATE_NS, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, }, { .name =3D "CNTP_TVAL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, .secure =3D ARM_CP_SECSTATE_S, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .readfn =3D gt_sec_tval_read, .writefn =3D gt_sec_tval_write, }, { .name =3D "CNTP_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .resetfn =3D gt_phys_timer_reset, .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, }, { .name =3D "CNTV_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 = =3D 0, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, }, { .name =3D "CNTV_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .resetfn =3D gt_virt_timer_reset, .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, }, @@ -2758,7 +2758,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { /* Comparison value, indicating when the timer goes off */ { .name =3D "CNTP_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, .secure =3D ARM_CP_SECSTATE_NS, - .access =3D PL1_RW | PL0_R, + .access =3D PL0_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .accessfn =3D gt_ptimer_access, @@ -2766,7 +2766,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { }, { .name =3D "CNTP_CVAL_S", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, .secure =3D ARM_CP_SECSTATE_S, - .access =3D PL1_RW | PL0_R, + .access =3D PL0_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), .accessfn =3D gt_ptimer_access, @@ -2774,14 +2774,14 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { }, { .name =3D "CNTP_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .access =3D PL1_RW | PL0_R, + .access =3D PL0_RW, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .resetvalue =3D 0, .accessfn =3D gt_ptimer_access, .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 3, - .access =3D PL1_RW | PL0_R, + .access =3D PL0_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .accessfn =3D gt_vtimer_access, @@ -2789,7 +2789,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { }, { .name =3D "CNTV_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_RW | PL0_R, + .access =3D PL0_RW, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .resetvalue =3D 0, .accessfn =3D gt_vtimer_access, --=20 2.20.1 From nobody Thu May 9 00:50:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552659602922903.775700417599; Fri, 15 Mar 2019 07:20:02 -0700 (PDT) Received: from localhost ([127.0.0.1]:55944 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h4ngk-0006ps-LJ for importer@patchew.org; Fri, 15 Mar 2019 10:19:58 -0400 Received: from eggs.gnu.org ([209.51.188.92]:59771) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h4n3m-0006uL-Rb for qemu-devel@nongnu.org; Fri, 15 Mar 2019 09:39:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h4mqM-0002Q6-7P for qemu-devel@nongnu.org; Fri, 15 Mar 2019 09:25:51 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:44133) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h4mqK-0002OJ-DZ for qemu-devel@nongnu.org; Fri, 15 Mar 2019 09:25:50 -0400 Received: by mail-wr1-x432.google.com with SMTP id w2so9548674wrt.11 for ; Fri, 15 Mar 2019 06:25:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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X-Received-From: 2a00:1450:4864:20::432 Subject: [Qemu-devel] [PULL 4/5] hw/arm/virt-acpi-build: use PCIE_MMCFG_BUS to retrieve end_bus_number X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Wei Yang This is more proper to use PCIE_MMCFG_BUS to retrieve end_bus_number. Signed-off-by: Wei Yang Reviewed-by: Eric Auger Reviewed-by: Igor Mammedov Message-id: 20190312074953.16671-1-richardw.yang@linux.intel.com Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index aa02d8d74ec..bf9c0bc2f49 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -560,8 +560,8 @@ build_mcfg(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Only a single allocation so no need to play with segments */ mcfg->allocation[0].pci_segment =3D cpu_to_le16(0); mcfg->allocation[0].start_bus_number =3D 0; - mcfg->allocation[0].end_bus_number =3D (memmap[ecam_id].size - / PCIE_MMCFG_SIZE_MIN) - 1; + mcfg->allocation[0].end_bus_number =3D + PCIE_MMCFG_BUS(memmap[ecam_id].size - 1); =20 build_header(linker, table_data, (void *)(table_data->data + mcfg_star= t), "MCFG", table_data->len - mcfg_start, 1, NULL, NULL); --=20 2.20.1 From nobody Thu May 9 00:50:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552659401856464.129064596287; Fri, 15 Mar 2019 07:16:41 -0700 (PDT) Received: from localhost ([127.0.0.1]:55911 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h4ndW-0004VU-NG for importer@patchew.org; Fri, 15 Mar 2019 10:16:38 -0400 Received: from eggs.gnu.org ([209.51.188.92]:60054) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h4n3K-0007Gr-Lx for qemu-devel@nongnu.org; Fri, 15 Mar 2019 09:39:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h4mx2-00076V-6g for qemu-devel@nongnu.org; Fri, 15 Mar 2019 09:32:45 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:34571) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h4mx1-00075N-Rr for qemu-devel@nongnu.org; Fri, 15 Mar 2019 09:32:44 -0400 Received: by mail-wr1-x441.google.com with SMTP id k1so9108265wre.1 for ; Fri, 15 Mar 2019 06:32:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 5/5] target/arm: Check access permission to ADDVL/ADDPL/RDVL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Amir Charif These instructions do not trap when SVE is disabled in EL0, causing them to be executed with wrong size information. Signed-off-by: Amir Charif Message-id: 1552579248-31025-1-git-send-email-amir.charif@cea.fr Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell [PMM: added 'target/arm' prefix to subject] Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 3a2eb515664..245cd826217 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -943,24 +943,30 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX= _rr *a) =20 static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) { - TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); - TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); - tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s)); + if (sve_access_check(s)) { + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s)); + } return true; } =20 static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { - TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); - TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); - tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s)); + if (sve_access_check(s)) { + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s)); + } return true; } =20 static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { - TCGv_i64 reg =3D cpu_reg(s, a->rd); - tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); + if (sve_access_check(s)) { + TCGv_i64 reg =3D cpu_reg(s, a->rd); + tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); + } return true; } =20 --=20 2.20.1