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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id d26sm690816pfn.86.2019.03.14.20.26.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Mar 2019 20:26:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wUaNiLlnpoO4I9xjlRRq8x+Qys7GOrUiY0x3QzlpWQA=; b=eJF99u6/rZaaOScD53XGXXKCgukmZZ9pb9QlZIslNjMWQegquM6IvFpFosxLl/lS9P cenvq/ikDD3wTm1IWikdr082lBsOyOArY+Q2HmFug056o+3OvzudaLmmbv1CrqCf+oVp 8ZvF45dvX2plSqTVD1a52wWet8b2KMuiIA07cZTIC+Kv3c4ok5RPqqn5XGRaC9g/ZPA4 ak21lgbv9uhOLGjllHVH/7cnJRVQ9/xIYS5Ey2DMoIThQAB/n1b9tsrhhy8/4MWg7aQk 2iyuG3+H0OMZ0fG0dS2FVDWLSzSPNrq/fNgCDG2t1YHKasnmlPwN1G6+/YV1j0SwrHAG P92w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wUaNiLlnpoO4I9xjlRRq8x+Qys7GOrUiY0x3QzlpWQA=; b=N/NQb/JBi6gSDcdlBnBjEocKLohzod/M0Byj71AEKwz3JDFKYmVrgd0sNRluthXPsL 9oyi5t8Znf4c8THf0ULYf8I01nw/Of3GyZmbl+LqqhHjt90yWQ7qJo1IVbKINC5Nvfrl PqtjOAIfhgbci8iyS+i/a8clquDH6NSslNDyg7l9dxsQ3rCnm5NUgyVQglXZIyHoQZb0 aDCet79QKn+larynfUd4Pc6mk86/53GJ/GSWv+5skbPTmQQL/2H8sn0pPAdc8D5Cteds ksbgQcu/4XPmSJG/hntCb4bNNcJUfpFHB4QatiMhaJJ1HL7cRWdND3brzMDasoT8XrbT P5/w== X-Gm-Message-State: APjAAAWwmWU6fnN9HUlblhIl/n2oRxBPr/B6jI3ORAH+rj6ICcRndUKX PTbp67CNCAzND/4Zooh8KlK0FkFbc+0= X-Google-Smtp-Source: APXvYqzGaLE1G2xAnMc8GOcjcv1NYcJIkhOSQt2Ion0Z4oaJQN50XNZ3e2d6hEyxspPyXN+/4UZbJA== X-Received: by 2002:a65:6546:: with SMTP id a6mr1277968pgw.296.1552620419297; Thu, 14 Mar 2019 20:26:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 14 Mar 2019 20:26:27 -0700 Message-Id: <20190315032629.21234-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190315032629.21234-1-richard.henderson@linaro.org> References: <20190315032629.21234-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 21/23] target/arm: Implement ARMv8.5-RNG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-arm@nongnu.org Cc: Peter Maydell Signed-off-by: Richard Henderson --- v3: Log errors with -d unimp, for lack of a better flag. --- target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 1 + target/arm/helper.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ae2381e222..6a078aa1a0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3443,6 +3443,11 @@ static inline bool isar_feature_aa64_condm_5(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >=3D 2; } =20 +static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) !=3D 0; +} + static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 228906f267..835f73cceb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -310,6 +310,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b5d63f894..4a8d2d4481 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -20,6 +20,8 @@ #include "fpu/softfloat.h" #include "qemu/range.h" #include "qapi/qapi-commands-target.h" +#include "qapi/error.h" +#include "qemu/guest-random.h" =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ =20 @@ -5717,6 +5719,45 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) }, REGINFO_SENTINEL }; + +static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + Error *err =3D NULL; + uint64_t ret; + + /* Success sets NZCV =3D 0000. */ + env->NF =3D env->CF =3D env->VF =3D 0, env->ZF =3D 1; + + if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { + /* + * ??? Failed, for unknown reasons in the crypto subsystem. + * The best we can do is log the reason and return the + * timed-out indication to the guest. There is no reason + * we know to expect this failure to be transitory, so the + * guest may well hang retrying the operation. + */ + qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", + ri->name, error_get_pretty(err)); + error_free(err); + + env->ZF =3D 0; /* NZCF =3D 0100 */ + return 0; + } + return ret; +} + +/* We do not support re-seeding, so the two registers operate the same. */ +static const ARMCPRegInfo rndr_reginfo[] =3D { + { .name =3D "RNDR", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 4, .opc2 =3D 0, + .access =3D PL0_R, .readfn =3D rndr_readfn }, + { .name =3D "RNDRRS", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 4, .opc2 =3D 1, + .access =3D PL0_R, .readfn =3D rndr_readfn }, + REGINFO_SENTINEL +}; #endif =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -6661,6 +6702,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } + if (cpu_isar_feature(aa64_rndr, cpu)) { + define_arm_cp_regs(cpu, rndr_reginfo); + } #endif =20 /* --=20 2.17.2