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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id m64sm25593889pfi.149.2019.03.12.23.26.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Mar 2019 23:26:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8ejONeoCzadNPUYlAxbfn+jA7CyP4F1IWrm2q1c5QP0=; b=oN5wkKZqD0fvF9x65sX6QPI+B7vDpOFru4ra3fiMqAAehA+8tZmzEwYnh25dAFFBa3 I5UhXUprlSaRE0hfLpNNm+ycev2GgFsBDWObqbZ40CiaIuefqSVq+1p7PJ+/glVi21D5 tWelcGYPLEeUE2PyuxECJYWQ62XmFMcDs0aaAOgP1GxyrnSBriKZeEQnc12qyuwKXSC7 t9Qyl5SWDFE5HnZ3IB1A7My/giE5DmPHVuS2HD/cstKNajmPfXgsx6WDtl/y8sFQbwOl RWyjzJg4WpTGIvCVa7knqA/rQf75VDtidioRKK5rPBR/Rbx1R4RVVXB06Zv7xYSl48c+ AY0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8ejONeoCzadNPUYlAxbfn+jA7CyP4F1IWrm2q1c5QP0=; b=Ns2pRukoGrLXLhEc9/2yeM9fTfzplvDgBnGFU6Qsxmi7l+ciThI7GcFVnc0V2YG4rf ZHMu9eQTEte8OsLop5Cp/OmDykRp3QzfDS1oQwbJNsyjyVcSsDn8RS7tgy6qOz7zFheK HFlX4zAizeVhEfLSAjqW/LoZarhogZCE1xEjq+K+dfs0CqkaY0NJ0WfzBJEj/mqi61EZ onJtg264WFef4c7DDulMGZnEzE2AM7GhRTGTVLuMitEed4Mh84ztKClJsyAIHeE9nnEJ u8wOylaYow0mIHHr+JEq0VSpUcQJ3j8Lqy0nfXAUA0pX7trWqtX2aaxrkWrOM8pFYlbz ITvA== X-Gm-Message-State: APjAAAXBnwtj//2+PlSIdEVaEry3o6F2c7ZQIXlFTdSo9oR1Dx7mLn8Z CfSYWVyBC8c62KVaRJy1iRkSYBp3voY= X-Google-Smtp-Source: APXvYqyL6LBcACbPU8wwrgAaj5z15+zZuPNU4B6P9bTMQulEknCzj1GCXoFYsDKngpHHzxCaLuqCUg== X-Received: by 2002:aa7:8c13:: with SMTP id c19mr6053062pfd.247.1552458400890; Tue, 12 Mar 2019 23:26:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Mar 2019 23:26:30 -0700 Message-Id: <20190313062630.30568-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190313062630.30568-1-richard.henderson@linaro.org> References: <20190313062630.30568-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH for-4.1 7/7] target/arm: Implement ARMv8.5-RNG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, david@redhat.com, laurent@vivier.eu, armbru@redhat.com, kraxel@redhat.com, pbonzini@redhat.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 1 + target/arm/helper.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5f23c62132..aaa9e02e78 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3441,6 +3441,11 @@ static inline bool isar_feature_aa64_condm_5(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >=3D 2; } =20 +static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) !=3D 0; +} + static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 228906f267..835f73cceb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -310,6 +310,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 2607d39ad1..3fe7dc8719 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -20,6 +20,7 @@ #include "fpu/softfloat.h" #include "qemu/range.h" #include "qapi/qapi-commands-target.h" +#include "qemu/random.h" =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ =20 @@ -5717,6 +5718,34 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, apib_key.hi) }, REGINFO_SENTINEL }; + +static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t ret; + + /* Success sets NZCV =3D 0000. */ + env->NF =3D env->CF =3D env->VF =3D 0, env->ZF =3D 1; + if (likely(qemu_getrandom(&ret, sizeof(ret), true))) { + return ret; + } + + /* Failure sets Z =3D 1 and returns 0. */ + env->ZF =3D 0; + return 0; +} + +/* We do not support re-seeding, so the two registers operate the same. */ +static const ARMCPRegInfo rndr_reginfo[] =3D { + { .name =3D "RNDR", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 4, .opc2 =3D 0, + .access =3D PL0_R, .readfn =3D rndr_readfn }, + { .name =3D "RNDRRS", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 4, .opc2 =3D 1, + .access =3D PL0_R, .readfn =3D rndr_readfn }, + REGINFO_SENTINEL +}; #endif =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -6661,6 +6690,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } + if (cpu_isar_feature(aa64_rndr, cpu)) { + define_arm_cp_regs(cpu, rndr_reginfo); + } #endif =20 /* --=20 2.17.1