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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id u26sm3808705pfh.42.2019.03.12.15.49.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2019 15:49:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=MP9dTGtxIACoxNzrJmiyDyvmhMxgDXj0R3gTdaRZako=; b=lIOEbEMVRvNxd7QHtC5Nw7A4tBmAW0031YEVY9iLh+Cf6WMj/xCftwAMp6+4W25cLE 2t4l8S8a7W6bPvwM0luuWallsV5ctkr4+Byo+5ucRIHayRIT/H46WPrRWOqCBatlzeHC WRdqW0Bt9hf3+XN3Ts2iiXyN72iHuropKk/ny+MX4By3lomKVqZwOVkEbMtIX6CMj6av t+hIDACVaK/vhtGROyHfdZsT9Ssmx6Lrzf6Ppf0k24uwVLFrNESlwT0TtxuUDg+Reb+B LENhElnr9OYhrlsroPBvPmYvMNIOn1dEd6NaxLQkNwkdfBrEQbzC7sbv2L0CHmdn9Jtz fWfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=MP9dTGtxIACoxNzrJmiyDyvmhMxgDXj0R3gTdaRZako=; b=skn+7KAIuiXR39y0yLHyXxcKpTT13fw/p+zoE8tSQ7gWBqbHy74Wt3ERbcIUgM0LBr 8alo0n5UpQ0gJd9sytw151CzumfSjcnhaQJjdd+/83rIJnlA8GFW0dryyBEyJCHtpK7l NURAk14xPagaMtm550+PorNGXavCnoHZ1l/XzA7AwbnVhKi+hM5a+maDy23SA5CnTLhs a3HsRgNI1bkhRnzIb4WSq1Dfm4UW492kXHnESkYsuOPW6AZdww/39nCfMsj3a4Sf+9Kt FggjglBpnsoWSUiCMzN592sPtJN0Hj6LWwW3dd9CEzdpIzJmsgbofGfUWTifLETlnwAC WRHg== X-Gm-Message-State: APjAAAXintnosNuvlFHdZ2Mljq38CTSPGG7TOR21ul2jirEzjI4Ut9Ov Vbp6tGsA2FZQ/dQaqGT35p0N8Wi/Nmg= X-Google-Smtp-Source: APXvYqxEZDIOphpeNWsKcNgw4MSE/bu8QcIpTSOAGqZ/GLgMnto5RAPn71Ygir428biGiMlPfGitgg== X-Received: by 2002:a17:902:5e2:: with SMTP id f89mr36319585plf.170.1552430965873; Tue, 12 Mar 2019 15:49:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Mar 2019 15:49:23 -0700 Message-Id: <20190312224923.25709-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH] target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXIT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: svens@stackframe.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Within a delay slot, we were squishing both DISAS_IAQ_N_STALE and DISAS_IAQ_N_STALE_EXIT to DISAS_IAQ_N_UPDATED. This lost the required exit to the main loop, and could result in interrupts never being delivered. Reported-by: Sven Schnelle Signed-off-by: Richard Henderson Tested-by: Sven Schnelle --- Sven, this should be a better fix for your 11/11. r~ --- target/hppa/translate.c | 42 +++++++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 35c504087f..43b74367ea 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -347,6 +347,7 @@ static int expand_shl11(int val) /* Similarly, but we want to return to the main loop immediately to recognize unmasked interrupts. */ #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2 +#define DISAS_EXIT DISAS_TARGET_3 =20 /* global register indexes */ static TCGv_reg cpu_gr[32]; @@ -4218,19 +4219,31 @@ static void hppa_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) ctx->iaoq_b =3D ctx->iaoq_n; ctx->base.pc_next +=3D 4; =20 - if (ret =3D=3D DISAS_NORETURN || ret =3D=3D DISAS_IAQ_N_UPDATED) { - return; - } - if (ctx->iaoq_f =3D=3D -1) { - tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); - copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + switch (ret) { + case DISAS_NORETURN: + case DISAS_IAQ_N_UPDATED: + break; + + case DISAS_NEXT: + case DISAS_IAQ_N_STALE: + case DISAS_IAQ_N_STALE_EXIT: + if (ctx->iaoq_f =3D=3D -1) { + tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); + copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); #ifndef CONFIG_USER_ONLY - tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); #endif - nullify_save(ctx); - ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; - } else if (ctx->iaoq_b =3D=3D -1) { - tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var); + nullify_save(ctx); + ctx->base.is_jmp =3D (ret =3D=3D DISAS_IAQ_N_STALE_EXIT + ? DISAS_EXIT + : DISAS_IAQ_N_UPDATED); + } else if (ctx->iaoq_b =3D=3D -1) { + tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var); + } + break; + + default: + g_assert_not_reached(); } } =20 @@ -4252,11 +4265,12 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cs) case DISAS_IAQ_N_UPDATED: if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); - } else if (is_jmp =3D=3D DISAS_IAQ_N_STALE_EXIT) { - tcg_gen_exit_tb(NULL, 0); - } else { + } else if (is_jmp !=3D DISAS_IAQ_N_STALE_EXIT) { tcg_gen_lookup_and_goto_ptr(); } + /* FALLTHRU */ + case DISAS_EXIT: + tcg_gen_exit_tb(NULL, 0); break; default: g_assert_not_reached(); --=20 2.17.2