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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PULL 05/11] target/hppa: add TLB trace events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Sven Schnelle Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Sven Schnelle To ease TLB debugging add a few trace events, which are disabled by default so that there's no performance impact. Signed-off-by: Sven Schnelle Message-Id: <20190311191602.25796-5-svens@stackframe.org> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- Makefile.objs | 1 + target/hppa/mem_helper.c | 21 +++++++++++++++++++-- target/hppa/op_helper.c | 2 ++ target/hppa/trace-events | 18 ++++++++++++++++++ 4 files changed, 40 insertions(+), 2 deletions(-) create mode 100644 target/hppa/trace-events diff --git a/Makefile.objs b/Makefile.objs index 31a84b7d41..72debbf5c5 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -182,6 +182,7 @@ trace-events-subdirs +=3D qapi trace-events-subdirs +=3D qom trace-events-subdirs +=3D scsi trace-events-subdirs +=3D target/arm +trace-events-subdirs +=3D target/hppa trace-events-subdirs +=3D target/i386 trace-events-subdirs +=3D target/mips trace-events-subdirs +=3D target/ppc diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 867449084f..d32ae6e7d9 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -22,6 +22,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qom/cpu.h" +#include "trace.h" =20 #ifdef CONFIG_USER_ONLY int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, @@ -43,9 +44,12 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, = vaddr addr) for (i =3D 0; i < ARRAY_SIZE(env->tlb); ++i) { hppa_tlb_entry *ent =3D &env->tlb[i]; if (ent->va_b <=3D addr && addr <=3D ent->va_e) { + trace_hppa_tlb_find_entry(env, ent + i, ent->entry_valid, + ent->va_b, ent->va_e, ent->pa); return ent; } } + trace_hppa_tlb_find_entry_not_found(env, addr); return NULL; } =20 @@ -55,6 +59,8 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tl= b_entry *ent) unsigned i, n =3D 1 << (2 * ent->page_size); uint64_t addr =3D ent->va_b; =20 + trace_hppa_tlb_flush_ent(env, ent, ent->va_b, ent->va_e, ent->pa); + for (i =3D 0; i < n; ++i, addr +=3D TARGET_PAGE_SIZE) { /* Do not flush MMU_PHYS_IDX. */ tlb_flush_page_by_mmuidx(cs, addr, 0xf); @@ -169,6 +175,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr = addr, int mmu_idx, egress: *pphys =3D phys; *pprot =3D prot; + trace_hppa_tlb_get_physical_address(env, ret, prot, addr, phys); return ret; } =20 @@ -198,6 +205,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType type, int mmu_idx, uintptr_t retaddr) { HPPACPU *cpu =3D HPPA_CPU(cs); + CPUHPPAState *env =3D &cpu->env; int prot, excp, a_prot; hwaddr phys; =20 @@ -213,9 +221,10 @@ void tlb_fill(CPUState *cs, target_ulong addr, int siz= e, break; } =20 - excp =3D hppa_get_physical_address(&cpu->env, addr, mmu_idx, + excp =3D hppa_get_physical_address(env, addr, mmu_idx, a_prot, &phys, &prot); if (unlikely(excp >=3D 0)) { + trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx); /* Failure. Raise the indicated exception. */ cs->exception_index =3D excp; if (cpu->env.psw & PSW_Q) { @@ -226,6 +235,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, cpu_loop_exit_restore(cs, retaddr); } =20 + trace_hppa_tlb_fill_success(env, addr & TARGET_PAGE_MASK, + phys & TARGET_PAGE_MASK, size, type, mmu_i= dx); /* Success! Store the translation into the QEMU TLB. */ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); @@ -259,6 +270,7 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr= , target_ureg reg) empty->va_b =3D addr & TARGET_PAGE_MASK; empty->va_e =3D empty->va_b + TARGET_PAGE_SIZE - 1; empty->pa =3D extract32(reg, 5, 20) << TARGET_PAGE_BITS; + trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa); } =20 /* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */ @@ -280,6 +292,8 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr= , target_ureg reg) ent->d =3D extract32(reg, 28, 1); ent->t =3D extract32(reg, 29, 1); ent->entry_valid =3D 1; + trace_hppa_tlb_itlbp(env, ent, ent->access_id, ent->u, ent->ar_pl2, + ent->ar_pl1, ent->ar_type, ent->b, ent->d, ent->t= ); } =20 /* Purge (Insn/Data) TLB. This is explicitly page-based, and is @@ -299,6 +313,7 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) { CPUState *src =3D CPU(hppa_env_get_cpu(env)); CPUState *cpu; + trace_hppa_tlb_ptlb(env); run_on_cpu_data data =3D RUN_ON_CPU_TARGET_PTR(addr); =20 CPU_FOREACH(cpu) { @@ -314,7 +329,7 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) void HELPER(ptlbe)(CPUHPPAState *env) { CPUState *src =3D CPU(hppa_env_get_cpu(env)); - + trace_hppa_tlb_ptlbe(env); memset(env->tlb, 0, sizeof(env->tlb)); tlb_flush_by_mmuidx(src, 0xf); } @@ -335,8 +350,10 @@ target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulon= g addr) if (excp =3D=3D EXCP_DTLB_MISS) { excp =3D EXCP_NA_DTLB_MISS; } + trace_hppa_tlb_lpa_failed(env, addr); hppa_dynamic_excp(env, excp, GETPC()); } + trace_hppa_tlb_lpa_success(env, addr, phys); return phys; } =20 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 268caaaa20..a05681d480 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -25,6 +25,7 @@ #include "sysemu/sysemu.h" #include "qemu/timer.h" #include "fpu/softfloat.h" +#include "trace.h" =20 void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) { @@ -165,6 +166,7 @@ target_ureg HELPER(probe)(CPUHPPAState *env, target_ulo= ng addr, int prot, excp; hwaddr phys; =20 + trace_hppa_tlb_probe(addr, level, want); /* Fail if the requested privilege level is higher than current. */ if (level < (env->iaoq_f & 3)) { return 0; diff --git a/target/hppa/trace-events b/target/hppa/trace-events new file mode 100644 index 0000000000..80dae5bd8b --- /dev/null +++ b/target/hppa/trace-events @@ -0,0 +1,18 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# target/hppa/mem_helper.c +disable hppa_tlb_flush_ent(void *env, void *ent, uint64_t va_b, uint64_t v= a_e, uint64_t pa) "env=3D%p ent=3D%p va_b=3D0x%lx va_e=3D0x%lx pa=3D0x%lx" +disable hppa_tlb_find_entry(void *env, void *ent, int valid, uint64_t va_b= , uint64_t va_e, uint64_t pa) "env=3D%p ent=3D%p valid=3D%d va_b=3D0x%lx va= _e=3D0x%lx pa=3D0x%lx" +disable hppa_tlb_find_entry_not_found(void *env, uint64_t addr) "env=3D%p = addr=3D%08lx" +disable hppa_tlb_get_physical_address(void *env, int ret, int prot, uint64= _t addr, uint64_t phys) "env=3D%p ret=3D%d prot=3D%d addr=3D0x%lx phys=3D0x= %lx" +disable hppa_tlb_fill_excp(void *env, uint64_t addr, int size, int type, i= nt mmu_idx) "env=3D%p addr=3D0x%lx size=3D%d type=3D%d mmu_idx=3D%d" +disable hppa_tlb_fill_success(void *env, uint64_t addr, uint64_t phys, int= size, int type, int mmu_idx) "env=3D%p addr=3D0x%lx phys=3D0x%lx size=3D%d= type=3D%d mmu_idx=3D%d" +disable hppa_tlb_itlba(void *env, void *ent, uint64_t va_b, uint64_t va_e,= uint64_t pa) "env=3D%p ent=3D%p va_b=3D0x%lx va_e=3D0x%lx pa=3D0x%lx" +disable hppa_tlb_itlbp(void *env, void *ent, int access_id, int u, int pl2= , int pl1, int type, int b, int d, int t) "env=3D%p ent=3D%p access_id=3D%x= u=3D%d pl2=3D%d pl1=3D%d type=3D%d b=3D%d d=3D%d t=3D%d" +disable hppa_tlb_ptlb(void *env) "env=3D%p" +disable hppa_tlb_ptlbe(void *env) "env=3D%p" +disable hppa_tlb_lpa_success(void *env, uint64_t addr, uint64_t phys) "env= =3D%p addr=3D0x%lx phys=3D0x%lx" +disable hppa_tlb_lpa_failed(void *env, uint64_t addr) "env=3D%p addr=3D0x%= lx" + +# target/hppa/op_helper.c +disable hppa_tlb_probe(uint64_t addr, int level, int want) "addr=3D0x%lx l= evel=3D%d want=3D%d" --=20 2.17.2