From nobody Tue Feb 10 04:15:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552382130468624.7327573126528; Tue, 12 Mar 2019 02:15:30 -0700 (PDT) Received: from localhost ([127.0.0.1]:47854 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h3dVO-0001WQ-9G for importer@patchew.org; Tue, 12 Mar 2019 05:15:26 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48005) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h3dCo-0002Ia-0t for qemu-devel@nongnu.org; Tue, 12 Mar 2019 04:56:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h3dCn-00024c-4B for qemu-devel@nongnu.org; Tue, 12 Mar 2019 04:56:13 -0400 Received: from ozlabs.org ([203.11.71.1]:38669) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h3dCm-0001jt-FM; Tue, 12 Mar 2019 04:56:13 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 44JTMP50fsz9sPK; Tue, 12 Mar 2019 19:55:26 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1552380929; bh=IUGzJU2JtjtouJXDXSMctBRln3SEkm4SSXHyeiLM7ro=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oxFImbbj+1P9jQ1e/NzURFUjhBriz5ot2T4paMrcu/2SOn/omuAWi1o/7TVJHP/T1 xMkvTS916VBSVWet9f5merRKc9+Oix441KvyhNnq0pAe8DtoALwYnaZp/jG/Xr42h2 LFl6yK5ZW+GG/JHTo7jh2LgdRQYl4zXG1pWyklV0= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 12 Mar 2019 19:54:21 +1100 Message-Id: <20190312085502.8203-22-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190312085502.8203-1-david@gibson.dropbear.id.au> References: <20190312085502.8203-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 21/62] ppc/xive: hardwire the Physical CAM line of the thread context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: C=C3=A9dric Le Goater By default on P9, the HW CAM line (23bits) is hardwired to : 0x000||0b1||4Bit chip number||7Bit Thread number. When the block group mode is enabled at the controller level (PowerNV), the CAM line is changed for CAM compares to : 4Bit chip number||0x001||7Bit Thread number This will require changes in xive_presenter_tctx_match() possibly. This is a lowlevel functionality of the HW controller and it is not strictly needed. Leave it for later. Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20190306085032.15744-2-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/xive.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index daa7badc84..b21759c938 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1112,6 +1112,30 @@ XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPU= State *cs) return xrc->get_tctx(xrtr, cs); } =20 +/* + * By default on P9, the HW CAM line (23bits) is hardwired to : + * + * 0x000||0b1||4Bit chip number||7Bit Thread number. + * + * When the block grouping is enabled, the CAM line is changed to : + * + * 4Bit chip number||0x001||7Bit Thread number. + */ +static uint32_t hw_cam_line(uint8_t chip_id, uint8_t tid) +{ + return 1 << 11 | (chip_id & 0xf) << 7 | (tid & 0x7f); +} + +static bool xive_presenter_tctx_match_hw(XiveTCTX *tctx, + uint8_t nvt_blk, uint32_t nvt_idx) +{ + CPUPPCState *env =3D &POWERPC_CPU(tctx->cs)->env; + uint32_t pir =3D env->spr_cb[SPR_PIR].default_value; + + return hw_cam_line((pir >> 8) & 0xf, pir & 0x7f) =3D=3D + hw_cam_line(nvt_blk, nvt_idx); +} + /* * The thread context register words are in big-endian format. */ @@ -1120,6 +1144,7 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, = uint8_t format, bool cam_ignore, uint32_t logic_serv) { uint32_t cam =3D xive_nvt_cam_line(nvt_blk, nvt_idx); + uint32_t qw3w2 =3D xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); uint32_t qw2w2 =3D xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); uint32_t qw1w2 =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]); uint32_t qw0w2 =3D xive_tctx_word2(&tctx->regs[TM_QW0_USER]); @@ -1142,7 +1167,11 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx,= uint8_t format, =20 /* F=3D0 & i=3D0: Specific NVT notification */ =20 - /* TODO (PowerNV) : PHYS ring */ + /* PHYS ring */ + if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && + xive_presenter_tctx_match_hw(tctx, nvt_blk, nvt_idx)) { + return TM_QW3_HV_PHYS; + } =20 /* HV POOL ring */ if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) && --=20 2.20.1