From nobody Tue Feb 10 17:30:58 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155220773890470.32609419884079; Sun, 10 Mar 2019 00:48:58 -0800 (PST) Received: from localhost ([127.0.0.1]:42013 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h2u8c-0002IJ-9u for importer@patchew.org; Sun, 10 Mar 2019 04:48:54 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42949) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h2toS-0001IJ-T5 for qemu-devel@nongnu.org; Sun, 10 Mar 2019 04:28:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h2toP-0001Va-5y for qemu-devel@nongnu.org; Sun, 10 Mar 2019 04:28:03 -0400 Received: from ozlabs.org ([203.11.71.1]:48687) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h2toN-0001GS-Nr; Sun, 10 Mar 2019 04:28:01 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 44HDqn5qb9z9sP6; Sun, 10 Mar 2019 19:27:16 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1552206437; bh=azXpz97OGWFofTT+IFcm8e+r5aZ2C0NnlrQgWdlJWGY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qUgTPjzL80ZDLVps6KtNQawXnG4fQ/f2sCyH55yCNAJD7eXE5qbBumy8A44QSzasw ykkwhQJghvh3xrHHKiEoc31nr/mHW3a17s3xMHQnA2nUL5I7zjreE0lbkcSf5s+bE8 FpeyqTJGXVD9XSQLYKk5WuRTztQgBHRdabi/C8hE= From: David Gibson To: peter.maydell@linaro.org Date: Sun, 10 Mar 2019 19:26:31 +1100 Message-Id: <20190310082703.1245-29-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190310082703.1245-1-david@gibson.dropbear.id.au> References: <20190310082703.1245-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 28/60] ppc/pnv: introduce a new pic_print_info() operation to the chip model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: C=C3=A9dric Le Goater The POWER9 and POWER8 processors have different interrupt controllers, and reporting their state requires calling different helper routines. However, the interrupt presenters are still handled in the higher level pic_print_info() routine because they are not related to the chip. Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20190306085032.15744-9-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 27 ++++++++++++++++++++++++--- include/hw/ppc/pnv.h | 1 + 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 087541a91a..7660eaa22c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -567,6 +567,20 @@ static ISABus *pnv_isa_create(PnvChip *chip, Error **e= rrp) return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); } =20 +static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) +{ + Pnv8Chip *chip8 =3D PNV8_CHIP(chip); + + ics_pic_print_info(&chip8->psi.ics, mon); +} + +static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) +{ + Pnv9Chip *chip9 =3D PNV9_CHIP(chip); + + pnv_xive_pic_print_info(&chip9->xive, mon); +} + static void pnv_init(MachineState *machine) { PnvMachineState *pnv =3D PNV_MACHINE(machine); @@ -878,6 +892,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *kl= ass, void *data) k->intc_create =3D pnv_chip_power8_intc_create; k->isa_create =3D pnv_chip_power8_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; + k->pic_print_info =3D pnv_chip_power8_pic_print_info; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8E"; =20 @@ -897,6 +912,7 @@ static void pnv_chip_power8_class_init(ObjectClass *kla= ss, void *data) k->intc_create =3D pnv_chip_power8_intc_create; k->isa_create =3D pnv_chip_power8_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; + k->pic_print_info =3D pnv_chip_power8_pic_print_info; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8"; =20 @@ -916,6 +932,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *= klass, void *data) k->intc_create =3D pnv_chip_power8_intc_create; k->isa_create =3D pnv_chip_power8nvl_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; + k->pic_print_info =3D pnv_chip_power8_pic_print_info; k->xscom_base =3D 0x003fc0000000000ull; dc->desc =3D "PowerNV Chip POWER8NVL"; =20 @@ -977,6 +994,7 @@ static void pnv_chip_power9_class_init(ObjectClass *kla= ss, void *data) k->intc_create =3D pnv_chip_power9_intc_create; k->isa_create =3D pnv_chip_power9_isa_create; k->dt_populate =3D pnv_chip_power9_dt_populate; + k->pic_print_info =3D pnv_chip_power9_pic_print_info; k->xscom_base =3D 0x00603fc00000000ull; dc->desc =3D "PowerNV Chip POWER9"; =20 @@ -1164,12 +1182,15 @@ static void pnv_pic_print_info(InterruptStatsProvid= er *obj, CPU_FOREACH(cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); =20 - icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); + if (pnv_chip_is_power9(pnv->chips[0])) { + xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), = mon); + } else { + icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); + } } =20 for (i =3D 0; i < pnv->num_chips; i++) { - Pnv8Chip *chip8 =3D PNV8_CHIP(pnv->chips[i]); - ics_pic_print_info(&chip8->psi.ics, mon); + PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], m= on); } } =20 diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index fa9ec50fd5..eb4bba25b3 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -103,6 +103,7 @@ typedef struct PnvChipClass { void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); ISABus *(*isa_create)(PnvChip *chip, Error **errp); void (*dt_populate)(PnvChip *chip, void *fdt); + void (*pic_print_info)(PnvChip *chip, Monitor *mon); } PnvChipClass; =20 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP --=20 2.20.1