From nobody Sun Nov 9 22:32:40 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998900084561.2356574172674; Thu, 7 Mar 2019 14:48:20 -0800 (PST) Received: from localhost ([127.0.0.1]:60693 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21o9-0000Xo-PA for importer@patchew.org; Thu, 07 Mar 2019 17:48:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21dR-0007eZ-KK for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:37:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h21dQ-0003WB-2K for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:37:05 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:45404 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h21dO-000237-MN for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:37:02 -0500 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x27MJ5rJ172810 for ; Thu, 7 Mar 2019 17:36:04 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0b-001b2d01.pphosted.com with ESMTP id 2r38ya92pg-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 07 Mar 2019 17:36:04 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:35:59 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZwdT36372514 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 7 Mar 2019 22:35:58 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3F205522F0; Thu, 7 Mar 2019 22:35:58 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 25A5E522F1; Thu, 7 Mar 2019 22:35:58 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 95E4B220062; Thu, 7 Mar 2019 23:35:57 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:41 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0016-0000-0000-0000025F4197 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0017-0000-0000-000032B9D1B1 Message-Id: <20190307223548.20516-9-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0b-001b2d01.pphosted.com id x27MJ5rJ172810 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2 08/15] ppc/pnv: add a OCC model class X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" To ease the introduction of the OCC model for POWER9, provide a new class attributes to define XSCOM operations per CPU family and a PSI IRQ number. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- Changes in v2: - new attributes to define XSCOM operations per CPU family and a PSI IRQ number. include/hw/ppc/pnv_occ.h | 15 +++++++++++ hw/ppc/pnv.c | 2 +- hw/ppc/pnv_occ.c | 55 +++++++++++++++++++++++++++------------- 3 files changed, 54 insertions(+), 18 deletions(-) diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h index 82f299dc76ff..dab5a05f8e99 100644 --- a/include/hw/ppc/pnv_occ.h +++ b/include/hw/ppc/pnv_occ.h @@ -23,6 +23,8 @@ =20 #define TYPE_PNV_OCC "pnv-occ" #define PNV_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV_OCC) +#define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8" +#define PNV8_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV8_OCC) =20 typedef struct PnvOCC { DeviceState xd; @@ -35,4 +37,17 @@ typedef struct PnvOCC { MemoryRegion xscom_regs; } PnvOCC; =20 +#define PNV_OCC_CLASS(klass) \ + OBJECT_CLASS_CHECK(PnvOCCClass, (klass), TYPE_PNV_OCC) +#define PNV_OCC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(PnvOCCClass, (obj), TYPE_PNV_OCC) + +typedef struct PnvOCCClass { + DeviceClass parent_class; + + int xscom_size; + const MemoryRegionOps *xscom_ops; + int psi_irq; +} PnvOCCClass; + #endif /* _PPC_PNV_OCC_H */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 918fae057b5c..6ae9ce679505 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -790,7 +790,7 @@ static void pnv_chip_power8_instance_init(Object *obj) OBJECT(&chip8->psi), &error_abort); =20 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), - TYPE_PNV_OCC, &error_abort, NULL); + TYPE_PNV8_OCC, &error_abort, NULL); object_property_add_const_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), &error_abort); } diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 04880f26d612..ea725647c988 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -34,15 +34,17 @@ static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) { bool irq_state; + PnvOCCClass *poc =3D PNV_OCC_GET_CLASS(occ); =20 val &=3D 0xffff000000000000ull; =20 occ->occmisc =3D val; irq_state =3D !!(val >> 63); - pnv_psi_irq_set(occ->psi, PSIHB_IRQ_OCC, irq_state); + pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state); } =20 -static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, unsigned siz= e) +static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr, + unsigned size) { PnvOCC *occ =3D PNV_OCC(opaque); uint32_t offset =3D addr >> 3; @@ -54,13 +56,13 @@ static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr= addr, unsigned size) break; default: qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" - HWADDR_PRIx "\n", addr); + HWADDR_PRIx "\n", addr >> 3); } return val; } =20 -static void pnv_occ_xscom_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { PnvOCC *occ =3D PNV_OCC(opaque); uint32_t offset =3D addr >> 3; @@ -77,13 +79,13 @@ static void pnv_occ_xscom_write(void *opaque, hwaddr ad= dr, break; default: qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" - HWADDR_PRIx "\n", addr); + HWADDR_PRIx "\n", addr >> 3); } } =20 -static const MemoryRegionOps pnv_occ_xscom_ops =3D { - .read =3D pnv_occ_xscom_read, - .write =3D pnv_occ_xscom_write, +static const MemoryRegionOps pnv_occ_power8_xscom_ops =3D { + .read =3D pnv_occ_power8_xscom_read, + .write =3D pnv_occ_power8_xscom_write, .valid.min_access_size =3D 8, .valid.max_access_size =3D 8, .impl.min_access_size =3D 8, @@ -91,27 +93,42 @@ static const MemoryRegionOps pnv_occ_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +static void pnv_occ_power8_class_init(ObjectClass *klass, void *data) +{ + PnvOCCClass *poc =3D PNV_OCC_CLASS(klass); + + poc->xscom_size =3D PNV_XSCOM_OCC_SIZE; + poc->xscom_ops =3D &pnv_occ_power8_xscom_ops; + poc->psi_irq =3D PSIHB_IRQ_OCC; +} + +static const TypeInfo pnv_occ_power8_type_info =3D { + .name =3D TYPE_PNV8_OCC, + .parent =3D TYPE_PNV_OCC, + .instance_size =3D sizeof(PnvOCC), + .class_init =3D pnv_occ_power8_class_init, +}; =20 static void pnv_occ_realize(DeviceState *dev, Error **errp) { PnvOCC *occ =3D PNV_OCC(dev); + PnvOCCClass *poc =3D PNV_OCC_GET_CLASS(occ); Object *obj; - Error *error =3D NULL; + Error *local_err =3D NULL; =20 occ->occmisc =3D 0; =20 - /* get PSI object from chip */ - obj =3D object_property_get_link(OBJECT(dev), "psi", &error); + obj =3D object_property_get_link(OBJECT(dev), "psi", &local_err); if (!obj) { - error_setg(errp, "%s: required link 'psi' not found: %s", - __func__, error_get_pretty(error)); + error_propagate(errp, local_err); + error_prepend(errp, "required link 'psi' not found: "); return; } occ->psi =3D PNV_PSI(obj); =20 /* XScom region for OCC registers */ - pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), &pnv_occ_xscom_op= s, - occ, "xscom-occ", PNV_XSCOM_OCC_SIZE); + pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops, + occ, "xscom-occ", poc->xscom_size); } =20 static void pnv_occ_class_init(ObjectClass *klass, void *data) @@ -119,6 +136,7 @@ static void pnv_occ_class_init(ObjectClass *klass, void= *data) DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D pnv_occ_realize; + dc->desc =3D "PowerNV OCC Controller"; } =20 static const TypeInfo pnv_occ_type_info =3D { @@ -126,11 +144,14 @@ static const TypeInfo pnv_occ_type_info =3D { .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(PnvOCC), .class_init =3D pnv_occ_class_init, + .class_size =3D sizeof(PnvOCCClass), + .abstract =3D true, }; =20 static void pnv_occ_register_types(void) { type_register_static(&pnv_occ_type_info); + type_register_static(&pnv_occ_power8_type_info); } =20 -type_init(pnv_occ_register_types) +type_init(pnv_occ_register_types); --=20 2.20.1