From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998493043493.47446201672847; Thu, 7 Mar 2019 14:41:33 -0800 (PST) Received: from localhost ([127.0.0.1]:60587 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21hg-0002dy-Ud for importer@patchew.org; Thu, 07 Mar 2019 17:41:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:33971) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21cu-000774-OZ for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h21co-0002ey-Vp for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:28 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:37794 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h21cn-0001yD-GY for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:25 -0500 Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x27MIcAA120450 for ; Thu, 7 Mar 2019 17:36:00 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0b-001b2d01.pphosted.com with ESMTP id 2r3a3ae09s-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 07 Mar 2019 17:36:00 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:35:55 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZsk530736508 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 7 Mar 2019 22:35:54 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 72491A42FB; Thu, 7 Mar 2019 22:35:54 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 567BBA42F6; Thu, 7 Mar 2019 22:35:54 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:35:54 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id C9634220227; Thu, 7 Mar 2019 23:35:53 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:34 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0016-0000-0000-0000025F4193 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0017-0000-0000-000032B9D1AE Message-Id: <20190307223548.20516-2-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0b-001b2d01.pphosted.com id x27MIcAA120450 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2 01/15] ppc/pnv: add a PSI bridge class model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" To ease the introduction of the PSI bridge model for POWER9, abstract the POWER chip differences in a PnvPsi class model and introduce a specific Pnv8Psi type for POWER8. POWER8 interface to the interrupt controller is still XICS whereas POWER9 uses the new XIVE model. Signed-off-by: C=C3=A9dric Le Goater --- Changes in v2 : - introduced a Pnv8Psi (XICS) model include/hw/ppc/pnv.h | 2 +- include/hw/ppc/pnv_psi.h | 29 ++++++++++++++- hw/ppc/pnv.c | 6 ++- hw/ppc/pnv_psi.c | 79 ++++++++++++++++++++++++++++------------ 4 files changed, 87 insertions(+), 29 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index eb4bba25b3e9..3b5f9cd53184 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -71,7 +71,7 @@ typedef struct Pnv8Chip { MemoryRegion icp_mmio; =20 PnvLpcController lpc; - PnvPsi psi; + Pnv8Psi psi; PnvOCC occ; } Pnv8Chip; =20 diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index 64ac73512e81..7087cbcb9ad7 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -39,7 +39,6 @@ typedef struct PnvPsi { uint64_t fsp_bar; =20 /* Interrupt generation */ - ICSState ics; qemu_irq *qirqs; =20 /* Registers */ @@ -48,6 +47,32 @@ typedef struct PnvPsi { MemoryRegion xscom_regs; } PnvPsi; =20 +#define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8" +#define PNV8_PSI(obj) \ + OBJECT_CHECK(Pnv8Psi, (obj), TYPE_PNV8_PSI) + +typedef struct Pnv8Psi { + PnvPsi parent; + + ICSState ics; +} Pnv8Psi; + +#define PNV_PSI_CLASS(klass) \ + OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI) +#define PNV_PSI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(PnvPsiClass, (obj), TYPE_PNV_PSI) + +typedef struct PnvPsiClass { + SysBusDeviceClass parent_class; + + int chip_type; + uint32_t xscom_pcba; + uint32_t xscom_size; + uint64_t bar_mask; + + void (*irq_set)(PnvPsi *psi, int, bool state); +} PnvPsiClass; + /* The PSI and FSP interrupts are muxed on the same IRQ number */ typedef enum PnvPsiIrq { PSIHB_IRQ_PSI, /* internal use only */ @@ -61,6 +86,6 @@ typedef enum PnvPsiIrq { =20 #define PSI_NUM_INTERRUPTS 6 =20 -extern void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state); +void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state); =20 #endif /* _PPC_PNV_PSI_H */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 7660eaa22cf9..5bb2332f167a 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -788,7 +788,7 @@ static void pnv_chip_power8_instance_init(Object *obj) Pnv8Chip *chip8 =3D PNV8_CHIP(obj); =20 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), - TYPE_PNV_PSI, &error_abort, NULL); + TYPE_PNV8_PSI, &error_abort, NULL); object_property_add_const_link(OBJECT(&chip8->psi), "xics", OBJECT(qdev_get_machine()), &error_abor= t); =20 @@ -840,6 +840,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, E= rror **errp) PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); PnvChip *chip =3D PNV_CHIP(dev); Pnv8Chip *chip8 =3D PNV8_CHIP(dev); + Pnv8Psi *psi8 =3D &chip8->psi; Error *local_err =3D NULL; =20 pcc->parent_realize(dev, &local_err); @@ -856,7 +857,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, E= rror **errp) error_propagate(errp, local_err); return; } - pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip8->psi.xscom_= regs); + pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, + &PNV_PSI(psi8)->xscom_regs); =20 /* Create LPC controller */ object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index e61861bfd3c6..067f733f1e4a 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -118,10 +118,11 @@ =20 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) { + PnvPsiClass *ppc =3D PNV_PSI_GET_CLASS(psi); MemoryRegion *sysmem =3D get_system_memory(); uint64_t old =3D psi->regs[PSIHB_XSCOM_BAR]; =20 - psi->regs[PSIHB_XSCOM_BAR] =3D bar & (PSIHB_BAR_MASK | PSIHB_BAR_EN); + psi->regs[PSIHB_XSCOM_BAR] =3D bar & (ppc->bar_mask | PSIHB_BAR_EN); =20 /* Update MR, always remove it first */ if (old & PSIHB_BAR_EN) { @@ -130,7 +131,7 @@ static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) =20 /* Then add it back if needed */ if (bar & PSIHB_BAR_EN) { - uint64_t addr =3D bar & PSIHB_BAR_MASK; + uint64_t addr =3D bar & ppc->bar_mask; memory_region_add_subregion(sysmem, addr, &psi->regs_mr); } } @@ -154,7 +155,7 @@ static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr) =20 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val) { - ICSState *ics =3D &psi->ics; + ICSState *ics =3D &PNV8_PSI(psi)->ics; =20 /* In this model we ignore the up/down enable bits for now * as SW doesn't use them (other than setting them at boot). @@ -207,7 +208,12 @@ static const uint64_t stat_bits[] =3D { [PSIHB_IRQ_EXTERNAL] =3D PSIHB_IRQ_STAT_EXT, }; =20 -void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state) +void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state) +{ + PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state); +} + +static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state) { uint32_t xivr_reg; uint32_t stat_reg; @@ -262,7 +268,7 @@ void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool s= tate) =20 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val) { - ICSState *ics =3D &psi->ics; + ICSState *ics =3D &PNV8_PSI(psi)->ics; uint16_t server; uint8_t prio; uint8_t src; @@ -451,11 +457,11 @@ static void pnv_psi_reset(void *dev) psi->regs[PSIHB_XSCOM_BAR] =3D psi->bar | PSIHB_BAR_EN; } =20 -static void pnv_psi_init(Object *obj) +static void pnv_psi_power8_instance_init(Object *obj) { - PnvPsi *psi =3D PNV_PSI(obj); + Pnv8Psi *psi8 =3D PNV8_PSI(obj); =20 - object_initialize_child(obj, "ics-psi", &psi->ics, sizeof(psi->ics), + object_initialize_child(obj, "ics-psi", &psi8->ics, sizeof(psi8->ics), TYPE_ICS_SIMPLE, &error_abort, NULL); } =20 @@ -468,10 +474,10 @@ static const uint8_t irq_to_xivr[] =3D { PSIHB_XSCOM_XIVR_EXT, }; =20 -static void pnv_psi_realize(DeviceState *dev, Error **errp) +static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) { PnvPsi *psi =3D PNV_PSI(dev); - ICSState *ics =3D &psi->ics; + ICSState *ics =3D &PNV8_PSI(psi)->ics; Object *obj; Error *err =3D NULL; unsigned int i; @@ -524,28 +530,28 @@ static void pnv_psi_realize(DeviceState *dev, Error *= *errp) qemu_register_reset(pnv_psi_reset, dev); } =20 +static const char compat_p8[] =3D "ibm,power8-psihb-x\0ibm,psihb-x"; + static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_o= ffset) { - const char compat[] =3D "ibm,power8-psihb-x\0ibm,psihb-x"; + PnvPsiClass *ppc =3D PNV_PSI_GET_CLASS(dev); char *name; int offset; - uint32_t lpc_pcba =3D PNV_XSCOM_PSIHB_BASE; uint32_t reg[] =3D { - cpu_to_be32(lpc_pcba), - cpu_to_be32(PNV_XSCOM_PSIHB_SIZE) + cpu_to_be32(ppc->xscom_pcba), + cpu_to_be32(ppc->xscom_size) }; =20 - name =3D g_strdup_printf("psihb@%x", lpc_pcba); + name =3D g_strdup_printf("psihb@%x", ppc->xscom_pcba); offset =3D fdt_add_subnode(fdt, xscom_offset, name); _FDT(offset); g_free(name); =20 - _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); - - _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); - _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); - _FDT((fdt_setprop(fdt, offset, "compatible", compat, - sizeof(compat)))); + _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); + _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); + _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); + _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8, + sizeof(compat_p8))); return 0; } =20 @@ -555,6 +561,29 @@ static Property pnv_psi_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvPsiClass *ppc =3D PNV_PSI_CLASS(klass); + + dc->desc =3D "PowerNV PSI Controller POWER8"; + dc->realize =3D pnv_psi_power8_realize; + + ppc->chip_type =3D PNV_CHIP_POWER8; + ppc->xscom_pcba =3D PNV_XSCOM_PSIHB_BASE; + ppc->xscom_size =3D PNV_XSCOM_PSIHB_SIZE; + ppc->bar_mask =3D PSIHB_BAR_MASK; + ppc->irq_set =3D pnv_psi_power8_irq_set; +} + +static const TypeInfo pnv_psi_power8_info =3D { + .name =3D TYPE_PNV8_PSI, + .parent =3D TYPE_PNV_PSI, + .instance_size =3D sizeof(Pnv8Psi), + .instance_init =3D pnv_psi_power8_instance_init, + .class_init =3D pnv_psi_power8_class_init, +}; + static void pnv_psi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -562,7 +591,7 @@ static void pnv_psi_class_init(ObjectClass *klass, void= *data) =20 xdc->dt_xscom =3D pnv_psi_dt_xscom; =20 - dc->realize =3D pnv_psi_realize; + dc->desc =3D "PowerNV PSI Controller"; dc->props =3D pnv_psi_properties; } =20 @@ -570,8 +599,9 @@ static const TypeInfo pnv_psi_info =3D { .name =3D TYPE_PNV_PSI, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(PnvPsi), - .instance_init =3D pnv_psi_init, .class_init =3D pnv_psi_class_init, + .class_size =3D sizeof(PnvPsiClass), + .abstract =3D true, .interfaces =3D (InterfaceInfo[]) { { TYPE_PNV_XSCOM_INTERFACE }, { } @@ -581,6 +611,7 @@ static const TypeInfo pnv_psi_info =3D { static void pnv_psi_register_types(void) { type_register_static(&pnv_psi_info); + type_register_static(&pnv_psi_power8_info); } =20 -type_init(pnv_psi_register_types) +type_init(pnv_psi_register_types); --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998467894803.8197752084392; Thu, 7 Mar 2019 14:41:07 -0800 (PST) Received: from localhost ([127.0.0.1]:60576 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21hD-00029m-Iz for importer@patchew.org; Thu, 07 Mar 2019 17:40:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:33730) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21cc-0006sm-TA for qemu-devel@nongnu.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:35:56 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZtEs37159086 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Mar 2019 22:35:55 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 06814A40A5; Thu, 7 Mar 2019 22:35:55 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D44BDA409F; Thu, 7 Mar 2019 22:35:54 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:35:54 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 496EF220062; Thu, 7 Mar 2019 23:35:54 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:35 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0012-0000-0000-000002FFF8DD X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0013-0000-0000-000021370902 Message-Id: <20190307223548.20516-3-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=680 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x27MIalI070981 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2 02/15] ppc/pnv: add a PSI bridge model for POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The PSI bridge on POWER9 is very similar to POWER8. The BAR is still set through XSCOM but the controls are now entirely done with MMIOs. More interrupts are defined and the interrupt controller interface has changed to XIVE. The POWER9 model is a first example of the usage of the notify() handler of the XiveNotifier interface, linking the PSI XiveSource to its owning device model. Signed-off-by: C=C3=A9dric Le Goater --- Changes in v2 : =20 - introduced a Pnv9Psi (XIVE) model =20 include/hw/ppc/pnv.h | 6 + include/hw/ppc/pnv_psi.h | 30 ++++ include/hw/ppc/pnv_xscom.h | 3 + hw/ppc/pnv.c | 18 ++ hw/ppc/pnv_psi.c | 329 ++++++++++++++++++++++++++++++++++++- 5 files changed, 384 insertions(+), 2 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 3b5f9cd53184..8d80cb34eebb 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -84,6 +84,7 @@ typedef struct Pnv9Chip { =20 /*< public >*/ PnvXive xive; + Pnv9Psi psi; } Pnv9Chip; =20 typedef struct PnvChipClass { @@ -231,11 +232,16 @@ void pnv_bmc_powerdown(IPMIBmc *bmc); #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060180000000= 00ull) =20 +#define PNV9_PSIHB_SIZE 0x0000000000100000ull +#define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302030000= 00ull) + #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031000= 00ull) =20 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031800= 00ull) =20 +#define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull +#define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c00= 00ull) =20 #endif /* _PPC_PNV_H */ diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index 7087cbcb9ad7..2c1b27e865bd 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -21,6 +21,7 @@ =20 #include "hw/sysbus.h" #include "hw/ppc/xics.h" +#include "hw/ppc/xive.h" =20 #define TYPE_PNV_PSI "pnv-psi" #define PNV_PSI(obj) \ @@ -57,6 +58,16 @@ typedef struct Pnv8Psi { ICSState ics; } Pnv8Psi; =20 +#define TYPE_PNV9_PSI TYPE_PNV_PSI "-POWER9" +#define PNV9_PSI(obj) \ + OBJECT_CHECK(Pnv9Psi, (obj), TYPE_PNV9_PSI) + +typedef struct Pnv9Psi { + PnvPsi parent; + + XiveSource source; +} Pnv9Psi; + #define PNV_PSI_CLASS(klass) \ OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI) #define PNV_PSI_GET_CLASS(obj) \ @@ -88,4 +99,23 @@ typedef enum PnvPsiIrq { =20 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state); =20 +/* P9 PSI Interrupts */ +#define PSIHB9_IRQ_PSI 0 +#define PSIHB9_IRQ_OCC 1 +#define PSIHB9_IRQ_FSI 2 +#define PSIHB9_IRQ_LPCHC 3 +#define PSIHB9_IRQ_LOCAL_ERR 4 +#define PSIHB9_IRQ_GLOBAL_ERR 5 +#define PSIHB9_IRQ_TPM 6 +#define PSIHB9_IRQ_LPC_SIRQ0 7 +#define PSIHB9_IRQ_LPC_SIRQ1 8 +#define PSIHB9_IRQ_LPC_SIRQ2 9 +#define PSIHB9_IRQ_LPC_SIRQ3 10 +#define PSIHB9_IRQ_SBE_I2C 11 +#define PSIHB9_IRQ_DIO 12 +#define PSIHB9_IRQ_PSU 13 +#define PSIHB9_NUM_IRQS 14 + +void pnv_psi_pic_print_info(Pnv9Psi *psi, Monitor *mon); + #endif /* _PPC_PNV_PSI_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 6623ec54a7a8..403a365ed274 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -73,6 +73,9 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_OCC_BASE 0x0066000 #define PNV_XSCOM_OCC_SIZE 0x6000 =20 +#define PNV9_XSCOM_PSIHB_BASE 0x5012900 +#define PNV9_XSCOM_PSIHB_SIZE 0x100 + #define PNV9_XSCOM_XIVE_BASE 0x5013000 #define PNV9_XSCOM_XIVE_SIZE 0x300 =20 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 5bb2332f167a..1cc454cbbc27 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -579,6 +579,7 @@ static void pnv_chip_power9_pic_print_info(PnvChip *chi= p, Monitor *mon) Pnv9Chip *chip9 =3D PNV9_CHIP(chip); =20 pnv_xive_pic_print_info(&chip9->xive, mon); + pnv_psi_pic_print_info(&chip9->psi, mon); } =20 static void pnv_init(MachineState *machine) @@ -950,6 +951,11 @@ static void pnv_chip_power9_instance_init(Object *obj) TYPE_PNV_XIVE, &error_abort, NULL); object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj, &error_abort); + + object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), + TYPE_PNV9_PSI, &error_abort, NULL); + object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj, + &error_abort); } =20 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) @@ -957,6 +963,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, E= rror **errp) PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); Pnv9Chip *chip9 =3D PNV9_CHIP(dev); PnvChip *chip =3D PNV_CHIP(dev); + Pnv9Psi *psi9 =3D &chip9->psi; Error *local_err =3D NULL; =20 pcc->parent_realize(dev, &local_err); @@ -982,6 +989,17 @@ static void pnv_chip_power9_realize(DeviceState *dev, = Error **errp) } pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, &chip9->xive.xscom_regs); + + /* Processor Service Interface (PSI) Host Bridge */ + object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), + "bar", &error_fatal); + object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local= _err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, + &PNV_PSI(psi9)->xscom_regs); } =20 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 067f733f1e4a..5a923e41518d 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -22,6 +22,7 @@ #include "target/ppc/cpu.h" #include "qemu/log.h" #include "qapi/error.h" +#include "monitor/monitor.h" =20 #include "exec/address-spaces.h" =20 @@ -114,6 +115,9 @@ #define PSIHB_BAR_MASK 0x0003fffffff00000ull #define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull =20 +#define PSIHB9_BAR_MASK 0x00fffffffff00000ull +#define PSIHB9_FSPBAR_MASK 0x00ffffff00000000ull + #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) =20 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) @@ -531,6 +535,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Er= ror **errp) } =20 static const char compat_p8[] =3D "ibm,power8-psihb-x\0ibm,psihb-x"; +static const char compat_p9[] =3D "ibm,power9-psihb-x\0ibm,psihb-x"; =20 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_o= ffset) { @@ -550,8 +555,13 @@ static int pnv_psi_dt_xscom(PnvXScomInterface *dev, vo= id *fdt, int xscom_offset) _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); - _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8, - sizeof(compat_p8))); + if (ppc->chip_type =3D=3D PNV_CHIP_POWER9) { + _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9, + sizeof(compat_p9))); + } else { + _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8, + sizeof(compat_p8))); + } return 0; } =20 @@ -584,6 +594,308 @@ static const TypeInfo pnv_psi_power8_info =3D { .class_init =3D pnv_psi_power8_class_init, }; =20 + +/* Common registers */ + +#define PSIHB9_CR 0x20 +#define PSIHB9_SEMR 0x28 + +/* P9 registers */ + +#define PSIHB9_INTERRUPT_CONTROL 0x58 +#define PSIHB9_IRQ_METHOD PPC_BIT(0) +#define PSIHB9_IRQ_RESET PPC_BIT(1) +#define PSIHB9_ESB_CI_BASE 0x60 +#define PSIHB9_ESB_CI_VALID 1 +#define PSIHB9_ESB_NOTIF_ADDR 0x68 +#define PSIHB9_ESB_NOTIF_VALID 1 +#define PSIHB9_IVT_OFFSET 0x70 +#define PSIHB9_IVT_OFF_SHIFT 32 + +#define PSIHB9_IRQ_LEVEL 0x78 /* assertion */ +#define PSIHB9_IRQ_LEVEL_PSI PPC_BIT(0) +#define PSIHB9_IRQ_LEVEL_OCC PPC_BIT(1) +#define PSIHB9_IRQ_LEVEL_FSI PPC_BIT(2) +#define PSIHB9_IRQ_LEVEL_LPCHC PPC_BIT(3) +#define PSIHB9_IRQ_LEVEL_LOCAL_ERR PPC_BIT(4) +#define PSIHB9_IRQ_LEVEL_GLOBAL_ERR PPC_BIT(5) +#define PSIHB9_IRQ_LEVEL_TPM PPC_BIT(6) +#define PSIHB9_IRQ_LEVEL_LPC_SIRQ1 PPC_BIT(7) +#define PSIHB9_IRQ_LEVEL_LPC_SIRQ2 PPC_BIT(8) +#define PSIHB9_IRQ_LEVEL_LPC_SIRQ3 PPC_BIT(9) +#define PSIHB9_IRQ_LEVEL_LPC_SIRQ4 PPC_BIT(10) +#define PSIHB9_IRQ_LEVEL_SBE_I2C PPC_BIT(11) +#define PSIHB9_IRQ_LEVEL_DIO PPC_BIT(12) +#define PSIHB9_IRQ_LEVEL_PSU PPC_BIT(13) +#define PSIHB9_IRQ_LEVEL_I2C_C PPC_BIT(14) +#define PSIHB9_IRQ_LEVEL_I2C_D PPC_BIT(15) +#define PSIHB9_IRQ_LEVEL_I2C_E PPC_BIT(16) +#define PSIHB9_IRQ_LEVEL_SBE PPC_BIT(19) + +#define PSIHB9_IRQ_STAT 0x80 /* P bit */ +#define PSIHB9_IRQ_STAT_PSI PPC_BIT(0) +#define PSIHB9_IRQ_STAT_OCC PPC_BIT(1) +#define PSIHB9_IRQ_STAT_FSI PPC_BIT(2) +#define PSIHB9_IRQ_STAT_LPCHC PPC_BIT(3) +#define PSIHB9_IRQ_STAT_LOCAL_ERR PPC_BIT(4) +#define PSIHB9_IRQ_STAT_GLOBAL_ERR PPC_BIT(5) +#define PSIHB9_IRQ_STAT_TPM PPC_BIT(6) +#define PSIHB9_IRQ_STAT_LPC_SIRQ1 PPC_BIT(7) +#define PSIHB9_IRQ_STAT_LPC_SIRQ2 PPC_BIT(8) +#define PSIHB9_IRQ_STAT_LPC_SIRQ3 PPC_BIT(9) +#define PSIHB9_IRQ_STAT_LPC_SIRQ4 PPC_BIT(10) +#define PSIHB9_IRQ_STAT_SBE_I2C PPC_BIT(11) +#define PSIHB9_IRQ_STAT_DIO PPC_BIT(12) +#define PSIHB9_IRQ_STAT_PSU PPC_BIT(13) + +static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno) +{ + PnvPsi *psi =3D PNV_PSI(xf); + uint64_t notif_port =3D psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; + bool valid =3D notif_port & PSIHB9_ESB_NOTIF_VALID; + uint64_t notify_addr =3D notif_port & ~PSIHB9_ESB_NOTIF_VALID; + + uint32_t offset =3D + (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); + uint64_t lisn =3D cpu_to_be64(offset + srcno); + + if (valid) { + cpu_physical_memory_write(notify_addr, &lisn, sizeof(lisn)); + } +} + +static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned s= ize) +{ + PnvPsi *psi =3D PNV_PSI(opaque); + uint32_t reg =3D PSIHB_REG(addr); + uint64_t val =3D -1; + + switch (addr) { + case PSIHB9_CR: + case PSIHB9_SEMR: + /* FSP stuff */ + case PSIHB9_INTERRUPT_CONTROL: + case PSIHB9_ESB_CI_BASE: + case PSIHB9_ESB_NOTIF_ADDR: + case PSIHB9_IVT_OFFSET: + val =3D psi->regs[reg]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", add= r); + } + + return val; +} + +static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvPsi *psi =3D PNV_PSI(opaque); + Pnv9Psi *psi9 =3D PNV9_PSI(psi); + uint32_t reg =3D PSIHB_REG(addr); + MemoryRegion *sysmem =3D get_system_memory(); + + switch (addr) { + case PSIHB9_CR: + case PSIHB9_SEMR: + /* FSP stuff */ + break; + case PSIHB9_INTERRUPT_CONTROL: + if (val & PSIHB9_IRQ_RESET) { + device_reset(DEVICE(&psi9->source)); + } + psi->regs[reg] =3D val; + break; + + case PSIHB9_ESB_CI_BASE: + if (!(val & PSIHB9_ESB_CI_VALID)) { + if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) { + memory_region_del_subregion(sysmem, &psi9->source.esb_mmio= ); + } + } else { + if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) { + memory_region_add_subregion(sysmem, + val & ~PSIHB9_ESB_CI_VALID, + &psi9->source.esb_mmio); + } + } + psi->regs[reg] =3D val; + break; + + case PSIHB9_ESB_NOTIF_ADDR: + psi->regs[reg] =3D val; + break; + case PSIHB9_IVT_OFFSET: + psi->regs[reg] =3D val; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", ad= dr); + } +} + +static const MemoryRegionOps pnv_psi_p9_mmio_ops =3D { + .read =3D pnv_psi_p9_mmio_read, + .write =3D pnv_psi_p9_mmio_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 8, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 8, + .max_access_size =3D 8, + }, +}; + +static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned = size) +{ + /* No read are expected */ + qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", a= ddr); + return -1; +} + +static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvPsi *psi =3D PNV_PSI(opaque); + + /* XSCOM is only used to set the PSIHB MMIO region */ + switch (addr >> 3) { + case PSIHB_XSCOM_BAR: + pnv_psi_set_bar(psi, val); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\= n", + addr); + } +} + +static const MemoryRegionOps pnv_psi_p9_xscom_ops =3D { + .read =3D pnv_psi_p9_xscom_read, + .write =3D pnv_psi_p9_xscom_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 8, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 8, + .max_access_size =3D 8, + } +}; + +static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state) +{ + uint32_t irq_method =3D psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; + + if (irq > PSIHB9_NUM_IRQS) { + qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq); + return; + } + + if (irq_method & PSIHB9_IRQ_METHOD) { + qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n= "); + return; + } + + /* Update LSI levels */ + if (state) { + psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |=3D PPC_BIT(irq); + } else { + psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &=3D ~PPC_BIT(irq); + } + + qemu_set_irq(psi->qirqs[irq], state); +} + +static void pnv_psi_power9_reset(void *dev) +{ + Pnv9Psi *psi =3D PNV9_PSI(dev); + + pnv_psi_reset(dev); + + if (memory_region_is_mapped(&psi->source.esb_mmio)) { + memory_region_del_subregion(get_system_memory(), &psi->source.esb_= mmio); + } +} + +static void pnv_psi_power9_instance_init(Object *obj) +{ + Pnv9Psi *psi =3D PNV9_PSI(obj); + + object_initialize_child(obj, "source", &psi->source, sizeof(psi->sourc= e), + TYPE_XIVE_SOURCE, &error_abort, NULL); +} + +static void pnv_psi_power9_realize(DeviceState *dev, Error **errp) +{ + PnvPsi *psi =3D PNV_PSI(dev); + XiveSource *xsrc =3D &PNV9_PSI(psi)->source; + Error *local_err =3D NULL; + int i; + + /* This is the only device with 4k ESB pages */ + object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift", + &error_fatal); + object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs", + &error_fatal); + object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(psi), + &error_fatal); + object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + for (i =3D 0; i < xsrc->nr_irqs; i++) { + xive_source_irq_set_lsi(xsrc, i); + } + + psi->qirqs =3D qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_= irqs); + + /* XSCOM region for PSI registers */ + pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom= _ops, + psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE); + + /* MMIO region for PSI registers */ + memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops= , psi, + "psihb", PNV9_PSIHB_SIZE); + + pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); + + qemu_register_reset(pnv_psi_power9_reset, dev); +} + +static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvPsiClass *ppc =3D PNV_PSI_CLASS(klass); + XiveNotifierClass *xfc =3D XIVE_NOTIFIER_CLASS(klass); + + dc->desc =3D "PowerNV PSI Controller POWER9"; + dc->realize =3D pnv_psi_power9_realize; + + ppc->chip_type =3D PNV_CHIP_POWER9; + ppc->xscom_pcba =3D PNV9_XSCOM_PSIHB_BASE; + ppc->xscom_size =3D PNV9_XSCOM_PSIHB_SIZE; + ppc->bar_mask =3D PSIHB9_BAR_MASK; + ppc->irq_set =3D pnv_psi_power9_irq_set; + + xfc->notify =3D pnv_psi_notify; +} + +static const TypeInfo pnv_psi_power9_info =3D { + .name =3D TYPE_PNV9_PSI, + .parent =3D TYPE_PNV_PSI, + .instance_size =3D sizeof(Pnv9Psi), + .instance_init =3D pnv_psi_power9_instance_init, + .class_init =3D pnv_psi_power9_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_XIVE_NOTIFIER }, + { }, + }, +}; + static void pnv_psi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -612,6 +924,19 @@ static void pnv_psi_register_types(void) { type_register_static(&pnv_psi_info); type_register_static(&pnv_psi_power8_info); + type_register_static(&pnv_psi_power9_info); } =20 type_init(pnv_psi_register_types); + +void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon) +{ + PnvPsi *psi =3D PNV_PSI(psi9); + + uint32_t offset =3D + (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); + + monitor_printf(mon, "PSIHB Source %08x .. %08x\n", + offset, offset + psi9->source.nr_irqs - 1); + xive_source_pic_print_info(&psi9->source, offset, mon); +} --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998926569205.7954238501943; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:35:56 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZtc137159092 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Mar 2019 22:35:55 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7909FA40A2; Thu, 7 Mar 2019 22:35:55 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 65EF4A40A4; Thu, 7 Mar 2019 22:35:55 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:35:55 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id CCC92220227; Thu, 7 Mar 2019 23:35:54 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:36 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0028-0000-0000-000003515EF9 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0029-0000-0000-0000240FD27C Message-Id: <20190307223548.20516-4-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=432 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x27MIbbY119415 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v2 03/15] ppc/pnv: lpc: fix OPB address ranges X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The PowerNV LPC Controller exposes different sets of registers for each of the functional units it encompasses, among which the OPB (On-Chip Peripheral Bus) Master and Arbitrer and the LPC HOST Controller. The mapping addresses of each register range are correct but the sizes are too large. Fix the sizes and define the OPB Arbitrer range to fill the gap between the OPB Master registers and the LPC HOST Controller registers. Signed-off-by: C=C3=A9dric Le Goater --- Changes in v2 : - wrote a commit log hw/ppc/pnv_lpc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 9b18ce55e391..547be609cafe 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -89,10 +89,11 @@ enum { #define LPC_FW_OPB_SIZE 0x10000000 =20 #define LPC_OPB_REGS_OPB_ADDR 0xc0010000 -#define LPC_OPB_REGS_OPB_SIZE 0x00002000 +#define LPC_OPB_REGS_OPB_SIZE 0x00000060 +#define LPC_OPB_REGS_OPBA_ADDR 0xc0011000 +#define LPC_OPB_REGS_OPBA_SIZE 0x00000008 #define LPC_HC_REGS_OPB_ADDR 0xc0012000 -#define LPC_HC_REGS_OPB_SIZE 0x00001000 - +#define LPC_HC_REGS_OPB_SIZE 0x00000100 =20 static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_o= ffset) { --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998364588516.2712166694948; Thu, 7 Mar 2019 14:39:24 -0800 (PST) Received: from localhost ([127.0.0.1]:60532 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21fc-0000gF-Fn for importer@patchew.org; Thu, 07 Mar 2019 17:39:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:33871) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21cn-0006zw-JQ for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h21cl-0002Xe-7u for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:25 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:50986 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h21ck-0001yE-Cb for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:22 -0500 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x27MIlWW018672 for ; Thu, 7 Mar 2019 17:36:00 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2r39urxmjs-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 07 Mar 2019 17:36:00 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:35:57 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZuGr54460524 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 7 Mar 2019 22:35:56 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F3B984C082; Thu, 7 Mar 2019 22:35:55 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D8EFD4C088; Thu, 7 Mar 2019 22:35:55 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:35:55 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 5D377220062; Thu, 7 Mar 2019 23:35:55 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:37 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-4275-0000-0000-00000318537E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-4276-0000-0000-00003826AF2A Message-Id: <20190307223548.20516-5-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=963 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x27MIlWW018672 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2 04/15] ppc/pnv: add a LPC Controller class model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" It will ease the introduction of the LPC Controller model for POWER9. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- include/hw/ppc/pnv_lpc.h | 15 +++++++ hw/ppc/pnv.c | 2 +- hw/ppc/pnv_lpc.c | 85 ++++++++++++++++++++++++++++------------ 3 files changed, 77 insertions(+), 25 deletions(-) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index d657489b07ce..f3f24419b19a 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -24,6 +24,8 @@ #define TYPE_PNV_LPC "pnv-lpc" #define PNV_LPC(obj) \ OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) +#define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8" +#define PNV8_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV8_LPC) =20 typedef struct PnvLpcController { DeviceState parent; @@ -70,6 +72,19 @@ typedef struct PnvLpcController { PnvPsi *psi; } PnvLpcController; =20 +#define PNV_LPC_CLASS(klass) \ + OBJECT_CLASS_CHECK(PnvLpcClass, (klass), TYPE_PNV_LPC) +#define PNV_LPC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(PnvLpcClass, (obj), TYPE_PNV_LPC) + +typedef struct PnvLpcClass { + DeviceClass parent_class; + + int psi_irq; + + DeviceRealize parent_realize; +} PnvLpcClass; + ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **e= rrp); =20 #endif /* _PPC_PNV_LPC_H */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 1cc454cbbc27..922e3ec48bb5 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -794,7 +794,7 @@ static void pnv_chip_power8_instance_init(Object *obj) OBJECT(qdev_get_machine()), &error_abor= t); =20 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), - TYPE_PNV_LPC, &error_abort, NULL); + TYPE_PNV8_LPC, &error_abort, NULL); object_property_add_const_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), &error_abort); =20 diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 547be609cafe..3c509a30a0af 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -245,6 +245,7 @@ static const MemoryRegionOps pnv_lpc_xscom_ops =3D { static void pnv_lpc_eval_irqs(PnvLpcController *lpc) { bool lpc_to_opb_irq =3D false; + PnvLpcClass *plc =3D PNV_LPC_GET_CLASS(lpc); =20 /* Update LPC controller to OPB line */ if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { @@ -267,7 +268,7 @@ static void pnv_lpc_eval_irqs(PnvLpcController *lpc) lpc->opb_irq_stat |=3D lpc->opb_irq_input & lpc->opb_irq_mask; =20 /* Reflect the interrupt */ - pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat !=3D 0); + pnv_psi_irq_set(lpc->psi, plc->psi_irq, lpc->opb_irq_stat !=3D 0); } =20 static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) @@ -419,11 +420,65 @@ static const MemoryRegionOps opb_master_ops =3D { }, }; =20 +static void pnv_lpc_power8_realize(DeviceState *dev, Error **errp) +{ + PnvLpcController *lpc =3D PNV_LPC(dev); + PnvLpcClass *plc =3D PNV_LPC_GET_CLASS(dev); + Error *local_err =3D NULL; + + plc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + /* P8 uses a XSCOM region for LPC registers */ + pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(lpc), + &pnv_lpc_xscom_ops, lpc, "xscom-lpc", + PNV_XSCOM_LPC_SIZE); +} + +static void pnv_lpc_power8_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvXScomInterfaceClass *xdc =3D PNV_XSCOM_INTERFACE_CLASS(klass); + PnvLpcClass *plc =3D PNV_LPC_CLASS(klass); + + dc->desc =3D "PowerNV LPC Controller POWER8"; + + xdc->dt_xscom =3D pnv_lpc_dt_xscom; + + plc->psi_irq =3D PSIHB_IRQ_LPC_I2C; + + device_class_set_parent_realize(dc, pnv_lpc_power8_realize, + &plc->parent_realize); +} + +static const TypeInfo pnv_lpc_power8_info =3D { + .name =3D TYPE_PNV8_LPC, + .parent =3D TYPE_PNV_LPC, + .instance_size =3D sizeof(PnvLpcController), + .class_init =3D pnv_lpc_power8_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_PNV_XSCOM_INTERFACE }, + { } + } +}; + static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc =3D PNV_LPC(dev); Object *obj; - Error *error =3D NULL; + Error *local_err =3D NULL; + + obj =3D object_property_get_link(OBJECT(dev), "psi", &local_err); + if (!obj) { + error_propagate(errp, local_err); + error_prepend(errp, "required link 'psi' not found: "); + return; + } + /* The LPC controller needs PSI to generate interrupts */ + lpc->psi =3D PNV_PSI(obj); =20 /* Reg inits */ lpc->lpc_hc_fw_rd_acc_size =3D LPC_HC_FW_RD_4B; @@ -463,46 +518,28 @@ static void pnv_lpc_realize(DeviceState *dev, Error *= *errp) "lpc-hc", LPC_HC_REGS_OPB_SIZE); memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR, &lpc->lpc_hc_regs); - - /* XScom region for LPC registers */ - pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), - &pnv_lpc_xscom_ops, lpc, "xscom-lpc", - PNV_XSCOM_LPC_SIZE); - - /* get PSI object from chip */ - obj =3D object_property_get_link(OBJECT(dev), "psi", &error); - if (!obj) { - error_setg(errp, "%s: required link 'psi' not found: %s", - __func__, error_get_pretty(error)); - return; - } - lpc->psi =3D PNV_PSI(obj); } =20 static void pnv_lpc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); - PnvXScomInterfaceClass *xdc =3D PNV_XSCOM_INTERFACE_CLASS(klass); - - xdc->dt_xscom =3D pnv_lpc_dt_xscom; =20 dc->realize =3D pnv_lpc_realize; + dc->desc =3D "PowerNV LPC Controller"; } =20 static const TypeInfo pnv_lpc_info =3D { .name =3D TYPE_PNV_LPC, .parent =3D TYPE_DEVICE, - .instance_size =3D sizeof(PnvLpcController), .class_init =3D pnv_lpc_class_init, - .interfaces =3D (InterfaceInfo[]) { - { TYPE_PNV_XSCOM_INTERFACE }, - { } - } + .class_size =3D sizeof(PnvLpcClass), + .abstract =3D true, }; =20 static void pnv_lpc_register_types(void) { type_register_static(&pnv_lpc_info); + type_register_static(&pnv_lpc_power8_info); } =20 type_init(pnv_lpc_register_types) --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551999141002252.8698405829466; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:35:57 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZuZ126935422 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Mar 2019 22:35:56 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 69A6DA40A3; Thu, 7 Mar 2019 22:35:56 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 56C79A40A2; Thu, 7 Mar 2019 22:35:56 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:35:56 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id D0348220227; Thu, 7 Mar 2019 23:35:55 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:38 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0012-0000-0000-000002FFF8DE X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0013-0000-0000-000021370903 Message-Id: <20190307223548.20516-6-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=789 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0b-001b2d01.pphosted.com id x27MIac1057220 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2 05/15] ppc/pnv: add a 'dt_isa_nodename' to the chip X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The ISA bus has a different DT nodename on POWER9. Compute the name when the PnvChip is realized, that is before it is used by the machine to populate the device tree with the ISA devices. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 2 ++ hw/ppc/pnv.c | 18 +++++------------- 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 8d80cb34eebb..c81f157f41a9 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -58,6 +58,8 @@ typedef struct PnvChip { MemoryRegion xscom_mmio; MemoryRegion xscom; AddressSpace xscom_as; + + gchar *dt_isa_nodename; } PnvChip; =20 #define TYPE_PNV8_CHIP "pnv8-chip" diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 922e3ec48bb5..6625562d276d 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -417,24 +417,12 @@ static int pnv_dt_isa_device(DeviceState *dev, void *= opaque) return 0; } =20 -static int pnv_chip_isa_offset(PnvChip *chip, void *fdt) -{ - char *name; - int offset; - - name =3D g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", - (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_= BASE); - offset =3D fdt_path_offset(fdt, name); - g_free(name); - return offset; -} - /* The default LPC bus of a multichip system is on chip 0. It's * recognized by the firmware (skiboot) using a "primary" property. */ static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) { - int isa_offset =3D pnv_chip_isa_offset(pnv->chips[0], fdt); + int isa_offset =3D fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename= ); ForeachPopulateArgs args =3D { .fdt =3D fdt, .offset =3D isa_offset, @@ -866,6 +854,10 @@ static void pnv_chip_power8_realize(DeviceState *dev, = Error **errp) &error_fatal); pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_re= gs); =20 + chip->dt_isa_nodename =3D g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", + (uint64_t) PNV_XSCOM_BASE(chip= ), + PNV_XSCOM_LPC_BASE); + /* Interrupt Management Area. This is the memory region holding * all the Interrupt Control Presenter (ICP) registers */ pnv_chip_icp_realize(chip8, &local_err); --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998385569492.45593501523024; Thu, 7 Mar 2019 14:39:45 -0800 (PST) Received: from localhost ([127.0.0.1]:60538 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21fv-0000z9-E8 for importer@patchew.org; Thu, 07 Mar 2019 17:39:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:33965) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21cu-000772-NP for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h21co-0002ev-Uw for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:28 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:47400) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h21cn-00020b-H8 for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:26 -0500 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x27MIe3Y139210 for ; Thu, 7 Mar 2019 17:36:02 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2r3a23nu0w-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 07 Mar 2019 17:36:01 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:35:58 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZvcg30933084 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Mar 2019 22:35:57 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 11E9411C06C; Thu, 7 Mar 2019 22:35:57 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E8E0A11C071; Thu, 7 Mar 2019 22:35:56 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:35:56 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 53AFF220062; Thu, 7 Mar 2019 23:35:56 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:39 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0008-0000-0000-000002C9FB7E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0009-0000-0000-000022360B29 Message-Id: <20190307223548.20516-7-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x27MIe3Y139210 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v2 06/15] ppc/pnv: add a LPC Controller model for POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The LPC Controller on POWER9 is very similar to the one found on POWER8 but accesses are now done via on MMIOs, without the XSCOM and ECCB logic. The device tree is populated differently so we add a specific POWER9 routine for the purpose. SerIRQ routing is yet to be done. Signed-off-by: C=C3=A9dric Le Goater --- Changes in v2: - defined a 'dt_isa_nodename' for the POWER9 chip include/hw/ppc/pnv.h | 4 + include/hw/ppc/pnv_lpc.h | 9 ++ hw/ppc/pnv.c | 22 ++++- hw/ppc/pnv_lpc.c | 200 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 234 insertions(+), 1 deletion(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index c81f157f41a9..1cd1ad622d0b 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -87,6 +87,7 @@ typedef struct Pnv9Chip { /*< public >*/ PnvXive xive; Pnv9Psi psi; + PnvLpcController lpc; } Pnv9Chip; =20 typedef struct PnvChipClass { @@ -234,6 +235,9 @@ void pnv_bmc_powerdown(IPMIBmc *bmc); #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060180000000= 00ull) =20 +#define PNV9_LPCM_SIZE 0x0000000100000000ull +#define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060300000000= 00ull) + #define PNV9_PSIHB_SIZE 0x0000000000100000ull #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302030000= 00ull) =20 diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index f3f24419b19a..242b18081caa 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -27,6 +27,9 @@ #define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8" #define PNV8_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV8_LPC) =20 +#define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9" +#define PNV9_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV9_LPC) + typedef struct PnvLpcController { DeviceState parent; =20 @@ -85,6 +88,12 @@ typedef struct PnvLpcClass { DeviceRealize parent_realize; } PnvLpcClass; =20 +/* + * Old compilers error on typdef forward declarations. Keep them happy. + */ +struct PnvChip; + ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **e= rrp); +int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset); =20 #endif /* _PPC_PNV_LPC_H */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 6625562d276d..918fae057b5c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -306,6 +306,8 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, = void *fdt) if (chip->ram_size) { pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } + + pnv_dt_lpc(chip, fdt, 0); } =20 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) @@ -547,7 +549,8 @@ static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *c= hip, Error **errp) =20 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) { - return NULL; + Pnv9Chip *chip9 =3D PNV9_CHIP(chip); + return pnv_lpc_isa_create(&chip9->lpc, false, errp); } =20 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) @@ -948,6 +951,11 @@ static void pnv_chip_power9_instance_init(Object *obj) TYPE_PNV9_PSI, &error_abort, NULL); object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj, &error_abort); + + object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), + TYPE_PNV9_LPC, &error_abort, NULL); + object_property_add_const_link(OBJECT(&chip9->lpc), "psi", + OBJECT(&chip9->psi), &error_abort); } =20 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) @@ -992,6 +1000,18 @@ static void pnv_chip_power9_realize(DeviceState *dev,= Error **errp) } pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, &PNV_PSI(psi9)->xscom_regs); + + /* LPC */ + object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local= _err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), + &chip9->lpc.xscom_regs); + + chip->dt_isa_nodename =3D g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0= ", + (uint64_t) PNV9_LPCM_BASE(chip= )); } =20 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 3c509a30a0af..6df694e0abc1 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -118,6 +118,100 @@ static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, v= oid *fdt, int xscom_offset) return 0; } =20 +/* POWER9 only */ +int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset) +{ + const char compat[] =3D "ibm,power9-lpcm-opb\0simple-bus"; + const char lpc_compat[] =3D "ibm,power9-lpc\0ibm,lpc"; + char *name; + int offset, lpcm_offset; + uint64_t lpcm_addr =3D PNV9_LPCM_BASE(chip); + uint32_t opb_ranges[8] =3D { 0, + cpu_to_be32(lpcm_addr >> 32), + cpu_to_be32((uint32_t)lpcm_addr), + cpu_to_be32(PNV9_LPCM_SIZE / 2), + cpu_to_be32(PNV9_LPCM_SIZE / 2), + cpu_to_be32(lpcm_addr >> 32), + cpu_to_be32(PNV9_LPCM_SIZE / 2), + cpu_to_be32(PNV9_LPCM_SIZE / 2), + }; + uint32_t opb_reg[4] =3D { cpu_to_be32(lpcm_addr >> 32), + cpu_to_be32((uint32_t)lpcm_addr), + cpu_to_be32(PNV9_LPCM_SIZE >> 32), + cpu_to_be32((uint32_t)PNV9_LPCM_SIZE), + }; + uint32_t reg[2]; + + /* + * OPB bus + */ + name =3D g_strdup_printf("lpcm-opb@%"PRIx64, lpcm_addr); + lpcm_offset =3D fdt_add_subnode(fdt, root_offset, name); + _FDT(lpcm_offset); + g_free(name); + + _FDT((fdt_setprop(fdt, lpcm_offset, "reg", opb_reg, sizeof(opb_reg)))); + _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1))); + _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#size-cells", 1))); + _FDT((fdt_setprop(fdt, lpcm_offset, "compatible", compat, sizeof(compa= t)))); + _FDT((fdt_setprop_cell(fdt, lpcm_offset, "ibm,chip-id", chip->chip_id)= )); + _FDT((fdt_setprop(fdt, lpcm_offset, "ranges", opb_ranges, + sizeof(opb_ranges)))); + + /* + * OPB Master registers + */ + name =3D g_strdup_printf("opb-master@%x", LPC_OPB_REGS_OPB_ADDR); + offset =3D fdt_add_subnode(fdt, lpcm_offset, name); + _FDT(offset); + g_free(name); + + reg[0] =3D cpu_to_be32(LPC_OPB_REGS_OPB_ADDR); + reg[1] =3D cpu_to_be32(LPC_OPB_REGS_OPB_SIZE); + _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); + _FDT((fdt_setprop_string(fdt, offset, "compatible", + "ibm,power9-lpcm-opb-master"))); + + /* + * OPB arbitrer registers + */ + name =3D g_strdup_printf("opb-arbitrer@%x", LPC_OPB_REGS_OPBA_ADDR); + offset =3D fdt_add_subnode(fdt, lpcm_offset, name); + _FDT(offset); + g_free(name); + + reg[0] =3D cpu_to_be32(LPC_OPB_REGS_OPBA_ADDR); + reg[1] =3D cpu_to_be32(LPC_OPB_REGS_OPBA_SIZE); + _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); + _FDT((fdt_setprop_string(fdt, offset, "compatible", + "ibm,power9-lpcm-opb-arbiter"))); + + /* + * LPC Host Controller registers + */ + name =3D g_strdup_printf("lpc-controller@%x", LPC_HC_REGS_OPB_ADDR); + offset =3D fdt_add_subnode(fdt, lpcm_offset, name); + _FDT(offset); + g_free(name); + + reg[0] =3D cpu_to_be32(LPC_HC_REGS_OPB_ADDR); + reg[1] =3D cpu_to_be32(LPC_HC_REGS_OPB_SIZE); + _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); + _FDT((fdt_setprop_string(fdt, offset, "compatible", + "ibm,power9-lpc-controller"))); + + name =3D g_strdup_printf("lpc@0"); + offset =3D fdt_add_subnode(fdt, lpcm_offset, name); + _FDT(offset); + g_free(name); + _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); + _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); + _FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat, + sizeof(lpc_compat)))); + + return 0; +} + /* * These read/write handlers of the OPB address space should be common * with the P9 LPC Controller which uses direct MMIOs. @@ -242,6 +336,74 @@ static const MemoryRegionOps pnv_lpc_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned size) +{ + PnvLpcController *lpc =3D PNV_LPC(opaque); + uint64_t val =3D 0; + uint32_t opb_addr =3D addr & ECCB_CTL_ADDR_MASK; + MemTxResult result; + + switch (size) { + case 4: + val =3D address_space_ldl(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPE= CIFIED, + &result); + break; + case 1: + val =3D address_space_ldub(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSP= ECIFIED, + &result); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%" + HWADDR_PRIx " invalid size %d\n", addr, size); + return 0; + } + + if (result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%" + HWADDR_PRIx "\n", addr); + } + + return val; +} + +static void pnv_lpc_mmio_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvLpcController *lpc =3D PNV_LPC(opaque); + uint32_t opb_addr =3D addr & ECCB_CTL_ADDR_MASK; + MemTxResult result; + + switch (size) { + case 4: + address_space_stl(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIF= IED, + &result); + break; + case 1: + address_space_stb(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIF= IED, + &result); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%" + HWADDR_PRIx " invalid size %d\n", addr, size); + return; + } + + if (result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%" + HWADDR_PRIx "\n", addr); + } +} + +static const MemoryRegionOps pnv_lpc_mmio_ops =3D { + .read =3D pnv_lpc_mmio_read, + .write =3D pnv_lpc_mmio_write, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + static void pnv_lpc_eval_irqs(PnvLpcController *lpc) { bool lpc_to_opb_irq =3D false; @@ -465,6 +627,43 @@ static const TypeInfo pnv_lpc_power8_info =3D { } }; =20 +static void pnv_lpc_power9_realize(DeviceState *dev, Error **errp) +{ + PnvLpcController *lpc =3D PNV_LPC(dev); + PnvLpcClass *plc =3D PNV_LPC_GET_CLASS(dev); + Error *local_err =3D NULL; + + plc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + /* P9 uses a MMIO region */ + memory_region_init_io(&lpc->xscom_regs, OBJECT(lpc), &pnv_lpc_mmio_ops, + lpc, "lpcm", PNV9_LPCM_SIZE); +} + +static void pnv_lpc_power9_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvLpcClass *plc =3D PNV_LPC_CLASS(klass); + + dc->desc =3D "PowerNV LPC Controller POWER9"; + + plc->psi_irq =3D PSIHB9_IRQ_LPCHC; + + device_class_set_parent_realize(dc, pnv_lpc_power9_realize, + &plc->parent_realize); +} + +static const TypeInfo pnv_lpc_power9_info =3D { + .name =3D TYPE_PNV9_LPC, + .parent =3D TYPE_PNV_LPC, + .instance_size =3D sizeof(PnvLpcController), + .class_init =3D pnv_lpc_power9_class_init, +}; + static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc =3D PNV_LPC(dev); @@ -540,6 +739,7 @@ static void pnv_lpc_register_types(void) { type_register_static(&pnv_lpc_info); type_register_static(&pnv_lpc_power8_info); + type_register_static(&pnv_lpc_power9_info); } =20 type_init(pnv_lpc_register_types) --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998334150997.0523412774969; Thu, 7 Mar 2019 14:38:54 -0800 (PST) Received: from localhost ([127.0.0.1]:60530 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21f0-00007f-V9 for importer@patchew.org; Thu, 07 Mar 2019 17:38:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:33865) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21cn-0006zv-IG for qemu-devel@nongnu.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:35:58 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZvj140566994 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 7 Mar 2019 22:35:57 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9D401522F1; Thu, 7 Mar 2019 22:35:57 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 898FE522F0; Thu, 7 Mar 2019 22:35:57 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id EA553220227; Thu, 7 Mar 2019 23:35:56 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:40 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0028-0000-0000-000003515EFC X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0029-0000-0000-0000240FD27E Message-Id: <20190307223548.20516-8-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=774 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x27MIbg6071065 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2 07/15] ppc/pnv: add SerIRQ routing registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is just a simple reminder that SerIRQ routing should be addressed. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv_lpc.h | 2 ++ hw/ppc/pnv_lpc.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 242b18081caa..413579792ed1 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -55,6 +55,8 @@ typedef struct PnvLpcController { MemoryRegion opb_master_regs; =20 /* OPB Master LS registers */ + uint32_t opb_irq_route0; + uint32_t opb_irq_route1; uint32_t opb_irq_stat; uint32_t opb_irq_mask; uint32_t opb_irq_pol; diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 6df694e0abc1..641e2046db92 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -39,6 +39,8 @@ enum { }; =20 /* OPB Master LS registers */ +#define OPB_MASTER_LS_ROUTE0 0x8 +#define OPB_MASTER_LS_ROUTE1 0xC #define OPB_MASTER_LS_IRQ_STAT 0x50 #define OPB_MASTER_IRQ_LPC 0x00000800 #define OPB_MASTER_LS_IRQ_MASK 0x54 @@ -521,6 +523,12 @@ static uint64_t opb_master_read(void *opaque, hwaddr a= ddr, unsigned size) uint64_t val =3D 0xfffffffffffffffful; =20 switch (addr) { + case OPB_MASTER_LS_ROUTE0: /* TODO */ + val =3D lpc->opb_irq_route0; + break; + case OPB_MASTER_LS_ROUTE1: /* TODO */ + val =3D lpc->opb_irq_route1; + break; case OPB_MASTER_LS_IRQ_STAT: val =3D lpc->opb_irq_stat; break; @@ -547,6 +555,12 @@ static void opb_master_write(void *opaque, hwaddr addr, PnvLpcController *lpc =3D opaque; =20 switch (addr) { + case OPB_MASTER_LS_ROUTE0: /* TODO */ + lpc->opb_irq_route0 =3D val; + break; + case OPB_MASTER_LS_ROUTE1: /* TODO */ + lpc->opb_irq_route1 =3D val; + break; case OPB_MASTER_LS_IRQ_STAT: lpc->opb_irq_stat &=3D ~val; pnv_lpc_eval_irqs(lpc); --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998900084561.2356574172674; Thu, 7 Mar 2019 14:48:20 -0800 (PST) Received: from localhost ([127.0.0.1]:60693 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21o9-0000Xo-PA for importer@patchew.org; Thu, 07 Mar 2019 17:48:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21dR-0007eZ-KK for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:37:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h21dQ-0003WB-2K for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:37:05 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:45404 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h21dO-000237-MN for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:37:02 -0500 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x27MJ5rJ172810 for ; Thu, 7 Mar 2019 17:36:04 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0b-001b2d01.pphosted.com with ESMTP id 2r38ya92pg-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 07 Mar 2019 17:36:04 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:35:59 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZwdT36372514 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 7 Mar 2019 22:35:58 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3F205522F0; Thu, 7 Mar 2019 22:35:58 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 25A5E522F1; Thu, 7 Mar 2019 22:35:58 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 95E4B220062; Thu, 7 Mar 2019 23:35:57 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:41 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0016-0000-0000-0000025F4197 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0017-0000-0000-000032B9D1B1 Message-Id: <20190307223548.20516-9-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0b-001b2d01.pphosted.com id x27MJ5rJ172810 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2 08/15] ppc/pnv: add a OCC model class X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" To ease the introduction of the OCC model for POWER9, provide a new class attributes to define XSCOM operations per CPU family and a PSI IRQ number. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- Changes in v2: - new attributes to define XSCOM operations per CPU family and a PSI IRQ number. include/hw/ppc/pnv_occ.h | 15 +++++++++++ hw/ppc/pnv.c | 2 +- hw/ppc/pnv_occ.c | 55 +++++++++++++++++++++++++++------------- 3 files changed, 54 insertions(+), 18 deletions(-) diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h index 82f299dc76ff..dab5a05f8e99 100644 --- a/include/hw/ppc/pnv_occ.h +++ b/include/hw/ppc/pnv_occ.h @@ -23,6 +23,8 @@ =20 #define TYPE_PNV_OCC "pnv-occ" #define PNV_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV_OCC) +#define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8" +#define PNV8_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV8_OCC) =20 typedef struct PnvOCC { DeviceState xd; @@ -35,4 +37,17 @@ typedef struct PnvOCC { MemoryRegion xscom_regs; } PnvOCC; =20 +#define PNV_OCC_CLASS(klass) \ + OBJECT_CLASS_CHECK(PnvOCCClass, (klass), TYPE_PNV_OCC) +#define PNV_OCC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(PnvOCCClass, (obj), TYPE_PNV_OCC) + +typedef struct PnvOCCClass { + DeviceClass parent_class; + + int xscom_size; + const MemoryRegionOps *xscom_ops; + int psi_irq; +} PnvOCCClass; + #endif /* _PPC_PNV_OCC_H */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 918fae057b5c..6ae9ce679505 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -790,7 +790,7 @@ static void pnv_chip_power8_instance_init(Object *obj) OBJECT(&chip8->psi), &error_abort); =20 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), - TYPE_PNV_OCC, &error_abort, NULL); + TYPE_PNV8_OCC, &error_abort, NULL); object_property_add_const_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), &error_abort); } diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 04880f26d612..ea725647c988 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -34,15 +34,17 @@ static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) { bool irq_state; + PnvOCCClass *poc =3D PNV_OCC_GET_CLASS(occ); =20 val &=3D 0xffff000000000000ull; =20 occ->occmisc =3D val; irq_state =3D !!(val >> 63); - pnv_psi_irq_set(occ->psi, PSIHB_IRQ_OCC, irq_state); + pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state); } =20 -static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, unsigned siz= e) +static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr, + unsigned size) { PnvOCC *occ =3D PNV_OCC(opaque); uint32_t offset =3D addr >> 3; @@ -54,13 +56,13 @@ static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr= addr, unsigned size) break; default: qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" - HWADDR_PRIx "\n", addr); + HWADDR_PRIx "\n", addr >> 3); } return val; } =20 -static void pnv_occ_xscom_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { PnvOCC *occ =3D PNV_OCC(opaque); uint32_t offset =3D addr >> 3; @@ -77,13 +79,13 @@ static void pnv_occ_xscom_write(void *opaque, hwaddr ad= dr, break; default: qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" - HWADDR_PRIx "\n", addr); + HWADDR_PRIx "\n", addr >> 3); } } =20 -static const MemoryRegionOps pnv_occ_xscom_ops =3D { - .read =3D pnv_occ_xscom_read, - .write =3D pnv_occ_xscom_write, +static const MemoryRegionOps pnv_occ_power8_xscom_ops =3D { + .read =3D pnv_occ_power8_xscom_read, + .write =3D pnv_occ_power8_xscom_write, .valid.min_access_size =3D 8, .valid.max_access_size =3D 8, .impl.min_access_size =3D 8, @@ -91,27 +93,42 @@ static const MemoryRegionOps pnv_occ_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +static void pnv_occ_power8_class_init(ObjectClass *klass, void *data) +{ + PnvOCCClass *poc =3D PNV_OCC_CLASS(klass); + + poc->xscom_size =3D PNV_XSCOM_OCC_SIZE; + poc->xscom_ops =3D &pnv_occ_power8_xscom_ops; + poc->psi_irq =3D PSIHB_IRQ_OCC; +} + +static const TypeInfo pnv_occ_power8_type_info =3D { + .name =3D TYPE_PNV8_OCC, + .parent =3D TYPE_PNV_OCC, + .instance_size =3D sizeof(PnvOCC), + .class_init =3D pnv_occ_power8_class_init, +}; =20 static void pnv_occ_realize(DeviceState *dev, Error **errp) { PnvOCC *occ =3D PNV_OCC(dev); + PnvOCCClass *poc =3D PNV_OCC_GET_CLASS(occ); Object *obj; - Error *error =3D NULL; + Error *local_err =3D NULL; =20 occ->occmisc =3D 0; =20 - /* get PSI object from chip */ - obj =3D object_property_get_link(OBJECT(dev), "psi", &error); + obj =3D object_property_get_link(OBJECT(dev), "psi", &local_err); if (!obj) { - error_setg(errp, "%s: required link 'psi' not found: %s", - __func__, error_get_pretty(error)); + error_propagate(errp, local_err); + error_prepend(errp, "required link 'psi' not found: "); return; } occ->psi =3D PNV_PSI(obj); =20 /* XScom region for OCC registers */ - pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), &pnv_occ_xscom_op= s, - occ, "xscom-occ", PNV_XSCOM_OCC_SIZE); + pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops, + occ, "xscom-occ", poc->xscom_size); } =20 static void pnv_occ_class_init(ObjectClass *klass, void *data) @@ -119,6 +136,7 @@ static void pnv_occ_class_init(ObjectClass *klass, void= *data) DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D pnv_occ_realize; + dc->desc =3D "PowerNV OCC Controller"; } =20 static const TypeInfo pnv_occ_type_info =3D { @@ -126,11 +144,14 @@ static const TypeInfo pnv_occ_type_info =3D { .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(PnvOCC), .class_init =3D pnv_occ_class_init, + .class_size =3D sizeof(PnvOCCClass), + .abstract =3D true, }; =20 static void pnv_occ_register_types(void) { type_register_static(&pnv_occ_type_info); + type_register_static(&pnv_occ_power8_type_info); } =20 -type_init(pnv_occ_register_types) +type_init(pnv_occ_register_types); --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15519985287651006.9468866089074; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:35:59 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZw9P21495918 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Mar 2019 22:35:59 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CB259AE376; Thu, 7 Mar 2019 22:35:58 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BAABBAE374; Thu, 7 Mar 2019 22:35:58 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:35:58 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 3105B220227; Thu, 7 Mar 2019 23:35:58 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:42 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-4275-0000-0000-000003185382 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-4276-0000-0000-00003826AF2D Message-Id: <20190307223548.20516-10-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=953 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0b-001b2d01.pphosted.com id x27MZrsF039358 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2 09/15] ppc/pnv: add a OCC model for POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The OCC on POWER9 is very similar to the one found on POWER8. Provide the same routines with P9 values for the registers and IRQ number. Signed-off-by: C=C3=A9dric Le Goater --- Changes in v2 : - made use of the new class attributes for POWER9 include/hw/ppc/pnv.h | 1 + include/hw/ppc/pnv_occ.h | 2 ++ include/hw/ppc/pnv_xscom.h | 3 ++ hw/ppc/pnv.c | 13 +++++++ hw/ppc/pnv_occ.c | 72 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 91 insertions(+) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 1cd1ad622d0b..39888f9d52c1 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -88,6 +88,7 @@ typedef struct Pnv9Chip { PnvXive xive; Pnv9Psi psi; PnvLpcController lpc; + PnvOCC occ; } Pnv9Chip; =20 typedef struct PnvChipClass { diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h index dab5a05f8e99..d22b65a71abe 100644 --- a/include/hw/ppc/pnv_occ.h +++ b/include/hw/ppc/pnv_occ.h @@ -25,6 +25,8 @@ #define PNV_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV_OCC) #define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8" #define PNV8_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV8_OCC) +#define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9" +#define PNV9_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV9_OCC) =20 typedef struct PnvOCC { DeviceState xd; diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 403a365ed274..3292459fbb78 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -73,6 +73,9 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_OCC_BASE 0x0066000 #define PNV_XSCOM_OCC_SIZE 0x6000 =20 +#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE +#define PNV9_XSCOM_OCC_SIZE 0x8000 + #define PNV9_XSCOM_PSIHB_BASE 0x5012900 #define PNV9_XSCOM_PSIHB_SIZE 0x100 =20 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 6ae9ce679505..1559a733235b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -956,6 +956,11 @@ static void pnv_chip_power9_instance_init(Object *obj) TYPE_PNV9_LPC, &error_abort, NULL); object_property_add_const_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), &error_abort); + + object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), + TYPE_PNV9_OCC, &error_abort, NULL); + object_property_add_const_link(OBJECT(&chip9->occ), "psi", + OBJECT(&chip9->psi), &error_abort); } =20 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) @@ -1012,6 +1017,14 @@ static void pnv_chip_power9_realize(DeviceState *dev= , Error **errp) =20 chip->dt_isa_nodename =3D g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0= ", (uint64_t) PNV9_LPCM_BASE(chip= )); + + /* Create the simplified OCC model */ + object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local= _err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_r= egs); } =20 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index ea725647c988..fdd9296e1bc7 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -109,6 +109,77 @@ static const TypeInfo pnv_occ_power8_type_info =3D { .class_init =3D pnv_occ_power8_class_init, }; =20 +#define P9_OCB_OCI_OCCMISC 0x6080 +#define P9_OCB_OCI_OCCMISC_CLEAR 0x6081 +#define P9_OCB_OCI_OCCMISC_OR 0x6082 + + +static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvOCC *occ =3D PNV_OCC(opaque); + uint32_t offset =3D addr >> 3; + uint64_t val =3D 0; + + switch (offset) { + case P9_OCB_OCI_OCCMISC: + val =3D occ->occmisc; + break; + default: + qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" + HWADDR_PRIx "\n", addr >> 3); + } + return val; +} + +static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvOCC *occ =3D PNV_OCC(opaque); + uint32_t offset =3D addr >> 3; + + switch (offset) { + case P9_OCB_OCI_OCCMISC_CLEAR: + pnv_occ_set_misc(occ, 0); + break; + case P9_OCB_OCI_OCCMISC_OR: + pnv_occ_set_misc(occ, occ->occmisc | val); + break; + case P9_OCB_OCI_OCCMISC: + pnv_occ_set_misc(occ, val); + break; + default: + qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" + HWADDR_PRIx "\n", addr >> 3); + } +} + +static const MemoryRegionOps pnv_occ_power9_xscom_ops =3D { + .read =3D pnv_occ_power9_xscom_read, + .write =3D pnv_occ_power9_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void pnv_occ_power9_class_init(ObjectClass *klass, void *data) +{ + PnvOCCClass *poc =3D PNV_OCC_CLASS(klass); + + poc->xscom_size =3D PNV9_XSCOM_OCC_SIZE; + poc->xscom_ops =3D &pnv_occ_power9_xscom_ops; + poc->psi_irq =3D PSIHB9_IRQ_OCC; +} + +static const TypeInfo pnv_occ_power9_type_info =3D { + .name =3D TYPE_PNV9_OCC, + .parent =3D TYPE_PNV_OCC, + .instance_size =3D sizeof(PnvOCC), + .class_init =3D pnv_occ_power9_class_init, +}; + static void pnv_occ_realize(DeviceState *dev, Error **errp) { PnvOCC *occ =3D PNV_OCC(dev); @@ -152,6 +223,7 @@ static void pnv_occ_register_types(void) { type_register_static(&pnv_occ_type_info); type_register_static(&pnv_occ_power8_type_info); + type_register_static(&pnv_occ_power9_type_info); } =20 type_init(pnv_occ_register_types); --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:36:00 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZxcW46334000 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Mar 2019 22:35:59 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5EFE3AE36D; Thu, 7 Mar 2019 22:35:59 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 44E98AE370; Thu, 7 Mar 2019 22:35:59 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:35:59 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id B3A5D220062; Thu, 7 Mar 2019 23:35:58 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:43 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0016-0000-0000-0000025F4198 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0017-0000-0000-000032B9D1B2 Message-Id: <20190307223548.20516-11-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x27MMaOB042909 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v2 10/15] ppc/pnv: extend XSCOM core support for POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Provide a new class attribute to define XSCOM operations per CPU family and add a couple of XSCOM addresses controlling the power management states of the core on POWER9. Signed-off-by: C=C3=A9dric Le Goater --- Changes in v2 : - new class attribute to define XSCOM operations per CPU family include/hw/ppc/pnv_core.h | 2 + hw/ppc/pnv_core.c | 100 +++++++++++++++++++++++++++++++++----- 2 files changed, 89 insertions(+), 13 deletions(-) diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 6874bb847a01..cbe9ad36f32c 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -42,6 +42,8 @@ typedef struct PnvCore { =20 typedef struct PnvCoreClass { DeviceClass parent_class; + + const MemoryRegionOps *xscom_ops; } PnvCoreClass; =20 #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 38179cdc53dc..171474e0805c 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -60,8 +60,8 @@ static void pnv_cpu_reset(void *opaque) #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 =20 -static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr, - unsigned int width) +static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, + unsigned int width) { uint32_t offset =3D addr >> 3; uint64_t val =3D 0; @@ -82,16 +82,74 @@ static uint64_t pnv_core_xscom_read(void *opaque, hwadd= r addr, return val; } =20 -static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int width) +static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_= t val, + unsigned int width) { qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=3D0x%" HWADDR_PRIx "= \n", addr); } =20 -static const MemoryRegionOps pnv_core_xscom_ops =3D { - .read =3D pnv_core_xscom_read, - .write =3D pnv_core_xscom_write, +static const MemoryRegionOps pnv_core_power8_xscom_ops =3D { + .read =3D pnv_core_power8_xscom_read, + .write =3D pnv_core_power8_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + + +/* + * POWER9 core controls + */ +#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d +#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a + +static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, + unsigned int width) +{ + uint32_t offset =3D addr >> 3; + uint64_t val =3D 0; + + /* The result should be 38 C */ + switch (offset) { + case PNV_XSCOM_EX_DTS_RESULT0: + val =3D 0x26f024f023f0000ull; + break; + case PNV_XSCOM_EX_DTS_RESULT1: + val =3D 0x24f000000000000ull; + break; + case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: + case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: + val =3D 0x0; + break; + default: + qemu_log_mask(LOG_UNIMP, "Warning: reading reg=3D0x%" HWADDR_PRIx = "\n", + addr); + } + + return val; +} + +static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_= t val, + unsigned int width) +{ + uint32_t offset =3D addr >> 3; + + switch (offset) { + case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: + case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: + break; + default: + qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=3D0x%" HWADDR_PR= Ix "\n", + addr); + } +} + +static const MemoryRegionOps pnv_core_power9_xscom_ops =3D { + .read =3D pnv_core_power9_xscom_read, + .write =3D pnv_core_power9_xscom_write, .valid.min_access_size =3D 8, .valid.max_access_size =3D 8, .impl.min_access_size =3D 8, @@ -138,6 +196,7 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *= chip, Error **errp) static void pnv_core_realize(DeviceState *dev, Error **errp) { PnvCore *pc =3D PNV_CORE(OBJECT(dev)); + PnvCoreClass *pcc =3D PNV_CORE_GET_CLASS(pc); CPUCore *cc =3D CPU_CORE(OBJECT(dev)); const char *typename =3D pnv_core_cpu_typename(pc); Error *local_err =3D NULL; @@ -180,7 +239,7 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) } =20 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); - pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_op= s, + pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, pc, name, PNV_XSCOM_EX_SIZE); return; =20 @@ -222,6 +281,20 @@ static Property pnv_core_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static void pnv_core_power8_class_init(ObjectClass *oc, void *data) +{ + PnvCoreClass *pcc =3D PNV_CORE_CLASS(oc); + + pcc->xscom_ops =3D &pnv_core_power8_xscom_ops; +} + +static void pnv_core_power9_class_init(ObjectClass *oc, void *data) +{ + PnvCoreClass *pcc =3D PNV_CORE_CLASS(oc); + + pcc->xscom_ops =3D &pnv_core_power9_xscom_ops; +} + static void pnv_core_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -231,10 +304,11 @@ static void pnv_core_class_init(ObjectClass *oc, void= *data) dc->props =3D pnv_core_properties; } =20 -#define DEFINE_PNV_CORE_TYPE(cpu_model) \ +#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ { \ .parent =3D TYPE_PNV_CORE, \ .name =3D PNV_CORE_TYPE_NAME(cpu_model), \ + .class_init =3D pnv_core_##family##_class_init, \ } =20 static const TypeInfo pnv_core_infos[] =3D { @@ -246,10 +320,10 @@ static const TypeInfo pnv_core_infos[] =3D { .class_init =3D pnv_core_class_init, .abstract =3D true, }, - DEFINE_PNV_CORE_TYPE("power8e_v2.1"), - DEFINE_PNV_CORE_TYPE("power8_v2.0"), - DEFINE_PNV_CORE_TYPE("power8nvl_v1.0"), - DEFINE_PNV_CORE_TYPE("power9_v2.0"), + DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), + DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), + DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), + DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), }; =20 DEFINE_TYPES(pnv_core_infos) --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:36:00 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27MZxUZ33226842 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 7 Mar 2019 22:36:00 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D2BCBA4305; Thu, 7 Mar 2019 22:35:59 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B6B3DA4302; Thu, 7 Mar 2019 22:35:59 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:35:59 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 3C814220227; Thu, 7 Mar 2019 23:35:59 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:44 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0028-0000-0000-000003515EFD X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0029-0000-0000-0000240FD280 Message-Id: <20190307223548.20516-12-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x27MIaUf103641 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v2 11/15] ppc/pnv: POWER9 XSCOM quad support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The POWER9 processor does not support per-core frequency control. The cores are arranged in groups of four, along with their respective L2 and L3 caches, into a structure known as a Quad. The frequency must be managed at the Quad level. Provide a basic Quad model to fake the settings done by the firmware on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special BAR setting for the TIMA area of XIVE because it resides on the same address on all chips. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 4 ++ include/hw/ppc/pnv_core.h | 10 +++++ include/hw/ppc/pnv_xscom.h | 12 ++++-- hw/ppc/pnv.c | 38 ++++++++++++++++- hw/ppc/pnv_core.c | 87 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 146 insertions(+), 5 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 39888f9d52c1..e5b00d373ed2 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -26,6 +26,7 @@ #include "hw/ppc/pnv_psi.h" #include "hw/ppc/pnv_occ.h" #include "hw/ppc/pnv_xive.h" +#include "hw/ppc/pnv_core.h" =20 #define TYPE_PNV_CHIP "pnv-chip" #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) @@ -89,6 +90,9 @@ typedef struct Pnv9Chip { Pnv9Psi psi; PnvLpcController lpc; PnvOCC occ; + + uint32_t nr_quads; + PnvQuad *quads; } Pnv9Chip; =20 typedef struct PnvChipClass { diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index cbe9ad36f32c..50cdb2b35838 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -58,4 +58,14 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu) return (PnvCPUState *)cpu->machine_data; } =20 +#define TYPE_PNV_QUAD "powernv-cpu-quad" +#define PNV_QUAD(obj) \ + OBJECT_CHECK(PnvQuad, (obj), TYPE_PNV_QUAD) + +typedef struct PnvQuad { + DeviceState parent_obj; + + uint32_t id; + MemoryRegion xscom_regs; +} PnvQuad; #endif /* _PPC_PNV_CORE_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 3292459fbb78..68dfae0dfe41 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -60,10 +60,6 @@ typedef struct PnvXScomInterfaceClass { (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24)) #define PNV_XSCOM_EX_SIZE 0x100000 =20 -#define PNV_XSCOM_P9_EC_BASE(core) \ - ((uint64_t)(((core) & 0x1F) + 0x20) << 24) -#define PNV_XSCOM_P9_EC_SIZE 0x100000 - #define PNV_XSCOM_LPC_BASE 0xb0020 #define PNV_XSCOM_LPC_SIZE 0x4 =20 @@ -73,6 +69,14 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_OCC_BASE 0x0066000 #define PNV_XSCOM_OCC_SIZE 0x6000 =20 +#define PNV9_XSCOM_EC_BASE(core) \ + ((uint64_t)(((core) & 0x1F) + 0x20) << 24) +#define PNV9_XSCOM_EC_SIZE 0x100000 + +#define PNV9_XSCOM_EQ_BASE(core) \ + ((uint64_t)(((core) & 0x1C) + 0x40) << 22) +#define PNV9_XSCOM_EQ_SIZE 0x100000 + #define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE #define PNV9_XSCOM_OCC_SIZE 0x8000 =20 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 1559a733235b..e68d419203e8 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -963,6 +963,36 @@ static void pnv_chip_power9_instance_init(Object *obj) OBJECT(&chip9->psi), &error_abort); } =20 +static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) +{ + PnvChip *chip =3D PNV_CHIP(chip9); + const char *typename =3D pnv_chip_core_typename(chip); + size_t typesize =3D object_type_get_instance_size(typename); + int i; + + chip9->nr_quads =3D DIV_ROUND_UP(chip->nr_cores, 4); + chip9->quads =3D g_new0(PnvQuad, chip9->nr_quads); + + for (i =3D 0; i < chip9->nr_quads; i++) { + char eq_name[32]; + PnvQuad *eq =3D &chip9->quads[i]; + PnvCore *pnv_core =3D PNV_CORE(chip->cores + (i * 4) * typesize); + int core_id =3D CPU_CORE(pnv_core)->core_id; + + object_initialize(eq, sizeof(*eq), TYPE_PNV_QUAD); + snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); + + object_property_add_child(OBJECT(chip), eq_name, OBJECT(eq), + &error_fatal); + object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); + object_property_set_bool(OBJECT(eq), true, "realized", &error_fata= l); + object_unref(OBJECT(eq)); + + pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), + &eq->xscom_regs); + } +} + static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); @@ -977,6 +1007,12 @@ static void pnv_chip_power9_realize(DeviceState *dev,= Error **errp) return; } =20 + pnv_chip_quad_realize(chip9, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + /* XIVE interrupt controller (POWER9) */ object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), "ic-bar", &error_fatal); @@ -1135,7 +1171,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Erro= r **errp) if (!pnv_chip_is_power9(chip)) { xscom_core_base =3D PNV_XSCOM_EX_BASE(core_hwid); } else { - xscom_core_base =3D PNV_XSCOM_P9_EC_BASE(core_hwid); + xscom_core_base =3D PNV9_XSCOM_EC_BASE(core_hwid); } =20 pnv_xscom_add_subregion(chip, xscom_core_base, diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 171474e0805c..5feeed6bc463 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -327,3 +327,90 @@ static const TypeInfo pnv_core_infos[] =3D { }; =20 DEFINE_TYPES(pnv_core_infos) + +/* + * POWER9 Quads + */ + +#define P9X_EX_NCU_SPEC_BAR 0x11010 + +static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr, + unsigned int width) +{ + uint32_t offset =3D addr >> 3; + uint64_t val =3D -1; + + switch (offset) { + case P9X_EX_NCU_SPEC_BAR: + case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ + val =3D 0; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, + offset); + } + + return val; +} + +static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int width) +{ + uint32_t offset =3D addr >> 3; + + switch (offset) { + case P9X_EX_NCU_SPEC_BAR: + case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, + offset); + } +} + +static const MemoryRegionOps pnv_quad_xscom_ops =3D { + .read =3D pnv_quad_xscom_read, + .write =3D pnv_quad_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void pnv_quad_realize(DeviceState *dev, Error **errp) +{ + PnvQuad *eq =3D PNV_QUAD(dev); + char name[32]; + + snprintf(name, sizeof(name), "xscom-quad.%d", eq->id); + pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_op= s, + eq, name, PNV9_XSCOM_EQ_SIZE); +} + +static Property pnv_quad_properties[] =3D { + DEFINE_PROP_UINT32("id", PnvQuad, id, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pnv_quad_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D pnv_quad_realize; + dc->props =3D pnv_quad_properties; +} + +static const TypeInfo pnv_quad_info =3D { + .name =3D TYPE_PNV_QUAD, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(PnvQuad), + .class_init =3D pnv_quad_class_init, +}; + +static void pnv_core_register_types(void) +{ + type_register_static(&pnv_quad_info); +} + +type_init(pnv_core_register_types) --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998876084939.0837356210088; Thu, 7 Mar 2019 14:47:56 -0800 (PST) Received: from localhost ([127.0.0.1]:60689 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21nf-00006c-RO for importer@patchew.org; Thu, 07 Mar 2019 17:47:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34408) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21dU-0007j7-Jg for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:37:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h21dT-0003id-PA for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:37:08 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:46470) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h21dR-00028E-1v for qemu-devel@nongnu.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:36:01 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27Ma0Ew56623240 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 7 Mar 2019 22:36:00 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 529884C089; Thu, 7 Mar 2019 22:36:00 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3F3A34C081; Thu, 7 Mar 2019 22:36:00 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:36:00 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id AE13F220062; Thu, 7 Mar 2019 23:35:59 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:45 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-4275-0000-0000-000003185385 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-4276-0000-0000-00003826AF2F Message-Id: <20190307223548.20516-13-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=933 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x27MIapU103629 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v2 12/15] ppc/pnv: activate XSCOM tests for POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We now have enough support to let the XSCOM test run on POWER9. Signed-off-by: C=C3=A9dric Le Goater --- tests/pnv-xscom-test.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/pnv-xscom-test.c b/tests/pnv-xscom-test.c index 974f8da5b240..63d464048d53 100644 --- a/tests/pnv-xscom-test.c +++ b/tests/pnv-xscom-test.c @@ -39,7 +39,6 @@ static const PnvChip pnv_chips[] =3D { .cfam_id =3D 0x120d304980000000ull, .first_core =3D 0x1, }, -#if 0 /* POWER9 support is not ready yet */ { .chip_type =3D PNV_CHIP_POWER9, .cpu_model =3D "POWER9", @@ -47,7 +46,6 @@ static const PnvChip pnv_chips[] =3D { .cfam_id =3D 0x220d104900008000ull, .first_core =3D 0x0, }, -#endif }; =20 static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba) --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998305087683.9840452293869; Thu, 7 Mar 2019 14:38:25 -0800 (PST) Received: from localhost ([127.0.0.1]:60526 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21eW-000897-JP for importer@patchew.org; Thu, 07 Mar 2019 17:38:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:33740) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21cd-0006st-2S for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h21ca-0002GI-IX for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:14 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:38154 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h21cW-00025Q-DY for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:09 -0500 Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x27MIbjK120367 for ; Thu, 7 Mar 2019 17:36:05 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0b-001b2d01.pphosted.com with ESMTP id 2r3a3ae0bt-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 07 Mar 2019 17:36:05 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:36:01 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27Ma06A36044832 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Mar 2019 22:36:00 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C838311C071; Thu, 7 Mar 2019 22:36:00 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B510C11C070; Thu, 7 Mar 2019 22:36:00 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:36:00 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 35AC4220227; Thu, 7 Mar 2019 23:36:00 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:46 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0016-0000-0000-0000025F4199 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0017-0000-0000-000032B9D1B4 Message-Id: <20190307223548.20516-14-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0b-001b2d01.pphosted.com id x27MIbjK120367 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2 13/15] ppc/pnv: add more dummy XSCOM addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" To improve OPAL/skiboot support. We don't need to strictly model these XSCOM accesses. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv_xscom.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 46fae41f32b0..c285ef514e88 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -64,11 +64,21 @@ static uint64_t xscom_read_default(PnvChip *chip, uint3= 2_t pcba) switch (pcba) { case 0xf000f: return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id; + case 0x18002: /* ECID2 */ + return 0; + case 0x1010c00: /* PIBAM FIR */ case 0x1010c03: /* PIBAM FIR MASK */ - case 0x2020007: /* ADU stuff */ - case 0x2020009: /* ADU stuff */ - case 0x202000f: /* ADU stuff */ + + /* P9 xscom reset */ + case 0x0090018: /* Receive status reg */ + case 0x0090012: /* log register */ + case 0x0090013: /* error register */ + + /* P8 xscom reset */ + case 0x2020007: /* ADU stuff, log register */ + case 0x2020009: /* ADU stuff, error register */ + case 0x202000f: /* ADU stuff, receive status register*/ return 0; case 0x2013f00: /* PBA stuff */ case 0x2013f01: /* PBA stuff */ @@ -100,9 +110,20 @@ static bool xscom_write_default(PnvChip *chip, uint32_= t pcba, uint64_t val) case 0x1010c03: /* PIBAM FIR MASK */ case 0x1010c04: /* PIBAM FIR MASK */ case 0x1010c05: /* PIBAM FIR MASK */ - case 0x2020007: /* ADU stuff */ - case 0x2020009: /* ADU stuff */ - case 0x202000f: /* ADU stuff */ + /* P9 xscom reset */ + case 0x0090018: /* Receive status reg */ + case 0x0090012: /* log register */ + case 0x0090013: /* error register */ + + /* P8 xscom reset */ + case 0x2020007: /* ADU stuff, log register */ + case 0x2020009: /* ADU stuff, error register */ + case 0x202000f: /* ADU stuff, receive status register*/ + + case 0x2013028: /* CAPP stuff */ + case 0x201302a: /* CAPP stuff */ + case 0x2013801: /* CAPP stuff */ + case 0x2013802: /* CAPP stuff */ return true; default: return false; --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998889498396.63071879188465; Thu, 7 Mar 2019 14:48:09 -0800 (PST) Received: from localhost ([127.0.0.1]:60691 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21o2-0000Rb-Ev for importer@patchew.org; Thu, 07 Mar 2019 17:48:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34335) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21dR-0007di-1H for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:37:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h21dQ-0003WO-2w for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:37:04 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:38210 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h21dO-00029x-NO for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:37:02 -0500 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x27MIas4071012 for ; Thu, 7 Mar 2019 17:36:07 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2r3b5qtm1r-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 07 Mar 2019 17:36:06 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:36:02 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27Ma19f54329438 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Mar 2019 22:36:01 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5540011C075; Thu, 7 Mar 2019 22:36:01 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 405BB11C07A; Thu, 7 Mar 2019 22:36:01 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:36:01 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id ABD58220062; Thu, 7 Mar 2019 23:36:00 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:47 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0016-0000-0000-0000025F419B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0017-0000-0000-000032B9D1B5 Message-Id: <20190307223548.20516-15-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x27MIas4071012 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2 14/15] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Activate only stop0 and stop1 levels. We should not need more levels when under QEMU. Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index e68d419203e8..8be4d4cbf785 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -438,6 +438,16 @@ static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) &args); } =20 +static void pnv_dt_power_mgt(void *fdt) +{ + int off; + + off =3D fdt_add_subnode(fdt, 0, "ibm,opal"); + off =3D fdt_add_subnode(fdt, off, "power-mgt"); + + _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)= ); +} + static void *pnv_dt_create(MachineState *machine) { const char plat_compat[] =3D "qemu,powernv\0ibm,powernv"; @@ -493,6 +503,11 @@ static void *pnv_dt_create(MachineState *machine) pnv_dt_bmc_sensors(pnv->bmc, fdt); } =20 + /* Create an extra node for power management on Power9 */ + if (pnv_is_power9(pnv)) { + pnv_dt_power_mgt(fdt); + } + return fdt; } =20 --=20 2.20.1 From nobody Sun Nov 9 20:24:19 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551998555027686.0963156794456; Thu, 7 Mar 2019 14:42:35 -0800 (PST) Received: from localhost ([127.0.0.1]:60595 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21ie-0003U0-08 for importer@patchew.org; Thu, 07 Mar 2019 17:42:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34121) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h21d4-0007Jh-Vb for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h21d2-000321-Mq for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:42 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:54520 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h21cy-00028h-0l for qemu-devel@nongnu.org; Thu, 07 Mar 2019 17:36:36 -0500 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x27MZdot039259 for ; Thu, 7 Mar 2019 17:36:06 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0b-001b2d01.pphosted.com with ESMTP id 2r3c7u80bf-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 07 Mar 2019 17:36:06 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Mar 2019 22:36:02 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x27Ma1xo54329442 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Mar 2019 22:36:02 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BBE6D11C074; Thu, 7 Mar 2019 22:36:01 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B19FC11C079; Thu, 7 Mar 2019 22:36:01 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 7 Mar 2019 22:36:01 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-48-25.uk.ibm.com [9.145.48.25]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 356A1220227; Thu, 7 Mar 2019 23:36:01 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 7 Mar 2019 23:35:48 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307223548.20516-1-clg@kaod.org> References: <20190307223548.20516-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030722-0008-0000-0000-000002C9FB85 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030722-0009-0000-0000-000022360B30 Message-Id: <20190307223548.20516-16-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-07_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=788 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903070147 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0b-001b2d01.pphosted.com id x27MZdot039259 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v2 15/15] target/ppc: add HV support for POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We now have enough support to boot a PowerNV machine with a POWER9 processor. Allow HV mode on POWER9. Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/translate_init.inc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index af70a3b78c9a..0bd555eb1913 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8895,7 +8895,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | - PPC_64B | PPC_64BX | PPC_ALTIVEC | + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD | PPC_CILDST; @@ -8907,6 +8907,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; pcc->msr_mask =3D (1ull << MSR_SF) | + (1ull << MSR_SHV) | (1ull << MSR_TM) | (1ull << MSR_VR) | (1ull << MSR_VSX) | --=20 2.20.1