From nobody Sat Nov 8 06:05:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551935278024274.04628411788394; Wed, 6 Mar 2019 21:07:58 -0800 (PST) Received: from localhost ([127.0.0.1]:45374 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1lG7-0008Ov-1F for importer@patchew.org; Thu, 07 Mar 2019 00:07:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1lEJ-0007Ov-Bw for qemu-devel@nongnu.org; Thu, 07 Mar 2019 00:06:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1lEH-0005IF-Ed for qemu-devel@nongnu.org; Thu, 07 Mar 2019 00:06:03 -0500 Received: from ozlabs.ru ([107.173.13.209]:43880) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1lEF-0005GF-Db; Thu, 07 Mar 2019 00:06:01 -0500 Received: from fstn1-p1.ozlabs.ibm.com (localhost [IPv6:::1]) by ozlabs.ru (Postfix) with ESMTP id 12F59AE80049; Thu, 7 Mar 2019 00:05:25 -0500 (EST) From: Alexey Kardashevskiy To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 16:05:16 +1100 Message-Id: <20190307050518.64968-2-aik@ozlabs.ru> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190307050518.64968-1-aik@ozlabs.ru> References: <20190307050518.64968-1-aik@ozlabs.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 107.173.13.209 Subject: [Qemu-devel] [PATCH qemu v4 1/3] spapr_iommu: Do not replay mappings from just created DMA window X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Williamson , Jose Ricardo Ziviani , Alexey Kardashevskiy , Daniel Henrique Barboza , Gavin Shan , Sam Bobroff , Piotr Jaroszynski , qemu-ppc@nongnu.org, =?UTF-8?q?Leonardo=20Augusto=20Guimar=C3=A3es=20Garcia?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" On sPAPR vfio_listener_region_add() is called in 2 situations: 1. a new listener is registered from vfio_connect_container(); 2. a new IOMMU Memory Region is added from rtas_ibm_create_pe_dma_window(). In both cases vfio_listener_region_add() calls memory_region_iommu_replay() to notify newly registered IOMMU notifiers about existing mappings which is totally desirable for case 1. However for case 2 it is nothing but noop as the window has just been created and has no valid mappings so replaying those does not do anything. It is barely noticeable with usual guests but if the window happens to be really big, such no-op replay might take minutes and trigger RCU stall warnings in the guest. For example, a upcoming GPU RAM memory region mapped at 64TiB (right after SPAPR_PCI_LIMIT) causes a 64bit DMA window to be at least 128TiB which is (128<<40)/0x10000=3D2.147.483.648 TCEs to replay. This mitigates the problem by adding an "skipping_replay" flag to sPAPRTCETable and defining sPAPR own IOMMU MR replay() hook which does exactly the same thing as the generic one except it returns early if @skipping_replay=3D=3Dtrue. Another way of fixing this would be delaying replay till the very first H_PUT_TCE but this does not work if in-kernel H_PUT_TCE handler is enabled (a likely case). When "ibm,create-pe-dma-window" is complete, the guest will map only required regions of the huge DMA window. Signed-off-by: Alexey Kardashevskiy --- Changes: v4: * more explaining in the commit log and comments --- include/hw/ppc/spapr.h | 1 + hw/ppc/spapr_iommu.c | 31 +++++++++++++++++++++++++++++++ hw/ppc/spapr_rtas_ddw.c | 10 ++++++++++ 3 files changed, 42 insertions(+) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index ff1bd6061540..2b368e6677c5 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -723,6 +723,7 @@ struct sPAPRTCETable { uint64_t *mig_table; bool bypass; bool need_vfio; + bool skipping_replay; int fd; MemoryRegion root; IOMMUMemoryRegion iommu; diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index 37e98f93214d..8f231799b29b 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -141,6 +141,36 @@ static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMe= moryRegion *iommu, return ret; } =20 +static void spapr_tce_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) +{ + MemoryRegion *mr =3D MEMORY_REGION(iommu_mr); + IOMMUMemoryRegionClass *imrc =3D IOMMU_MEMORY_REGION_GET_CLASS(iommu_m= r); + hwaddr addr, granularity; + IOMMUTLBEntry iotlb; + sPAPRTCETable *tcet =3D container_of(iommu_mr, sPAPRTCETable, iommu); + + if (tcet->skipping_replay) { + return; + } + + granularity =3D memory_region_iommu_get_min_page_size(iommu_mr); + + for (addr =3D 0; addr < memory_region_size(mr); addr +=3D granularity)= { + iotlb =3D imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx= ); + if (iotlb.perm !=3D IOMMU_NONE) { + n->notify(n, &iotlb); + } + + /* + * if (2^64 - MR size) < granularity, it's possible to get an + * infinite loop here. This should catch such a wraparound. + */ + if ((addr + granularity) < addr) { + break; + } + } +} + static int spapr_tce_table_pre_save(void *opaque) { sPAPRTCETable *tcet =3D SPAPR_TCE_TABLE(opaque); @@ -659,6 +689,7 @@ static void spapr_iommu_memory_region_class_init(Object= Class *klass, void *data) IOMMUMemoryRegionClass *imrc =3D IOMMU_MEMORY_REGION_CLASS(klass); =20 imrc->translate =3D spapr_tce_translate_iommu; + imrc->replay =3D spapr_tce_replay; imrc->get_min_page_size =3D spapr_tce_get_min_page_size; imrc->notify_flag_changed =3D spapr_tce_notify_flag_changed; imrc->get_attr =3D spapr_tce_get_attr; diff --git a/hw/ppc/spapr_rtas_ddw.c b/hw/ppc/spapr_rtas_ddw.c index cb8a4103592e..cc9d1f5c1cc8 100644 --- a/hw/ppc/spapr_rtas_ddw.c +++ b/hw/ppc/spapr_rtas_ddw.c @@ -171,8 +171,18 @@ static void rtas_ibm_create_pe_dma_window(PowerPCCPU *= cpu, } =20 win_addr =3D (windows =3D=3D 0) ? sphb->dma_win_addr : sphb->dma64_win= _addr; + /* + * We have just created a window, we know for the fact that it is empt= y, + * use a hack to avoid iterating over the table as it is quite possible + * to have billions of TCEs, all empty. + * Note that we cannot delay this to the first H_PUT_TCE as this hcall= is + * mostly likely to be handled in KVM so QEMU just does not know if it + * happened. + */ + tcet->skipping_replay =3D true; spapr_tce_table_enable(tcet, page_shift, win_addr, 1ULL << (window_shift - page_shift)); + tcet->skipping_replay =3D false; if (!tcet->nb_table) { goto hw_error_exit; } --=20 2.17.1 From nobody Sat Nov 8 06:05:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551935287367666.2372035121145; Wed, 6 Mar 2019 21:08:07 -0800 (PST) Received: from localhost ([127.0.0.1]:45376 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1lG7-0008PV-6c for importer@patchew.org; Thu, 07 Mar 2019 00:07:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40609) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1lEN-0007QG-5Y for qemu-devel@nongnu.org; Thu, 07 Mar 2019 00:06:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1lEL-0005L5-AJ for qemu-devel@nongnu.org; Thu, 07 Mar 2019 00:06:06 -0500 Received: from ozlabs.ru ([107.173.13.209]:43884) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1lEJ-0005IV-Ce; Thu, 07 Mar 2019 00:06:05 -0500 Received: from fstn1-p1.ozlabs.ibm.com (localhost [IPv6:::1]) by ozlabs.ru (Postfix) with ESMTP id 47173AE80110; Thu, 7 Mar 2019 00:05:29 -0500 (EST) From: Alexey Kardashevskiy To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 16:05:17 +1100 Message-Id: <20190307050518.64968-3-aik@ozlabs.ru> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190307050518.64968-1-aik@ozlabs.ru> References: <20190307050518.64968-1-aik@ozlabs.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 107.173.13.209 Subject: [Qemu-devel] [PATCH qemu v4 2/3] vfio: Make vfio_get_region_info_cap public X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Williamson , Jose Ricardo Ziviani , Alexey Kardashevskiy , Daniel Henrique Barboza , Gavin Shan , Sam Bobroff , Piotr Jaroszynski , qemu-ppc@nongnu.org, =?UTF-8?q?Leonardo=20Augusto=20Guimar=C3=A3es=20Garcia?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This makes vfio_get_region_info_cap() to be used in quirks. Signed-off-by: Alexey Kardashevskiy Acked-by: Alex Williamson --- include/hw/vfio/vfio-common.h | 2 ++ hw/vfio/common.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h index 7624c9f511c4..fbf0966af484 100644 --- a/include/hw/vfio/vfio-common.h +++ b/include/hw/vfio/vfio-common.h @@ -189,6 +189,8 @@ int vfio_get_region_info(VFIODevice *vbasedev, int inde= x, int vfio_get_dev_region_info(VFIODevice *vbasedev, uint32_t type, uint32_t subtype, struct vfio_region_info **i= nfo); bool vfio_has_region_cap(VFIODevice *vbasedev, int region, uint16_t cap_ty= pe); +struct vfio_info_cap_header * +vfio_get_region_info_cap(struct vfio_region_info *info, uint16_t id); #endif extern const MemoryListener vfio_prereg_listener; =20 diff --git a/hw/vfio/common.c b/hw/vfio/common.c index df2b4721bffb..4374cc6176a2 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -729,7 +729,7 @@ static void vfio_listener_release(VFIOContainer *contai= ner) } } =20 -static struct vfio_info_cap_header * +struct vfio_info_cap_header * vfio_get_region_info_cap(struct vfio_region_info *info, uint16_t id) { struct vfio_info_cap_header *hdr; --=20 2.17.1 From nobody Sat Nov 8 06:05:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551935263083946.6830002370289; Wed, 6 Mar 2019 21:07:43 -0800 (PST) Received: from localhost ([127.0.0.1]:45372 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1lFm-00083Y-4Z for importer@patchew.org; Thu, 07 Mar 2019 00:07:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40489) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1lDw-0007Ck-Sq for qemu-devel@nongnu.org; Thu, 07 Mar 2019 00:05:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1lDt-00059Y-No for qemu-devel@nongnu.org; Thu, 07 Mar 2019 00:05:40 -0500 Received: from ozlabs.ru ([107.173.13.209]:43841) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1lDt-00058w-AT; Thu, 07 Mar 2019 00:05:37 -0500 Received: from fstn1-p1.ozlabs.ibm.com (localhost [IPv6:::1]) by ozlabs.ru (Postfix) with ESMTP id 43E8BAE801D5; Thu, 7 Mar 2019 00:05:32 -0500 (EST) From: Alexey Kardashevskiy To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 16:05:18 +1100 Message-Id: <20190307050518.64968-4-aik@ozlabs.ru> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190307050518.64968-1-aik@ozlabs.ru> References: <20190307050518.64968-1-aik@ozlabs.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 107.173.13.209 Subject: [Qemu-devel] [PATCH qemu v4 3/3] spapr: Support NVIDIA V100 GPU with NVLink2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Williamson , Jose Ricardo Ziviani , Alexey Kardashevskiy , Daniel Henrique Barboza , Gavin Shan , Sam Bobroff , Piotr Jaroszynski , qemu-ppc@nongnu.org, =?UTF-8?q?Leonardo=20Augusto=20Guimar=C3=A3es=20Garcia?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" NVIDIA V100 GPUs have on-board RAM which is mapped into the host memory space and accessible as normal RAM via an NVLink bus. The VFIO-PCI driver implements special regions for such GPUs and emulates an NVLink bridge. NVLink2-enabled POWER9 CPUs also provide address translation services which includes an ATS shootdown (ATSD) register exported via the NVLink bridge device. This adds a quirk to VFIO to map the GPU memory and create an MR; the new MR is stored in a PCI device as a QOM link. The sPAPR PCI uses this to get the MR and map it to the system address space. Another quirk does the same for ATSD. This adds additional steps to sPAPR PHB setup: 1. Search for specific GPUs and NPUs, collect findings in sPAPRPHBState::nvgpus, manage system address space mappings; 2. Add device-specific properties such as "ibm,npu", "ibm,gpu", "memory-block", "link-speed" to advertise the NVLink2 function to the guest; 3. Add "mmio-atsd" to vPHB to advertise the ATSD capability; 4. Add new memory blocks (with extra "linux,memory-usable" to prevent the guest OS from accessing the new memory until it is onlined) and npuphb# nodes representing an NPU unit for every vPHB as the GPU driver uses it for link discovery. This allocates space for GPU RAM and ATSD like we do for MMIOs by adding 2 new parameters to the phb_placement() hook. Older machine types set these to zero. This puts new memory nodes in a separate NUMA node to replicate the host system setup as the GPU driver relies on this. This adds requirement similar to EEH - one IOMMU group per vPHB. The reason for this is that ATSD registers belong to a physical NPU so they cannot invalidate translations on GPUs attached to another NPU. It is guaranteed by the host platform as it does not mix NVLink bridges or GPUs from different NPU in the same IOMMU group. If more than one IOMMU group is detected on a vPHB, this disables ATSD support for that vPHB and prints a warning. Signed-off-by: Alexey Kardashevskiy --- Changes: v4: * fixed ATSD placement * fixed spapr_phb_unrealize() to do nvgpu cleanup * replaced warn_report() with Error* v3: * moved GPU RAM above PCI MMIO limit * renamed QOM property to nvlink2-tgt * moved nvlink2 code to its own file --- The example command line for redbud system: pbuild/qemu-aiku1804le-ppc64/ppc64-softmmu/qemu-system-ppc64 \ -nodefaults \ -chardev stdio,id=3DSTDIO0,signal=3Doff,mux=3Don \ -device spapr-vty,id=3Dsvty0,reg=3D0x71000110,chardev=3DSTDIO0 \ -mon id=3DMON0,chardev=3DSTDIO0,mode=3Dreadline -nographic -vga none \ -enable-kvm -m 384G \ -chardev socket,id=3DSOCKET0,server,nowait,host=3Dlocalhost,port=3D40000 \ -mon chardev=3DSOCKET0,mode=3Dcontrol \ -smp 80,sockets=3D1,threads=3D4 \ -netdev "tap,id=3DTAP0,helper=3D/home/aik/qemu-bridge-helper --br=3Dbr0" \ -device "virtio-net-pci,id=3Dvnet0,mac=3D52:54:00:12:34:56,netdev=3DTAP0" \ img/vdisk0.img \ -device "vfio-pci,id=3Dvfio0004_04_00_0,host=3D0004:04:00.0" \ -device "vfio-pci,id=3Dvfio0006_00_00_0,host=3D0006:00:00.0" \ -device "vfio-pci,id=3Dvfio0006_00_00_1,host=3D0006:00:00.1" \ -device "vfio-pci,id=3Dvfio0006_00_00_2,host=3D0006:00:00.2" \ -device "vfio-pci,id=3Dvfio0004_05_00_0,host=3D0004:05:00.0" \ -device "vfio-pci,id=3Dvfio0006_00_01_0,host=3D0006:00:01.0" \ -device "vfio-pci,id=3Dvfio0006_00_01_1,host=3D0006:00:01.1" \ -device "vfio-pci,id=3Dvfio0006_00_01_2,host=3D0006:00:01.2" \ -device spapr-pci-host-bridge,id=3Dphb1,index=3D1 \ -device "vfio-pci,id=3Dvfio0035_03_00_0,host=3D0035:03:00.0" \ -device "vfio-pci,id=3Dvfio0007_00_00_0,host=3D0007:00:00.0" \ -device "vfio-pci,id=3Dvfio0007_00_00_1,host=3D0007:00:00.1" \ -device "vfio-pci,id=3Dvfio0007_00_00_2,host=3D0007:00:00.2" \ -device "vfio-pci,id=3Dvfio0035_04_00_0,host=3D0035:04:00.0" \ -device "vfio-pci,id=3Dvfio0007_00_01_0,host=3D0007:00:01.0" \ -device "vfio-pci,id=3Dvfio0007_00_01_1,host=3D0007:00:01.1" \ -device "vfio-pci,id=3Dvfio0007_00_01_2,host=3D0007:00:01.2" -snapshot \ -machine pseries \ -L /home/aik/t/qemu-ppc64-bios/ -d guest_errors Note that QEMU attaches PCI devices to the last added vPHB so first 8 devices - 4:04:00.0 till 6:00:01.2 - go to the default vPHB, and 35:03:00.0..7:00:01.2 to the vPHB with id=3Dphb1. --- hw/ppc/Makefile.objs | 2 +- hw/vfio/pci.h | 2 + include/hw/pci-host/spapr.h | 45 ++++ include/hw/ppc/spapr.h | 3 +- hw/ppc/spapr.c | 29 ++- hw/ppc/spapr_pci.c | 19 ++ hw/ppc/spapr_pci_nvlink2.c | 441 ++++++++++++++++++++++++++++++++++++ hw/vfio/pci-quirks.c | 120 ++++++++++ hw/vfio/pci.c | 14 ++ hw/vfio/trace-events | 4 + 10 files changed, 674 insertions(+), 5 deletions(-) create mode 100644 hw/ppc/spapr_pci_nvlink2.c diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs index 1111b218a048..636e717f207c 100644 --- a/hw/ppc/Makefile.objs +++ b/hw/ppc/Makefile.objs @@ -9,7 +9,7 @@ obj-$(CONFIG_SPAPR_RNG) +=3D spapr_rng.o # IBM PowerNV obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.= o pnv_occ.o pnv_bmc.o ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy) -obj-y +=3D spapr_pci_vfio.o +obj-y +=3D spapr_pci_vfio.o spapr_pci_nvlink2.o endif obj-$(CONFIG_PSERIES) +=3D spapr_rtas_ddw.o # PowerPC 4xx boards diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index b1ae4c07549a..706c30443617 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -194,6 +194,8 @@ int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp= ); int vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev, struct vfio_region_info *info, Error **errp); +int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp); +int vfio_pci_nvlink2_init(VFIOPCIDevice *vdev, Error **errp); =20 void vfio_display_reset(VFIOPCIDevice *vdev); int vfio_display_probe(VFIOPCIDevice *vdev, Error **errp); diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index ab0e3a0a6f72..912fb36807ee 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -87,6 +87,9 @@ struct sPAPRPHBState { uint32_t mig_liobn; hwaddr mig_mem_win_addr, mig_mem_win_size; hwaddr mig_io_win_addr, mig_io_win_size; + hwaddr nv2_gpa_win_addr; + hwaddr nv2_atsd_win_addr; + struct spapr_phb_pci_nvgpu_config *nvgpus; }; =20 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL @@ -105,6 +108,22 @@ struct sPAPRPHBState { =20 #define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL =20 +#define SPAPR_PCI_NV2RAM64_WIN_BASE SPAPR_PCI_LIMIT +#define SPAPR_PCI_NV2RAM64_WIN_SIZE (2 * TiB) /* For up to 6 GPUs 256GB e= ach */ + +/* Max number of these GPUsper a physical box */ +#define NVGPU_MAX_NUM 6 +/* Max number of NVLinks per GPU in any physical box */ +#define NVGPU_MAX_LINKS 3 + +/* + * GPU RAM starts at 64TiB so huge DMA window to cover it all ends at 128T= iB + * which is enough. We do not need DMA for ATSD so we put them at 128TiB. + */ +#define SPAPR_PCI_NV2ATSD_WIN_BASE (128 * TiB) +#define SPAPR_PCI_NV2ATSD_WIN_SIZE (NVGPU_MAX_NUM * NVGPU_MAX_LINKS * \ + 64 * KiB) + static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int p= in) { sPAPRMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); @@ -135,6 +154,13 @@ int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, = int *state); int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option); int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb); void spapr_phb_vfio_reset(DeviceState *qdev); +void spapr_phb_nvgpu_setup(sPAPRPHBState *sphb, Error **errp); +void spapr_phb_nvgpu_free(sPAPRPHBState *sphb); +void spapr_phb_nvgpu_populate_dt(sPAPRPHBState *sphb, void *fdt, int bus_o= ff, + Error **errp); +void spapr_phb_nvgpu_ram_populate_dt(sPAPRPHBState *sphb, void *fdt); +void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int off= set, + sPAPRPHBState *sphb); #else static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb) { @@ -161,6 +187,25 @@ static inline int spapr_phb_vfio_eeh_configure(sPAPRPH= BState *sphb) static inline void spapr_phb_vfio_reset(DeviceState *qdev) { } +static inline void spapr_phb_nvgpu_setup(sPAPRPHBState *sphb, Error **errp) +{ +} +static inline void spapr_phb_nvgpu_free(sPAPRPHBState *sphb) +{ +} +static inline void spapr_phb_nvgpu_populate_dt(sPAPRPHBState *sphb, void *= fdt, + int bus_off, Error **errp) +{ +} +static inline void spapr_phb_nvgpu_ram_populate_dt(sPAPRPHBState *sphb, + void *fdt) +{ +} +static inline void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void= *fdt, + int offset, + sPAPRPHBState *sphb) +{ +} #endif =20 void spapr_phb_dma_reset(sPAPRPHBState *sphb); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 2b368e6677c5..2037a865fa1f 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -122,7 +122,8 @@ struct sPAPRMachineClass { void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio,=20 hwaddr *mmio32, hwaddr *mmio64, - unsigned n_dma, uint32_t *liobns, Error **errp); + unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, + hwaddr *nv2atsd, Error **errp); sPAPRResizeHPT resize_hpt_default; sPAPRCapabilities default_caps; sPAPRIrq *irq; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 6063496932c2..7cd16c538a29 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3930,7 +3930,9 @@ static void spapr_phb_pre_plug(HotplugHandler *hotplu= g_dev, DeviceState *dev, smc->phb_placement(spapr, sphb->index, &sphb->buid, &sphb->io_win_addr, &sphb->mem_win_addr, &sphb->mem64_win_addr, - windows_supported, sphb->dma_liobn, errp); + windows_supported, sphb->dma_liobn, + &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, + errp); } =20 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, @@ -4130,7 +4132,8 @@ static const CPUArchIdList *spapr_possible_cpu_arch_i= ds(MachineState *machine) static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio, hwaddr *mmio32, hwaddr *mmio64, - unsigned n_dma, uint32_t *liobns, Error **= errp) + unsigned n_dma, uint32_t *liobns, + hwaddr *nv2gpa, hwaddr *nv2atsd, Error **e= rrp) { /* * New-style PHB window placement. @@ -4175,6 +4178,9 @@ static void spapr_phb_placement(sPAPRMachineState *sp= apr, uint32_t index, *pio =3D SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; *mmio32 =3D SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; *mmio64 =3D SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; + + *nv2gpa =3D SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_W= IN_SIZE; + *nv2atsd =3D SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WI= N_SIZE; } =20 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) @@ -4379,6 +4385,18 @@ DEFINE_SPAPR_MACHINE(4_0, "4.0", true); /* * pseries-3.1 */ +static void phb_placement_3_1(sPAPRMachineState *spapr, uint32_t index, + uint64_t *buid, hwaddr *pio, + hwaddr *mmio32, hwaddr *mmio64, + unsigned n_dma, uint32_t *liobns, + hwaddr *nv2gpa, hwaddr *nv2atsd, Error **err= p) +{ + spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, li= obns, + nv2gpa, nv2atsd, errp); + *nv2gpa =3D 0; + *nv2atsd =3D 0; +} + static void spapr_machine_3_1_class_options(MachineClass *mc) { sPAPRMachineClass *smc =3D SPAPR_MACHINE_CLASS(mc); @@ -4398,6 +4416,7 @@ static void spapr_machine_3_1_class_options(MachineCl= ass *mc) smc->default_caps.caps[SPAPR_CAP_SBBC] =3D SPAPR_CAP_BROKEN; smc->default_caps.caps[SPAPR_CAP_IBS] =3D SPAPR_CAP_BROKEN; smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] =3D SPAPR_CAP_OFF; + smc->phb_placement =3D phb_placement_3_1; } =20 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); @@ -4529,7 +4548,8 @@ DEFINE_SPAPR_MACHINE(2_8, "2.8", false); static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio, hwaddr *mmio32, hwaddr *mmio64, - unsigned n_dma, uint32_t *liobns, Error **er= rp) + unsigned n_dma, uint32_t *liobns, + hwaddr *nv2gpa, hwaddr *nv2atsd, Error **err= p) { /* Legacy PHB placement for pseries-2.7 and earlier machine types */ const uint64_t base_buid =3D 0x800000020000000ULL; @@ -4573,6 +4593,9 @@ static void phb_placement_2_7(sPAPRMachineState *spap= r, uint32_t index, * fallback behaviour of automatically splitting a large "32-bit" * window into contiguous 32-bit and 64-bit windows */ + + *nv2gpa =3D 0; + *nv2atsd =3D 0; } =20 static void spapr_machine_2_7_class_options(MachineClass *mc) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 06a5ffd28184..09d283e97629 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1355,6 +1355,8 @@ static void spapr_populate_pci_child_dt(PCIDevice *de= v, void *fdt, int offset, if (sphb->pcie_ecs && pci_is_express(dev)) { _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x= 1)); } + + spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb); } =20 /* create OF node for pci device and required OF DT properties */ @@ -1588,6 +1590,8 @@ static void spapr_phb_unrealize(DeviceState *dev, Err= or **errp) int i; const unsigned windows_supported =3D spapr_phb_windows_supported(sphb); =20 + spapr_phb_nvgpu_free(sphb); + if (sphb->msi) { g_hash_table_unref(sphb->msi); sphb->msi =3D NULL; @@ -1876,8 +1880,14 @@ void spapr_phb_dma_reset(sPAPRPHBState *sphb) static void spapr_phb_reset(DeviceState *qdev) { sPAPRPHBState *sphb =3D SPAPR_PCI_HOST_BRIDGE(qdev); + Error *errp =3D NULL; =20 spapr_phb_dma_reset(sphb); + spapr_phb_nvgpu_free(sphb); + spapr_phb_nvgpu_setup(sphb, &errp); + if (errp) { + error_report_err(errp); + } =20 /* Reset the IOMMU state */ object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); @@ -1910,6 +1920,8 @@ static Property spapr_phb_properties[] =3D { pre_2_8_migration, false), DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState, pcie_ecs, true), + DEFINE_PROP_UINT64("gpa", sPAPRPHBState, nv2_gpa_win_addr, 0), + DEFINE_PROP_UINT64("atsd", sPAPRPHBState, nv2_atsd_win_addr, 0), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -2190,6 +2202,7 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_= t intc_phandle, void *fdt, PCIBus *bus =3D PCI_HOST_BRIDGE(phb)->bus; sPAPRFDT s_fdt; sPAPRDRConnector *drc; + Error *errp =3D NULL; =20 /* Start populating the FDT */ nodename =3D g_strdup_printf("pci@%" PRIx64, phb->buid); @@ -2282,6 +2295,12 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32= _t intc_phandle, void *fdt, return ret; } =20 + spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &errp); + if (errp) { + error_report_err(errp); + } + spapr_phb_nvgpu_ram_populate_dt(phb, fdt); + return 0; } =20 diff --git a/hw/ppc/spapr_pci_nvlink2.c b/hw/ppc/spapr_pci_nvlink2.c new file mode 100644 index 000000000000..902cf4a39f80 --- /dev/null +++ b/hw/ppc/spapr_pci_nvlink2.c @@ -0,0 +1,441 @@ +/* + * QEMU sPAPR PCI for NVLink2 pass through + * + * Copyright (c) 2019 Alexey Kardashevskiy, IBM Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/pci/pci.h" +#include "hw/pci-host/spapr.h" +#include "qemu/error-report.h" +#include "hw/ppc/fdt.h" +#include "hw/pci/pci_bridge.h" + +#define PHANDLE_PCIDEV(phb, pdev) (0x12000000 | \ + (((phb)->index) << 16) | ((pdev)->dev= fn)) +#define PHANDLE_GPURAM(phb, n) (0x110000FF | ((n) << 8) | \ + (((phb)->index) << 16)) +/* NVLink2 wants a separate NUMA node for its RAM */ +#define GPURAM_ASSOCIATIVITY(phb, n) (255 - ((phb)->index * 3 + (n))) +#define PHANDLE_NVLINK(phb, gn, nn) (0x00130000 | (((phb)->index) << 8) |= \ + ((gn) << 4) | (nn)) + +struct spapr_phb_pci_nvgpu_config { + uint64_t nv2_ram_current; + uint64_t nv2_atsd_current; + int num; /* number of non empty (i.e. tgt!=3D0) entries in slots[] */ + struct spapr_phb_pci_nvgpu_slot { + uint64_t tgt; + uint64_t gpa; + PCIDevice *gpdev; + int linknum; + struct { + uint64_t atsd_gpa; + PCIDevice *npdev; + uint32_t link_speed; + } links[NVGPU_MAX_LINKS]; + } slots[NVGPU_MAX_NUM]; + Error *errp; +}; + +static struct spapr_phb_pci_nvgpu_slot * +spapr_nvgpu_get_slot(struct spapr_phb_pci_nvgpu_config *nvgpus, + uint64_t tgt) +{ + int i; + + /* Search for partially collected "slot" */ + for (i =3D 0; i < nvgpus->num; ++i) { + if (nvgpus->slots[i].tgt =3D=3D tgt) { + return &nvgpus->slots[i]; + } + } + + if (nvgpus->num =3D=3D ARRAY_SIZE(nvgpus->slots)) { + return NULL; + } + + i =3D nvgpus->num; + nvgpus->slots[i].tgt =3D tgt; + ++nvgpus->num; + + return &nvgpus->slots[i]; +} + +static void spapr_pci_collect_nvgpu(struct spapr_phb_pci_nvgpu_config *nvg= pus, + PCIDevice *pdev, uint64_t tgt, + MemoryRegion *mr, Error **errp) +{ + struct spapr_phb_pci_nvgpu_slot *nvslot =3D spapr_nvgpu_get_slot(nvgpu= s, tgt); + + if (!nvslot) { + error_setg(errp, "Found too many NVLink bridges per GPU"); + return; + } + g_assert(!nvslot->gpdev); + nvslot->gpdev =3D pdev; + + nvslot->gpa =3D nvgpus->nv2_ram_current; + nvgpus->nv2_ram_current +=3D memory_region_size(mr); +} + +static void spapr_pci_collect_nvnpu(struct spapr_phb_pci_nvgpu_config *nvg= pus, + PCIDevice *pdev, uint64_t tgt, + MemoryRegion *mr, Error **errp) +{ + struct spapr_phb_pci_nvgpu_slot *nvslot =3D spapr_nvgpu_get_slot(nvgpu= s, tgt); + int j; + + if (!nvslot) { + error_setg(errp, "Found too many NVLink bridges per GPU"); + return; + } + + j =3D nvslot->linknum; + if (j =3D=3D ARRAY_SIZE(nvslot->links)) { + error_setg(errp, "Found too many NVLink2 bridges"); + return; + } + ++nvslot->linknum; + + g_assert(!nvslot->links[j].npdev); + nvslot->links[j].npdev =3D pdev; + nvslot->links[j].atsd_gpa =3D nvgpus->nv2_atsd_current; + nvgpus->nv2_atsd_current +=3D memory_region_size(mr); + nvslot->links[j].link_speed =3D + object_property_get_uint(OBJECT(pdev), "nvlink2-link-speed", NULL); +} + +static void spapr_phb_pci_collect_nvgpu(PCIBus *bus, PCIDevice *pdev, + void *opaque) +{ + PCIBus *sec_bus; + Object *po =3D OBJECT(pdev); + uint64_t tgt =3D object_property_get_uint(po, "nvlink2-tgt", NULL); + + if (tgt) { + Error *local_err =3D NULL; + struct spapr_phb_pci_nvgpu_config *nvgpus =3D opaque; + Object *mr_gpu =3D object_property_get_link(po, "nvlink2-mr[0]", N= ULL); + Object *mr_npu =3D object_property_get_link(po, "nvlink2-atsd-mr[0= ]", + NULL); + + g_assert(mr_gpu || mr_npu); + if (mr_gpu) { + spapr_pci_collect_nvgpu(nvgpus, pdev, tgt, MEMORY_REGION(mr_gp= u), + &local_err); + } else { + spapr_pci_collect_nvnpu(nvgpus, pdev, tgt, MEMORY_REGION(mr_np= u), + &local_err); + } + error_propagate(&nvgpus->errp, local_err); + } + if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=3D + PCI_HEADER_TYPE_BRIDGE)) { + return; + } + + sec_bus =3D pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); + if (!sec_bus) { + return; + } + + pci_for_each_device(sec_bus, pci_bus_num(sec_bus), + spapr_phb_pci_collect_nvgpu, opaque); +} + +void spapr_phb_nvgpu_setup(sPAPRPHBState *sphb, Error **errp) +{ + int i, j, valid_gpu_num; + PCIBus *bus; + + /* Search for GPUs and NPUs */ + if (!sphb->nv2_gpa_win_addr || !sphb->nv2_atsd_win_addr) { + return; + } + + sphb->nvgpus =3D g_new0(struct spapr_phb_pci_nvgpu_config, 1); + sphb->nvgpus->nv2_ram_current =3D sphb->nv2_gpa_win_addr; + sphb->nvgpus->nv2_atsd_current =3D sphb->nv2_atsd_win_addr; + + bus =3D PCI_HOST_BRIDGE(sphb)->bus; + pci_for_each_device(bus, pci_bus_num(bus), + spapr_phb_pci_collect_nvgpu, sphb->nvgpus); + + if (sphb->nvgpus->errp) { + error_propagate(errp, sphb->nvgpus->errp); + sphb->nvgpus->errp =3D NULL; + goto cleanup_exit; + } + + /* Add found GPU RAM and ATSD MRs if found */ + for (i =3D 0, valid_gpu_num =3D 0; i < sphb->nvgpus->num; ++i) { + Object *nvmrobj; + struct spapr_phb_pci_nvgpu_slot *nvslot =3D &sphb->nvgpus->slots[i= ]; + + if (!nvslot->gpdev) { + continue; + } + nvmrobj =3D object_property_get_link(OBJECT(nvslot->gpdev), + "nvlink2-mr[0]", NULL); + /* ATSD is pointless without GPU RAM MR so skip those */ + if (!nvmrobj) { + continue; + } + + ++valid_gpu_num; + memory_region_add_subregion(get_system_memory(), nvslot->gpa, + MEMORY_REGION(nvmrobj)); + + for (j =3D 0; j < nvslot->linknum; ++j) { + Object *atsdmrobj; + + atsdmrobj =3D object_property_get_link(OBJECT(nvslot->links[j]= .npdev), + "nvlink2-atsd-mr[0]", NUL= L); + if (!atsdmrobj) { + continue; + } + memory_region_add_subregion(get_system_memory(), + nvslot->links[j].atsd_gpa, + MEMORY_REGION(atsdmrobj)); + } + } + + if (valid_gpu_num) { + return; + } + /* We did not find any interesting GPU */ +cleanup_exit: + g_free(sphb->nvgpus); + sphb->nvgpus =3D NULL; +} + +void spapr_phb_nvgpu_free(sPAPRPHBState *sphb) +{ + int i, j; + + if (!sphb->nvgpus) { + return; + } + + for (i =3D 0; i < sphb->nvgpus->num; ++i) { + struct spapr_phb_pci_nvgpu_slot *nvslot =3D &sphb->nvgpus->slots[i= ]; + Object *nv_mrobj =3D object_property_get_link(OBJECT(nvslot->gpdev= ), + "nvlink2-mr[0]", NULL); + + if (nv_mrobj) { + memory_region_del_subregion(get_system_memory(), + MEMORY_REGION(nv_mrobj)); + } + for (j =3D 0; j < nvslot->linknum; ++j) { + PCIDevice *npdev =3D nvslot->links[j].npdev; + Object *atsd_mrobj; + atsd_mrobj =3D object_property_get_link(OBJECT(npdev), + "nvlink2-atsd-mr[0]", NU= LL); + if (atsd_mrobj) { + memory_region_del_subregion(get_system_memory(), + MEMORY_REGION(atsd_mrobj)); + } + } + } + g_free(sphb->nvgpus); + sphb->nvgpus =3D NULL; +} + +void spapr_phb_nvgpu_populate_dt(sPAPRPHBState *sphb, void *fdt, int bus_o= ff, + Error **errp) +{ + int i, j, atsdnum =3D 0; + uint64_t atsd[8]; /* The existing limitation of known guests */ + + if (!sphb->nvgpus) { + return; + } + + for (i =3D 0; (i < sphb->nvgpus->num) && (atsdnum < ARRAY_SIZE(atsd));= ++i) { + struct spapr_phb_pci_nvgpu_slot *nvslot =3D &sphb->nvgpus->slots[i= ]; + + if (!nvslot->gpdev) { + continue; + } + for (j =3D 0; j < nvslot->linknum; ++j) { + if (!nvslot->links[j].atsd_gpa) { + continue; + } + + if (atsdnum =3D=3D ARRAY_SIZE(atsd)) { + error_setg(errp, "Only %ld ATSD registers supported", + ARRAY_SIZE(atsd)); + break; + } + atsd[atsdnum] =3D cpu_to_be64(nvslot->links[j].atsd_gpa); + ++atsdnum; + } + } + + if (!atsdnum) { + error_setg(errp, "No ATSD registers found"); + return; + } + + if (!spapr_phb_eeh_available(sphb)) { + /* + * ibm,mmio-atsd contains ATSD registers; these belong to an NPU P= HB + * which we do not emulate as a separate device. Instead we put + * ibm,mmio-atsd to the vPHB with GPU and make sure that we do not + * put GPUs from different IOMMU groups to the same vPHB to ensure + * that the guest will use ATSDs from the corresponding NPU. + */ + error_prepend(errp, "ATSD requires separate vPHB per GPU IOMMU gro= up"); + return; + } + + _FDT((fdt_setprop(fdt, bus_off, "ibm,mmio-atsd", atsd, + atsdnum * sizeof(atsd[0])))); +} + +void spapr_phb_nvgpu_ram_populate_dt(sPAPRPHBState *sphb, void *fdt) +{ + int i, j, linkidx, npuoff; + char *npuname; + + if (!sphb->nvgpus) { + return; + } + + npuname =3D g_strdup_printf("npuphb%d", sphb->index); + npuoff =3D fdt_add_subnode(fdt, 0, npuname); + _FDT(npuoff); + _FDT(fdt_setprop_cell(fdt, npuoff, "#address-cells", 1)); + _FDT(fdt_setprop_cell(fdt, npuoff, "#size-cells", 0)); + /* Advertise NPU as POWER9 so the guest can enable NPU2 contexts */ + _FDT((fdt_setprop_string(fdt, npuoff, "compatible", "ibm,power9-npu"))= ); + g_free(npuname); + + for (i =3D 0, linkidx =3D 0; i < sphb->nvgpus->num; ++i) { + for (j =3D 0; j < sphb->nvgpus->slots[i].linknum; ++j) { + char *linkname =3D g_strdup_printf("link@%d", linkidx); + int off =3D fdt_add_subnode(fdt, npuoff, linkname); + + _FDT(off); + /* _FDT((fdt_setprop_cell(fdt, off, "reg", linkidx))); */ + _FDT((fdt_setprop_string(fdt, off, "compatible", + "ibm,npu-link"))); + _FDT((fdt_setprop_cell(fdt, off, "phandle", + PHANDLE_NVLINK(sphb, i, j)))); + _FDT((fdt_setprop_cell(fdt, off, "ibm,npu-link-index", linkidx= ))); + g_free(linkname); + ++linkidx; + } + } + + /* Add memory nodes for GPU RAM and mark them unusable */ + for (i =3D 0; i < sphb->nvgpus->num; ++i) { + struct spapr_phb_pci_nvgpu_slot *nvslot =3D &sphb->nvgpus->slots[i= ]; + Object *nv_mrobj =3D object_property_get_link(OBJECT(nvslot->gpdev= ), + "nvlink2-mr[0]", NULL); + uint32_t at =3D cpu_to_be32(GPURAM_ASSOCIATIVITY(sphb, i)); + uint32_t associativity[] =3D { cpu_to_be32(0x4), at, at, at, at }; + uint64_t size =3D object_property_get_uint(nv_mrobj, "size", NULL); + uint64_t mem_reg[2] =3D { cpu_to_be64(nvslot->gpa), cpu_to_be64(si= ze) }; + char *mem_name =3D g_strdup_printf("memory@%lx", nvslot->gpa); + int off =3D fdt_add_subnode(fdt, 0, mem_name); + + _FDT(off); + _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); + _FDT((fdt_setprop(fdt, off, "reg", mem_reg, sizeof(mem_reg)))); + _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, + sizeof(associativity)))); + + _FDT((fdt_setprop_string(fdt, off, "compatible", + "ibm,coherent-device-memory"))); + + mem_reg[1] =3D cpu_to_be64(0); + _FDT((fdt_setprop(fdt, off, "linux,usable-memory", mem_reg, + sizeof(mem_reg)))); + _FDT((fdt_setprop_cell(fdt, off, "phandle", + PHANDLE_GPURAM(sphb, i)))); + g_free(mem_name); + } + +} + +void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int off= set, + sPAPRPHBState *sphb) +{ + int i, j; + + if (!sphb->nvgpus) { + return; + } + + for (i =3D 0; i < sphb->nvgpus->num; ++i) { + struct spapr_phb_pci_nvgpu_slot *nvslot =3D &sphb->nvgpus->slots[i= ]; + + /* Skip "slot" without attached GPU */ + if (!nvslot->gpdev) { + continue; + } + if (dev =3D=3D nvslot->gpdev) { + uint32_t npus[nvslot->linknum]; + + for (j =3D 0; j < nvslot->linknum; ++j) { + PCIDevice *npdev =3D nvslot->links[j].npdev; + + npus[j] =3D cpu_to_be32(PHANDLE_PCIDEV(sphb, npdev)); + } + _FDT(fdt_setprop(fdt, offset, "ibm,npu", npus, + j * sizeof(npus[0]))); + _FDT((fdt_setprop_cell(fdt, offset, "phandle", + PHANDLE_PCIDEV(sphb, dev)))); + continue; + } + + for (j =3D 0; j < nvslot->linknum; ++j) { + if (dev !=3D nvslot->links[j].npdev) { + continue; + } + + _FDT((fdt_setprop_cell(fdt, offset, "phandle", + PHANDLE_PCIDEV(sphb, dev)))); + _FDT(fdt_setprop_cell(fdt, offset, "ibm,gpu", + PHANDLE_PCIDEV(sphb, nvslot->gpdev))); + _FDT((fdt_setprop_cell(fdt, offset, "ibm,nvlink", + PHANDLE_NVLINK(sphb, i, j)))); + /* + * If we ever want to emulate GPU RAM at the same location as = on + * the host - here is the encoding GPA->TGT: + * + * gta =3D ((sphb->nv2_gpa >> 42) & 0x1) << 42; + * gta |=3D ((sphb->nv2_gpa >> 45) & 0x3) << 43; + * gta |=3D ((sphb->nv2_gpa >> 49) & 0x3) << 45; + * gta |=3D sphb->nv2_gpa & ((1UL << 43) - 1); + */ + _FDT(fdt_setprop_cell(fdt, offset, "memory-region", + PHANDLE_GPURAM(sphb, i))); + _FDT(fdt_setprop_u64(fdt, offset, "ibm,device-tgt-addr", + nvslot->tgt)); + _FDT(fdt_setprop_cell(fdt, offset, "ibm,nvlink-speed", + nvslot->links[j].link_speed)); + } + } +} diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index 40a12001f580..15ec0b4c2723 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -2180,3 +2180,123 @@ int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error *= *errp) =20 return 0; } + +static void vfio_pci_nvlink2_get_tgt(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + uint64_t tgt =3D (uint64_t) opaque; + visit_type_uint64(v, name, &tgt, errp); +} + +static void vfio_pci_nvlink2_get_link_speed(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **err= p) +{ + uint32_t link_speed =3D (uint32_t)(uint64_t) opaque; + visit_type_uint32(v, name, &link_speed, errp); +} + +int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp) +{ + int ret; + void *p; + struct vfio_region_info *nv2region =3D NULL; + struct vfio_info_cap_header *hdr; + MemoryRegion *nv2mr =3D g_malloc0(sizeof(*nv2mr)); + + ret =3D vfio_get_dev_region_info(&vdev->vbasedev, + VFIO_REGION_TYPE_PCI_VENDOR_TYPE | + PCI_VENDOR_ID_NVIDIA, + VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM, + &nv2region); + if (ret) { + return ret; + } + + p =3D mmap(NULL, nv2region->size, PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_SHARED, vdev->vbasedev.fd, nv2region->offset); + + if (!p) { + return -errno; + } + + memory_region_init_ram_ptr(nv2mr, OBJECT(vdev), "nvlink2-mr", + nv2region->size, p); + + hdr =3D vfio_get_region_info_cap(nv2region, + VFIO_REGION_INFO_CAP_NVLINK2_SSATGT); + if (hdr) { + struct vfio_region_info_cap_nvlink2_ssatgt *cap =3D (void *) hdr; + + object_property_add(OBJECT(vdev), "nvlink2-tgt", "uint64", + vfio_pci_nvlink2_get_tgt, NULL, NULL, + (void *) cap->tgt, NULL); + trace_vfio_pci_nvidia_gpu_setup_quirk(vdev->vbasedev.name, cap->tg= t, + nv2region->size); + } + g_free(nv2region); + + return 0; +} + +int vfio_pci_nvlink2_init(VFIOPCIDevice *vdev, Error **errp) +{ + int ret; + void *p; + struct vfio_region_info *atsd_region =3D NULL; + struct vfio_info_cap_header *hdr; + + ret =3D vfio_get_dev_region_info(&vdev->vbasedev, + VFIO_REGION_TYPE_PCI_VENDOR_TYPE | + PCI_VENDOR_ID_IBM, + VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD, + &atsd_region); + if (ret) { + return ret; + } + + /* Some NVLink bridges come without assigned ATSD, skip MR part */ + if (atsd_region->size) { + MemoryRegion *atsd_mr =3D g_malloc0(sizeof(*atsd_mr)); + + p =3D mmap(NULL, atsd_region->size, PROT_READ | PROT_WRITE | PROT_= EXEC, + MAP_SHARED, vdev->vbasedev.fd, atsd_region->offset); + + if (!p) { + return -errno; + } + + memory_region_init_ram_device_ptr(atsd_mr, OBJECT(vdev), + "nvlink2-atsd-mr", + atsd_region->size, + p); + } + + hdr =3D vfio_get_region_info_cap(atsd_region, + VFIO_REGION_INFO_CAP_NVLINK2_SSATGT); + if (hdr) { + struct vfio_region_info_cap_nvlink2_ssatgt *cap =3D (void *) hdr; + + object_property_add(OBJECT(vdev), "nvlink2-tgt", "uint64", + vfio_pci_nvlink2_get_tgt, NULL, NULL, + (void *) cap->tgt, NULL); + trace_vfio_pci_nvlink2_setup_quirk_ssatgt(vdev->vbasedev.name, cap= ->tgt, + atsd_region->size); + } + + hdr =3D vfio_get_region_info_cap(atsd_region, + VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD); + if (hdr) { + struct vfio_region_info_cap_nvlink2_lnkspd *cap =3D (void *) hdr; + + object_property_add(OBJECT(vdev), "nvlink2-link-speed", "uint32", + vfio_pci_nvlink2_get_link_speed, NULL, NULL, + (void *) (uint64_t) cap->link_speed, NULL); + trace_vfio_pci_nvlink2_setup_quirk_lnkspd(vdev->vbasedev.name, + cap->link_speed); + } + g_free(atsd_region); + + return 0; +} diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index dd12f363915d..07aa141aabe6 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -3069,6 +3069,20 @@ static void vfio_realize(PCIDevice *pdev, Error **er= rp) goto out_teardown; } =20 + if (vdev->vendor_id =3D=3D PCI_VENDOR_ID_NVIDIA) { + ret =3D vfio_pci_nvidia_v100_ram_init(vdev, errp); + if (ret && ret !=3D -ENODEV) { + error_report("Failed to setup NVIDIA V100 GPU RAM"); + } + } + + if (vdev->vendor_id =3D=3D PCI_VENDOR_ID_IBM) { + ret =3D vfio_pci_nvlink2_init(vdev, errp); + if (ret && ret !=3D -ENODEV) { + error_report("Failed to setup NVlink2 bridge"); + } + } + vfio_register_err_notifier(vdev); vfio_register_req_notifier(vdev); vfio_setup_resetfn_quirk(vdev); diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events index cf1e8868182b..88841e9a61da 100644 --- a/hw/vfio/trace-events +++ b/hw/vfio/trace-events @@ -87,6 +87,10 @@ vfio_pci_igd_opregion_enabled(const char *name) "%s" vfio_pci_igd_host_bridge_enabled(const char *name) "%s" vfio_pci_igd_lpc_bridge_enabled(const char *name) "%s" =20 +vfio_pci_nvidia_gpu_setup_quirk(const char *name, uint64_t tgt, uint64_t s= ize) "%s tgt=3D0x%"PRIx64" size=3D0x%"PRIx64 +vfio_pci_nvlink2_setup_quirk_ssatgt(const char *name, uint64_t tgt, uint64= _t size) "%s tgt=3D0x%"PRIx64" size=3D0x%"PRIx64 +vfio_pci_nvlink2_setup_quirk_lnkspd(const char *name, uint32_t link_speed)= "%s link_speed=3D0x%x" + # hw/vfio/common.c vfio_region_write(const char *name, int index, uint64_t addr, uint64_t dat= a, unsigned size) " (%s:region%d+0x%"PRIx64", 0x%"PRIx64 ", %d)" vfio_region_read(char *name, int index, uint64_t addr, unsigned size, uint= 64_t data) " (%s:region%d+0x%"PRIx64", %d) =3D 0x%"PRIx64 --=20 2.17.1