From nobody Sun Nov 9 22:27:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551863606118831.9063203727526; Wed, 6 Mar 2019 01:13:26 -0800 (PST) Received: from localhost ([127.0.0.1]:56863 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1Sc6-0006C0-0i for importer@patchew.org; Wed, 06 Mar 2019 04:13:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55487) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1SH5-0006db-J4 for qemu-devel@nongnu.org; Wed, 06 Mar 2019 03:51:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1SH3-00024S-TW for qemu-devel@nongnu.org; Wed, 06 Mar 2019 03:51:39 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:56410 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h1SH3-0001EV-Bi for qemu-devel@nongnu.org; Wed, 06 Mar 2019 03:51:37 -0500 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x268mk41030523 for ; Wed, 6 Mar 2019 03:50:51 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2r29dadrbr-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 06 Mar 2019 03:50:51 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 6 Mar 2019 08:50:48 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x268olCY30933148 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 6 Mar 2019 08:50:47 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 172AD42045; Wed, 6 Mar 2019 08:50:47 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EFDD742042; Wed, 6 Mar 2019 08:50:46 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 6 Mar 2019 08:50:46 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-0-135.uk.ibm.com [9.145.0.135]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 369A5220221; Wed, 6 Mar 2019 09:50:46 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 6 Mar 2019 09:50:14 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190306085032.15744-1-clg@kaod.org> References: <20190306085032.15744-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19030608-0016-0000-0000-0000025E6AC9 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19030608-0017-0000-0000-000032B8F191 Message-Id: <20190306085032.15744-10-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-06_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903060061 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x268mk41030523 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH 09/27] ppc/xive: activate HV support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The NSR register of the HV ring has a different, although similar, bit layout. TM_QW3_NSR_HE_PHYS bit should now be raised when the Hypervisor interrupt line is signaled. Other bits TM_QW3_NSR_HE_POOL and TM_QW3_NSR_HE_LSI are not modeled. LSI are for special interrupts reserved for HW bringup and the POOL bit is used when signaling a group of VPs. This is not currently implemented in Linux but it is in pHyp. The most important special commands on the HV TIMA page are added to let the core manage interrupts : acking and changing the CPU priority. Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xive.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 54 insertions(+), 3 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 7d7992c0ce3f..a0b87001da25 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -54,6 +54,8 @@ static uint8_t exception_mask(uint8_t ring) switch (ring) { case TM_QW1_OS: return TM_QW1_NSR_EO; + case TM_QW3_HV_PHYS: + return TM_QW3_NSR_HE; default: g_assert_not_reached(); } @@ -88,7 +90,16 @@ static void xive_tctx_notify(XiveTCTX *tctx, uint8_t rin= g) uint8_t *regs =3D &tctx->regs[ring]; =20 if (regs[TM_PIPR] < regs[TM_CPPR]) { - regs[TM_NSR] |=3D exception_mask(ring); + switch (ring) { + case TM_QW1_OS: + regs[TM_NSR] |=3D TM_QW1_NSR_EO; + break; + case TM_QW3_HV_PHYS: + regs[TM_NSR] |=3D (TM_QW3_NSR_HE_PHYS << 6); + break; + default: + g_assert_not_reached(); + } qemu_irq_raise(tctx->output); } } @@ -109,6 +120,38 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t= ring, uint8_t cppr) * XIVE Thread Interrupt Management Area (TIMA) */ =20 +static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset, + uint64_t value, unsigned size) +{ + xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); +} + +static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned= size) +{ + return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); +} + +static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, + unsigned size) +{ + uint64_t ret; + + ret =3D tctx->regs[TM_QW2_HV_POOL + TM_WORD2] & TM_QW2W2_POOL_CAM; + tctx->regs[TM_QW2_HV_POOL + TM_WORD2] &=3D ~TM_QW2W2_POOL_CAM; + return ret; +} + +static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, + uint64_t value, unsigned size) +{ + tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] =3D value & 0xff; +} + +static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned si= ze) +{ + return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; +} + /* * Define an access map for each page of the TIMA that we will use in * the memory region ops to filter values when doing loads and stores @@ -288,10 +331,16 @@ static const XiveTmOp xive_tm_operations[] =3D { * effects */ { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL= }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, N= ULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL= }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll= }, =20 /* MMIOs above 2K : special operations with side effects */ { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg = }, { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, N= ULL }, + { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg = }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_c= tx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_c= tx }, }; =20 static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool = write) @@ -323,7 +372,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, = uint64_t value, const XiveTmOp *xto; =20 /* - * TODO: check V bit in Q[0-3]W2, check PTER bit associated with CPU + * TODO: check V bit in Q[0-3]W2 */ =20 /* @@ -360,7 +409,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offse= t, unsigned size) const XiveTmOp *xto; =20 /* - * TODO: check V bit in Q[0-3]W2, check PTER bit associated with CPU + * TODO: check V bit in Q[0-3]W2 */ =20 /* @@ -472,6 +521,8 @@ static void xive_tctx_reset(void *dev) */ tctx->regs[TM_QW1_OS + TM_PIPR] =3D ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); + tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] =3D + ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); } =20 static void xive_tctx_realize(DeviceState *dev, Error **errp) --=20 2.20.1