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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 2sm10071495wrg.89.2019.03.05.08.51.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Mar 2019 08:51:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pst1NFAs0J0OzpJurEJPfYEB9/dNd7bzOWfgCBqK4d4=; b=dP3rtVtbjmKVv0HNnWIrNUSYoTC7PJAqAITb4p2+b5gB2cVLTnSJRz1FEbJ7OQZjS0 uY+wDjZe0++OlyrsELRSOWJVvQzkpqqiq1RHHlNi5AbeO5oJ3Vz1SKHKa7+RBppzpQZo NZAIYdbjHOEQ6uNUKf/Uvf0/bhlxEWhSiBfANg7Lm4/wx/TVwtAMDX1iw5iGjb38YSBG 52QKT3q1rR8Xso20o2EmnqC6UAdDJhyW/Fs8NMPXrj3IxTOsBXoLdbZhYLOIDlMp561o 683w4sNDWQGEsz2e3z1ZZhWmN/c0LTKf7JjVyyfpWBrdv2QBF/xAHFPt2Ui6kHC2Bwu5 ttnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pst1NFAs0J0OzpJurEJPfYEB9/dNd7bzOWfgCBqK4d4=; b=pAksNN+LAJ6wz8qXoEX4lQZxk8xFjbfxvSo7Jb2It/Tenne5m6RJhq6JAErq6zGPmx bM0KO+7Yai6wO0uvfoHnedFXedQ9nwn5rXhFiEgy8Zu0ffdrZgKV3eWRjTB0uC2kpJQf DPK4v3WHNXFq9yaMuj5UTdiiWTHuLAPDPLNHS52pCqzSOOTmaNA98v+b6wA+6TIc2Prk je1H8n5JkFIfGcCcNcU1sgYSJU6D5rErtmPdg+/Z0cnDxqsbZqIB9HZg2sMh4pvj0/m+ YR/9S5C9d0IOUzL+1N3RQK8doDFeMqzfKntkZcPN78ywxbELDyRdFjpq6Xu76FSTnRjG P+kQ== X-Gm-Message-State: APjAAAW1SVecO7gZQBbxkPdT4R9qpp4EnR+CHLJYFFCz0+tiAna+4Fx/ oxEsCa0tNYJpzdSrt6KZ7wwbSrEfdPQ= X-Google-Smtp-Source: APXvYqxlcYKWCBX6u6B4fD7QuytqlXxXt9GR/WH0HCAgrHU54vWByUkHN6l2ZOj0xu60fwh5Di9h/g== X-Received: by 2002:a1c:dc0a:: with SMTP id t10mr3360873wmg.101.1551804663530; Tue, 05 Mar 2019 08:51:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Mar 2019 16:50:37 +0000 Message-Id: <20190305165051.26860-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190305165051.26860-1-peter.maydell@linaro.org> References: <20190305165051.26860-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PULL 08/22] target/arm: Implement ARMv8.4-CondM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Tested-by: Laurent Desnogues Signed-off-by: Richard Henderson Message-id: 20190301200501.16533-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell [PMM: fixed up block comment style] Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 ++ linux-user/elfload.c | 1 + target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 99 +++++++++++++++++++++++++++++++++++++- 4 files changed, 105 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c822f94236c..fc2909ea6dc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3431,6 +3431,11 @@ static inline bool isar_feature_aa64_fhm(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) !=3D 0; } =20 +static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) !=3D 0; +} + static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 6cfebe1446d..6e8762b40de 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -605,6 +605,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM); GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); + GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); =20 #undef GET_FEATURE_ID =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 87337b63855..fcf79321e2f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -309,6 +309,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 1); cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 12d2649c204..3cc9a99a9cb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1657,6 +1657,14 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_TOO_MANY; =20 switch (op) { + case 0x00: /* CFINV */ + if (crm !=3D 0 || !dc_isar_feature(aa64_condm_4, s)) { + goto do_unallocated; + } + tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); + s->base.is_jmp =3D DISAS_NEXT; + break; + case 0x05: /* SPSel */ if (s->current_el =3D=3D 0) { goto do_unallocated; @@ -1710,7 +1718,6 @@ static void gen_get_nzcv(TCGv_i64 tcg_rt) } =20 static void gen_set_nzcv(TCGv_i64 tcg_rt) - { TCGv_i32 nzcv =3D tcg_temp_new_i32(); =20 @@ -4529,6 +4536,84 @@ static void disas_adc_sbc(DisasContext *s, uint32_t = insn) } } =20 +/* + * Rotate right into flags + * 31 30 29 21 15 10 5 4 0 + * +--+--+--+-----------------+--------+-----------+------+--+------+ + * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask | + * +--+--+--+-----------------+--------+-----------+------+--+------+ + */ +static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn) +{ + int mask =3D extract32(insn, 0, 4); + int o2 =3D extract32(insn, 4, 1); + int rn =3D extract32(insn, 5, 5); + int imm6 =3D extract32(insn, 15, 6); + int sf_op_s =3D extract32(insn, 29, 3); + TCGv_i64 tcg_rn; + TCGv_i32 nzcv; + + if (sf_op_s !=3D 5 || o2 !=3D 0 || !dc_isar_feature(aa64_condm_4, s)) { + unallocated_encoding(s); + return; + } + + tcg_rn =3D read_cpu_reg(s, rn, 1); + tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6); + + nzcv =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(nzcv, tcg_rn); + + if (mask & 8) { /* N */ + tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3); + } + if (mask & 4) { /* Z */ + tcg_gen_not_i32(cpu_ZF, nzcv); + tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4); + } + if (mask & 2) { /* C */ + tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1); + } + if (mask & 1) { /* V */ + tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0); + } + + tcg_temp_free_i32(nzcv); +} + +/* + * Evaluate into flags + * 31 30 29 21 15 14 10 5 4 0 + * +--+--+--+-----------------+---------+----+---------+------+--+------+ + * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask | + * +--+--+--+-----------------+---------+----+---------+------+--+------+ + */ +static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn) +{ + int o3_mask =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + int o2 =3D extract32(insn, 15, 6); + int sz =3D extract32(insn, 14, 1); + int sf_op_s =3D extract32(insn, 29, 3); + TCGv_i32 tmp; + int shift; + + if (sf_op_s !=3D 1 || o2 !=3D 0 || o3_mask !=3D 0xd || + !dc_isar_feature(aa64_condm_4, s)) { + unallocated_encoding(s); + return; + } + shift =3D sz ? 16 : 24; /* SETF16 or SETF8 */ + + tmp =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn)); + tcg_gen_shli_i32(cpu_NF, tmp, shift); + tcg_gen_shli_i32(cpu_VF, tmp, shift - 1); + tcg_gen_mov_i32(cpu_ZF, cpu_NF); + tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF); + tcg_temp_free_i32(tmp); +} + /* Conditional compare (immediate / register) * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 = 0 * +--+--+--+------------------------+--------+------+----+--+------+--+--= ---+ @@ -5195,6 +5280,18 @@ static void disas_data_proc_reg(DisasContext *s, uin= t32_t insn) disas_adc_sbc(s, insn); break; =20 + case 0x01: /* Rotate right into flags */ + case 0x21: + disas_rotate_right_into_flags(s, insn); + break; + + case 0x02: /* Evaluate into flags */ + case 0x12: + case 0x22: + case 0x32: + disas_evaluate_into_flags(s, insn); + break; + default: goto do_unallocated; } --=20 2.20.1