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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 2sm10071495wrg.89.2019.03.05.08.50.59 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Mar 2019 08:50:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sILGEvJbUY9LBA3iBxsJ8/AaEFFvkIepHtI5FM+vLtw=; b=YUIzQ+2DZOUS5V7O3wuQ3pbAh2Zqdodg1d+Qu7jW/7e3DyfyGS7vA28gckh/MoDmtl BAg8RQfS2eYGvyNlKmNldlJudskyBEttUNmHIY9+BYMx6I5oS3ozJm1ew1cbDARsDi/c rBcejWMR/cKymwBewSvaJDYEv4esbBV/BiX8upZEGCmqQad6sebAn5MXRohBGI/sWbCz 6Y3xVPtn6bgcHQ9+1Utn4G4UJMOFRsLK8aPzNIbEwemVBoEOIUzri43jLq/+V82YhGjZ O0QUZnwQyNc+dvXgEOmcUjlobzhAg+6pLigDTWn1VYr35hw0uUMxlk0Vpf44ZXrOq+Af AMGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sILGEvJbUY9LBA3iBxsJ8/AaEFFvkIepHtI5FM+vLtw=; b=C32z0h0Eb/YcQSCTNA068EJLh0lt/VzMUk631zVFaj/22nLy5usZ7jYxEyPi2qXCha RHMqfF960D6yfjBJ8lnP6kK9QJ3dWmQiyOaPrIerkXNQIB8NMyg6lxmRUvWsAsFLLycG +6MRKGgeJf8fzgYG+CmiSJhIT74sjHrWk5ImhyWqomTQMHUGmDfEFjMKMveYCYa7LOdA AhBjOhvqSdErrFQJFdqGvMAilh/NIIXfJ0KypxfJU4+kSJEQXNdSXnL2eBFWDk7z7oZu PQA0+7C0cS7KLyNnNDzcHUK4EL0vZbJzaNOMZZEqisq0eOC32/Bc+mkAvvdKwx5BPyuA Yk8w== X-Gm-Message-State: APjAAAXxsPBYo71oBeRtCGV8IxoUfeLq98F1guruQx/SloawXQy+aAPh QtTCj0u8w/tRhCR5P2wkyPlzcWgabpc= X-Google-Smtp-Source: APXvYqy53/f6fuDUDtOWsf4uMOi2U/LIn3oV3APv+0e7t/TuYD2opz9os8tUXtn1nq4UIzO8gfYW4g== X-Received: by 2002:a5d:428b:: with SMTP id k11mr17916444wrq.17.1551804660243; Tue, 05 Mar 2019 08:51:00 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Mar 2019 16:50:34 +0000 Message-Id: <20190305165051.26860-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190305165051.26860-1-peter.maydell@linaro.org> References: <20190305165051.26860-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 Subject: [Qemu-devel] [PULL 05/22] target/arm: Split helper_msr_i_pstate into 3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The EL0+UMA check is unique to DAIF. While SPSel had avoided the check by nature of already checking EL >=3D 1, the other post v8.0 extensions to MSR (imm) allow EL0 and do not require UMA. Avoid the unconditional write to pc and use raise_exception_ra to unwind. Signed-off-by: Richard Henderson Message-id: 20190301200501.16533-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 3 +++ target/arm/helper.h | 1 - target/arm/internals.h | 15 ++++++++++++++ target/arm/helper-a64.c | 30 +++++++++++++++++++++++++++ target/arm/op_helper.c | 42 -------------------------------------- target/arm/translate-a64.c | 41 ++++++++++++++++++++++--------------- 6 files changed, 73 insertions(+), 59 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index aff8d6c9f39..a915c1247fe 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -19,6 +19,9 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_2(msr_i_spsel, void, env, i32) +DEF_HELPER_2(msr_i_daifset, void, env, i32) +DEF_HELPER_2(msr_i_daifclear, void, env, i32) DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) diff --git a/target/arm/helper.h b/target/arm/helper.h index d363904278a..6f0f3869262 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -77,7 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) =20 -DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) DEF_HELPER_1(clear_pstate_ss, void, env) =20 DEF_HELPER_2(get_r13_banked, i32, env, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index a4bd1becb75..587a1ddf580 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -968,4 +968,19 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *e= nv, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); =20 +static inline int exception_target_el(CPUARMState *env) +{ + int target_el =3D MAX(1, arm_current_el(env)); + + /* + * No such thing as secure EL1 if EL3 is aarch32, + * so update the target EL to EL3 in this case. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el =3D=3D = 1) { + target_el =3D 3; + } + + return target_el; +} + #endif diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 70850e564d3..796ef34b55e 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -61,6 +61,36 @@ uint64_t HELPER(rbit64)(uint64_t x) return revbit64(x); } =20 +void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm) +{ + update_spsel(env, imm); +} + +static void daif_check(CPUARMState *env, uint32_t op, + uint32_t imm, uintptr_t ra) +{ + /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ + if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { + raise_exception_ra(env, EXCP_UDEF, + syn_aa64_sysregtrap(0, extract32(op, 0, 3), + extract32(op, 3, 3), 4, + imm, 0x1f, 0), + exception_target_el(env), ra); + } +} + +void HELPER(msr_i_daifset)(CPUARMState *env, uint32_t imm) +{ + daif_check(env, 0x1e, imm, GETPC()); + env->daif |=3D (imm << 6) & PSTATE_DAIF; +} + +void HELPER(msr_i_daifclear)(CPUARMState *env, uint32_t imm) +{ + daif_check(env, 0x1f, imm, GETPC()); + env->daif &=3D ~((imm << 6) & PSTATE_DAIF); +} + /* Convert a softfloat float_relation_ (as returned by * the float*_compare functions) to the correct ARM * NZCV flag state. diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c998eadfaa8..c5721a866d3 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -68,20 +68,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp,= uint32_t syndrome, cpu_loop_exit_restore(cs, ra); } =20 -static int exception_target_el(CPUARMState *env) -{ - int target_el =3D MAX(1, arm_current_el(env)); - - /* No such thing as secure EL1 if EL3 is aarch32, so update the target= EL - * to EL3 in this case. - */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el =3D=3D = 1) { - target_el =3D 3; - } - - return target_el; -} - uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, uint32_t maxindex) { @@ -875,34 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *= rip) return res; } =20 -void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) -{ - /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set. - * Note that SPSel is never OK from EL0; we rely on handle_msr_i() - * to catch that case at translate time. - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { - uint32_t syndrome =3D syn_aa64_sysregtrap(0, extract32(op, 0, 3), - extract32(op, 3, 3), 4, - imm, 0x1f, 0); - raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)= ); - } - - switch (op) { - case 0x05: /* SPSel */ - update_spsel(env, imm); - break; - case 0x1e: /* DAIFSet */ - env->daif |=3D (imm << 6) & PSTATE_DAIF; - break; - case 0x1f: /* DAIFClear */ - env->daif &=3D ~((imm << 6) & PSTATE_DAIF); - break; - default: - g_assert_not_reached(); - } -} - void HELPER(clear_pstate_ss)(CPUARMState *env) { env->pstate &=3D ~PSTATE_SS; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4aa5a307e41..1e49d333655 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1661,29 +1661,38 @@ static void handle_sync(DisasContext *s, uint32_t i= nsn, static void handle_msr_i(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int = crm) { + TCGv_i32 t1; int op =3D op1 << 3 | op2; + + /* End the TB by default, chaining is ok. */ + s->base.is_jmp =3D DISAS_TOO_MANY; + switch (op) { case 0x05: /* SPSel */ if (s->current_el =3D=3D 0) { - unallocated_encoding(s); - return; + goto do_unallocated; } - /* fall through */ - case 0x1e: /* DAIFSet */ - case 0x1f: /* DAIFClear */ - { - TCGv_i32 tcg_imm =3D tcg_const_i32(crm); - TCGv_i32 tcg_op =3D tcg_const_i32(op); - gen_a64_set_pc_im(s->pc - 4); - gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); - tcg_temp_free_i32(tcg_imm); - tcg_temp_free_i32(tcg_op); - /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ - gen_a64_set_pc_im(s->pc); - s->base.is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); + t1 =3D tcg_const_i32(crm & PSTATE_SP); + gen_helper_msr_i_spsel(cpu_env, t1); + tcg_temp_free_i32(t1); break; - } + + case 0x1e: /* DAIFSet */ + t1 =3D tcg_const_i32(crm); + gen_helper_msr_i_daifset(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + + case 0x1f: /* DAIFClear */ + t1 =3D tcg_const_i32(crm); + gen_helper_msr_i_daifclear(cpu_env, t1); + tcg_temp_free_i32(t1); + /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ + s->base.is_jmp =3D DISAS_UPDATE; + break; + default: + do_unallocated: unallocated_encoding(s); return; } --=20 2.20.1