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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 2sm10071495wrg.89.2019.03.05.08.50.56 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Mar 2019 08:50:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1uIXKoONtnkjCTDZZuAUO2wCgsqHmmOWbYwfgzZEbss=; b=rI6e9KXRVQqc3l9NbxyAPX3LRq8MF07XkiZRvtbhn7SYI7d2AfuSFYzvE7hpUY1u2H ZRqhU9eiIsrl7qxchaugqKP5GJqkzL01Vxdic0zPZ5khlrPKz7tGqyFuFK/66KXIl5LQ j/HSZ6/3hlzy44QzFXp1AgBQSugEgpDHaGe8FMXUg3J4aNa9SW6/e9zzPqvGmodZn3gq PpGS5v0KM5tWwe62snJDy+lOyZbmkcg7oUHremq130X3vnePgHnq2nmm7uwes6sAnKyr 9X8bNAMa9PvCHEduTj5b5BhGAZdC8VmwYp6osDiL5p51E7/+6MxnRYgr/Aekaj9+fNbe m+Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1uIXKoONtnkjCTDZZuAUO2wCgsqHmmOWbYwfgzZEbss=; b=eTw8svz80QDZWnH8gZr5/VDWFON6oQe50jJCTRsq//o3KzLe3An8iv2UGxd6h69GVg gSwftLfWHOWxdtFgJeaqgTY7qwUWtyTbiKZGgxn4TUXkMmYcyo3ou+QCpfmECrSR3w7H i0ABvbghQMavCWdXZyaZKOHiP7/N6RasAXz1yeFsQ8RRfqi/gezbjaj/8WfYKp53zSvc 4pTi6G9CphlUtJ2BVGyeRHmbNwb9NlbD1plk5YYYafgzFZGep3hRz28fwKy37nNSjChc fHEQ+vzvI03Ly22U+TUeA7eon/CZ+ON2eqa4ZNbT4kFZeiS8tprjCsf3VqxFFRPsre7d Jn9w== X-Gm-Message-State: APjAAAVUlqTHCtV1fM5xIarA2yT8MpplN7FfxT56NOMuCXf0wDZtPr72 nVIubWC0o/rkGd0wQSF1zcFECtKqXSE= X-Google-Smtp-Source: APXvYqzzeF1aNVmKSkFYye+KXk+HLtsf7PZuNuz4VFL1pBCoJWB58QhlWvunqnv5EZqoaVaTCW0zUg== X-Received: by 2002:adf:fc12:: with SMTP id i18mr16736622wrr.201.1551804657903; Tue, 05 Mar 2019 08:50:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Mar 2019 16:50:32 +0000 Message-Id: <20190305165051.26860-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190305165051.26860-1-peter.maydell@linaro.org> References: <20190305165051.26860-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 Subject: [Qemu-devel] [PULL 03/22] target/arm: Implement ARMv8.0-SB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20190301200501.16533-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++++ linux-user/elfload.c | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ target/arm/translate-a64.c | 14 ++++++++++++++ target/arm/translate.c | 22 ++++++++++++++++++++++ 6 files changed, 50 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 67b06bfad09..361e51143c7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3307,6 +3307,11 @@ static inline bool isar_feature_aa32_fhm(const ARMIS= ARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) !=3D 0; } =20 +static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* @@ -3445,6 +3450,11 @@ static inline bool isar_feature_aa64_pauth(const ARM= ISARegisters *id) FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) !=3D 0; } =20 +static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index b9f7cbbdc17..6cfebe1446d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -604,6 +604,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM); GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); + GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); =20 #undef GET_FEATURE_ID =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 54b61f917be..ef069c268df 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2021,6 +2021,7 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); cpu->isar.id_isar6 =3D t; =20 t =3D cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1b0c427277b..6788c0f6ff7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -318,6 +318,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; @@ -349,6 +350,7 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); cpu->isar.id_isar6 =3D u; =20 /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d3c8eaf0893..4aa5a307e41 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1637,7 +1637,21 @@ static void handle_sync(DisasContext *s, uint32_t in= sn, reset_btype(s); gen_goto_tb(s, 0, s->pc); return; + + case 7: /* SB */ + if (crm !=3D 0 || !dc_isar_feature(aa64_sb, s)) { + goto do_unallocated; + } + /* + * TODO: There is no speculation barrier opcode for TCG; + * MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc); + return; + default: + do_unallocated: unallocated_encoding(s); return; } diff --git a/target/arm/translate.c b/target/arm/translate.c index ad879e3480c..9f71206f857 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9282,6 +9282,17 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) */ gen_goto_tb(s, 0, s->pc & ~1); return; + case 7: /* sb */ + if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { + goto illegal_op; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc & ~1); + return; default: goto illegal_op; } @@ -11900,6 +11911,17 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) */ gen_goto_tb(s, 0, s->pc & ~1); break; + case 7: /* sb */ + if ((insn & 0xf) || !dc_isar_feature(aa32_sb, = s)) { + goto illegal_op; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc & ~1); + break; default: goto illegal_op; } --=20 2.20.1