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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 2sm10071495wrg.89.2019.03.05.08.51.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Mar 2019 08:51:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dEsL2TadOfzi2urpg/PHwOtzpKuEWVEwxv/gJ1fTYko=; b=ZMrH2+btB3IFDJF81QlnLXGF2axzUEp8deuJXpudtaRy0sAdd64kguyTPp2AKJ8GB1 fGBRIDpfBCpDf08X60sPt7sCFi5Sw/7RN7CViYB3oB9y5MX6SFDp0nqlGPvXDSZRXF4M 8paO8Tp1Kla7DHe6GO8mMlSi/5x1UaRXSVh02YzL4E6ZCt9/+8CcK1c/c6bcNW03Rwhp lbQUSZkyBin19XGBAGAyQCb7KObK6/yayRGCV/S9+zUNg71/vtPkTRFeQesbNSMul6Y4 KS+7bH6b+lpqmXbOhHt6Ye87M29IuQG1Bif1NOzVV/x33rRDf55uws8zidU+q2VH9Bp0 EpDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dEsL2TadOfzi2urpg/PHwOtzpKuEWVEwxv/gJ1fTYko=; b=aLZ/CRVlmEzhS3Wufq5TEUMq6NSxDDyJYeTIhFaokfjdManT4I3d8Cw4Uyjl65vlHr iluJHRXKIJFXdhr6JPBl9G4XD6pFeRvPs3wZO+J6gCcMM3Nv/eWAUx50nEO7/JT2y6Y/ crDneQ7a8X1Y/BStvxkmY3U9ibkrPXh1QbTK/QbUiavmeIPkHg8DjuVBZATICQyadGrZ 7CxCpBiaqmQ3NjGq5NGmT0eZmnPuSNK17XSTzSb6Xi8R92V0r0hlUDH5ZRWWwQUMcyQG g8Es18PH0UfR8btWaygloC1evt1H5XFoduzz04pOlYt/AI8NoUbeBkoj5C4Seig1TsDc rh2A== X-Gm-Message-State: APjAAAVe0L/vBskbFAmQRjDXTlq+1L1ppAtcQ7mDrc4dDG7ekwUXiIY5 pqFfKiuq0+mEnXyhmw8RM+zwx0816ec= X-Google-Smtp-Source: APXvYqyIlIgAv5FHsxiohHab0CM67XJkxox6Y+pVLR4/GrhDSzMnIYjq69JlXz04NBA1o9AcffD08g== X-Received: by 2002:a05:6000:1110:: with SMTP id z16mr17277621wrw.28.1551804669208; Tue, 05 Mar 2019 08:51:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Mar 2019 16:50:42 +0000 Message-Id: <20190305165051.26860-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190305165051.26860-1-peter.maydell@linaro.org> References: <20190305165051.26860-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a Subject: [Qemu-devel] [PULL 13/22] hw/arm/virt: Rename highmem IO regions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Eric Auger In preparation for a split of the memory map into a static part and a dynamic part floating after the RAM, let's rename the regions located after the RAM Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Reviewed-by: Igor Mammedov Message-id: 20190304101339.25970-3-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 8 ++++---- hw/arm/virt-acpi-build.c | 10 ++++++---- hw/arm/virt.c | 33 ++++++++++++++++++--------------- 3 files changed, 28 insertions(+), 23 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 4cc57a7ef62..a27086d524c 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -64,7 +64,7 @@ enum { VIRT_GIC_VCPU, VIRT_GIC_ITS, VIRT_GIC_REDIST, - VIRT_GIC_REDIST2, + VIRT_HIGH_GIC_REDIST2, VIRT_SMMU, VIRT_UART, VIRT_MMIO, @@ -74,9 +74,9 @@ enum { VIRT_PCIE_MMIO, VIRT_PCIE_PIO, VIRT_PCIE_ECAM, - VIRT_PCIE_ECAM_HIGH, + VIRT_HIGH_PCIE_ECAM, VIRT_PLATFORM_BUS, - VIRT_PCIE_MMIO_HIGH, + VIRT_HIGH_PCIE_MMIO, VIRT_GPIO, VIRT_SECURE_UART, VIRT_SECURE_MEM, @@ -128,7 +128,7 @@ typedef struct { int psci_conduit; } VirtMachineState; =20 -#define VIRT_ECAM_ID(high) (high ? VIRT_PCIE_ECAM_HIGH : VIRT_PCIE_ECAM) +#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) =20 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt") #define VIRT_MACHINE(obj) \ diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 04b62c714d9..d7e2e4885b8 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -229,8 +229,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapE= ntry *memmap, size_pio)); =20 if (use_highmem) { - hwaddr base_mmio_high =3D memmap[VIRT_PCIE_MMIO_HIGH].base; - hwaddr size_mmio_high =3D memmap[VIRT_PCIE_MMIO_HIGH].size; + hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; + hwaddr size_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].size; =20 aml_append(rbuf, aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, @@ -663,8 +663,10 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) gicr =3D acpi_data_push(table_data, sizeof(*gicr)); gicr->type =3D ACPI_APIC_GENERIC_REDISTRIBUTOR; gicr->length =3D sizeof(*gicr); - gicr->base_address =3D cpu_to_le64(memmap[VIRT_GIC_REDIST2].ba= se); - gicr->range_length =3D cpu_to_le32(memmap[VIRT_GIC_REDIST2].si= ze); + gicr->base_address =3D + cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base); + gicr->range_length =3D + cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size); } =20 if (its_class_name() && !vmc->no_its) { diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99c2b6e60d7..892bae4f3a7 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -150,10 +150,10 @@ static const MemMapEntry a15memmap[] =3D { [VIRT_PCIE_ECAM] =3D { 0x3f000000, 0x01000000 }, [VIRT_MEM] =3D { 0x40000000, RAMLIMIT_BYTES }, /* Additional 64 MB redist region (can contain up to 512 redistributor= s) */ - [VIRT_GIC_REDIST2] =3D { 0x4000000000ULL, 0x4000000 }, - [VIRT_PCIE_ECAM_HIGH] =3D { 0x4010000000ULL, 0x10000000 }, + [VIRT_HIGH_GIC_REDIST2] =3D { 0x4000000000ULL, 0x4000000 }, + [VIRT_HIGH_PCIE_ECAM] =3D { 0x4010000000ULL, 0x10000000 }, /* Second PCIe window, 512GB wide at the 512GB boundary */ - [VIRT_PCIE_MMIO_HIGH] =3D { 0x8000000000ULL, 0x8000000000ULL }, + [VIRT_HIGH_PCIE_MMIO] =3D { 0x8000000000ULL, 0x8000000000ULL }, }; =20 static const int a15irqmap[] =3D { @@ -431,12 +431,12 @@ static void fdt_add_gic_node(VirtMachineState *vms) 2, vms->memmap[VIRT_GIC_REDIST].s= ize); } else { qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_DIST].bas= e, - 2, vms->memmap[VIRT_GIC_DIST].siz= e, - 2, vms->memmap[VIRT_GIC_REDIST].b= ase, - 2, vms->memmap[VIRT_GIC_REDIST].s= ize, - 2, vms->memmap[VIRT_GIC_REDIST2].= base, - 2, vms->memmap[VIRT_GIC_REDIST2].= size); + 2, vms->memmap[VIRT_GIC_DIST].base, + 2, vms->memmap[VIRT_GIC_DIST].size, + 2, vms->memmap[VIRT_GIC_REDIST].base, + 2, vms->memmap[VIRT_GIC_REDIST].size, + 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].bas= e, + 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].siz= e); } =20 if (vms->virt) { @@ -584,7 +584,7 @@ static void create_gic(VirtMachineState *vms, qemu_irq = *pic) =20 if (nb_redist_regions =3D=3D 2) { uint32_t redist1_capacity =3D - vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_= SIZE; + vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST= _SIZE; =20 qdev_prop_set_uint32(gicdev, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); @@ -601,7 +601,8 @@ static void create_gic(VirtMachineState *vms, qemu_irq = *pic) if (type =3D=3D 3) { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); if (nb_redist_regions =3D=3D 2) { - sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_REDIST2].ba= se); + sysbus_mmio_map(gicbusdev, 2, + vms->memmap[VIRT_HIGH_GIC_REDIST2].base); } } else { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); @@ -1088,8 +1089,8 @@ static void create_pcie(VirtMachineState *vms, qemu_i= rq *pic) { hwaddr base_mmio =3D vms->memmap[VIRT_PCIE_MMIO].base; hwaddr size_mmio =3D vms->memmap[VIRT_PCIE_MMIO].size; - hwaddr base_mmio_high =3D vms->memmap[VIRT_PCIE_MMIO_HIGH].base; - hwaddr size_mmio_high =3D vms->memmap[VIRT_PCIE_MMIO_HIGH].size; + hwaddr base_mmio_high =3D vms->memmap[VIRT_HIGH_PCIE_MMIO].base; + hwaddr size_mmio_high =3D vms->memmap[VIRT_HIGH_PCIE_MMIO].size; hwaddr base_pio =3D vms->memmap[VIRT_PCIE_PIO].base; hwaddr size_pio =3D vms->memmap[VIRT_PCIE_PIO].size; hwaddr base_ecam, size_ecam; @@ -1417,8 +1418,10 @@ static void machvirt_init(MachineState *machine) * many redistributors we can fit into the memory map. */ if (vms->gic_version =3D=3D 3) { - virt_max_cpus =3D vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST= _SIZE; - virt_max_cpus +=3D vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDI= ST_SIZE; + virt_max_cpus =3D + vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + virt_max_cpus +=3D + vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; } else { virt_max_cpus =3D GIC_NCPU; } --=20 2.20.1