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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 2sm10071495wrg.89.2019.03.05.08.51.03 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Mar 2019 08:51:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tCUFi8KL/iSAnR6rUeS/eCrgxPaDmrB63r4RMOCGA/M=; b=GsLDi6LWcKZVYS+6ApCAlwRW0oCoOT9non+76TMWLOXTGhXAkcKkQTY/rsTh7W0+j7 +b8tEwefnSkXQNTx7y/IiqJarcY+HDUvcYvGEUYzp+KLnOmI+QefeqzxWSHNpgzfkejA LN4n77r78srvgMqRw1sSkfqNIh3ecBDInfEVYkWaIFMigjETCVfvTpggeAXNTPz8n9eF UxU60SXAzZWVTN2cXhxPqJ7tO341s7PKniAYoT9FMBxINzrSacRfoLwU1wP0T17M93DJ VG4dmrfscPn9NlNx5S5mkIXQkSOM7B4l8xNLJHGmornj8eQu9Oey7o/zlb6jWfSCpahN PaHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tCUFi8KL/iSAnR6rUeS/eCrgxPaDmrB63r4RMOCGA/M=; b=J1HiSoFoHpzg6TxGWY4NuZYN+KWOWwHGNZ5UfVM0TVWifL90aYAdDa93pFAmnNaVF3 2JFLzu4EGjLYI20Y1is54CjS2iQtWfJvp8iUSboz1vORuolFQa5LTnILR+cePSLscpNV Xps9AoSzLuiex6u9nFKYWzSh5h4y3rFna3DC3zJesQbFs7K7Uk/rCQyXXc1rDBHnYO9f YRQMHeqXbiB9VEV0p6HykA/PkT2SilqnhbjVSyj1kF38sLoIg9SHnj+2ExrpqpnCgDOB gxfdgy4gWK4G5s59zAiNMdqJuqD29k3LCYf4IKXSO0oqDeSRS4JsgO0ByBrKQu6bDVxM z82w== X-Gm-Message-State: APjAAAVowUOKmiAmcbaI1rZhmEoMEpPyraAIhm/zE3RrRbG4gVpFBy97 pEk1giSel34GTB4fFRHt1l/u+rVVnRY= X-Google-Smtp-Source: APXvYqzfFxoiLnXEkBcfNuX56EbjgB8bs37g5NJfUGEZflhvhCrTBbNOkgB5gzrBly4NOu0CjycyNQ== X-Received: by 2002:a5d:55c5:: with SMTP id i5mr18600294wrw.245.1551804664556; Tue, 05 Mar 2019 08:51:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Mar 2019 16:50:38 +0000 Message-Id: <20190305165051.26860-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190305165051.26860-1-peter.maydell@linaro.org> References: <20190305165051.26860-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b Subject: [Qemu-devel] [PULL 09/22] target/arm: Implement ARMv8.5-CondM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Tested-by: Laurent Desnogues Signed-off-by: Richard Henderson Message-id: 20190301200501.16533-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 ++++ target/arm/cpu64.c | 2 +- target/arm/translate-a64.c | 58 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fc2909ea6dc..a7aaec63d74 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3436,6 +3436,11 @@ static inline bool isar_feature_aa64_condm_4(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) !=3D 0; } =20 +static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >=3D 2; +} + static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index fcf79321e2f..9fe0844a828 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -309,7 +309,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3cc9a99a9cb..0cfd07d3abd 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1646,6 +1646,48 @@ static void handle_sync(DisasContext *s, uint32_t in= sn, } } =20 +static void gen_xaflag(void) +{ + TCGv_i32 z =3D tcg_temp_new_i32(); + + tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); + + /* + * (!C & !Z) << 31 + * (!(C | Z)) << 31 + * ~((C | Z) << 31) + * ~-(C | Z) + * (C | Z) - 1 + */ + tcg_gen_or_i32(cpu_NF, cpu_CF, z); + tcg_gen_subi_i32(cpu_NF, cpu_NF, 1); + + /* !(Z & C) */ + tcg_gen_and_i32(cpu_ZF, z, cpu_CF); + tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1); + + /* (!C & Z) << 31 -> -(Z & ~C) */ + tcg_gen_andc_i32(cpu_VF, z, cpu_CF); + tcg_gen_neg_i32(cpu_VF, cpu_VF); + + /* C | Z */ + tcg_gen_or_i32(cpu_CF, cpu_CF, z); + + tcg_temp_free_i32(z); +} + +static void gen_axflag(void) +{ + tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ + tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ + + /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */ + tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF); + + tcg_gen_movi_i32(cpu_NF, 0); + tcg_gen_movi_i32(cpu_VF, 0); +} + /* MSR (immediate) - move immediate to processor state field */ static void handle_msr_i(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int = crm) @@ -1665,6 +1707,22 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_NEXT; break; =20 + case 0x01: /* XAFlag */ + if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { + goto do_unallocated; + } + gen_xaflag(); + s->base.is_jmp =3D DISAS_NEXT; + break; + + case 0x02: /* AXFlag */ + if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { + goto do_unallocated; + } + gen_axflag(); + s->base.is_jmp =3D DISAS_NEXT; + break; + case 0x05: /* SPSel */ if (s->current_el =3D=3D 0) { goto do_unallocated; --=20 2.20.1