From nobody Sun Nov 9 20:19:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15516342966223.6981354567307108; Sun, 3 Mar 2019 09:31:36 -0800 (PST) Received: from localhost ([127.0.0.1]:42235 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UxW-0002HB-FO for importer@patchew.org; Sun, 03 Mar 2019 12:31:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45471) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UqB-0004vn-Ag for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0UqA-0001qe-7k for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:55 -0500 Received: from mail.default.ilande.uk0.bigv.io ([2001:41c9:1:41f::167]:42502) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0UqA-0001pY-0V; Sun, 03 Mar 2019 12:23:54 -0500 Received: from host86-184-243-112.range86-184.btcentralplus.com ([86.184.243.112] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h0Uq8-0003k5-CN; Sun, 03 Mar 2019 17:23:52 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Sun, 3 Mar 2019 17:23:42 +0000 Message-Id: <20190303172343.13406-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> References: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.184.243.112 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH 7/8] target/ppc: introduce vsrh_offset() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that both VSX and VMX registers are in host-endian order we can introdu= ce a vsrh_offset() function as a replacement for fpr_offset(). In addition the avrh_offset() and avrl_offset() functions can be simplified= in terms of vsrh_offset() and vsrl_offset(). Signed-off-by: Mark Cave-Ayland --- target/ppc/cpu.h | 16 ++++++++-------- target/ppc/translate.c | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index faae25a566..9f8eb0bdc0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2583,16 +2583,11 @@ static inline bool lsw_reg_in_range(int start, int = nregs, int rx) #define VsrSD(i) s64[1 - (i)] #endif =20 -static inline int fpr_offset(int i) +static inline int vsrh_offset(int i) { return offsetof(CPUPPCState, vsr[i].VsrD(0)); } =20 -static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) -{ - return (uint64_t *)((uintptr_t)env + fpr_offset(i)); -} - static inline int vsrl_offset(int i) { return offsetof(CPUPPCState, vsr[i].VsrD(1)); @@ -2603,6 +2598,11 @@ static inline int vsr_full_offset(int i) return offsetof(CPUPPCState, vsr[i].u64[0]); } =20 +static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) +{ + return (uint64_t *)((uintptr_t)env + vsrh_offset(i)); +} + static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) { return (uint64_t *)((uintptr_t)env + vsrl_offset(i)); @@ -2610,12 +2610,12 @@ static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *e= nv, int i) =20 static inline int avrh_offset(int i) { - return offsetof(CPUPPCState, vsr[32 + i].VsrD(0)); + return vsrh_offset(i + 32); } =20 static inline int avrl_offset(int i) { - return offsetof(CPUPPCState, vsr[32 + i].VsrD(1)); + return vsrl_offset(i + 32); } =20 static inline int avr_offset(int i) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f646f359e7..1c7377d588 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6677,12 +6677,12 @@ GEN_TM_PRIV_NOOP(trechkpt); =20 static inline void get_fpr(TCGv_i64 dst, int regno) { - tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); + tcg_gen_ld_i64(dst, cpu_env, vsrh_offset(regno)); } =20 static inline void set_fpr(int regno, TCGv_i64 src) { - tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); + tcg_gen_st_i64(src, cpu_env, vsrh_offset(regno)); } =20 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) --=20 2.11.0