From nobody Tue Feb 10 12:27:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155163407422649.879523981690795; Sun, 3 Mar 2019 09:27:54 -0800 (PST) Received: from localhost ([127.0.0.1]:42169 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0Utz-0007dP-5Q for importer@patchew.org; Sun, 03 Mar 2019 12:27:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45516) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UqC-0004vr-FE for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0UqB-0001s8-Jr for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:56 -0500 Received: from mail.default.ilande.uk0.bigv.io ([2001:41c9:1:41f::167]:42484) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0UqB-0001pG-Bz; Sun, 03 Mar 2019 12:23:55 -0500 Received: from host86-184-243-112.range86-184.btcentralplus.com ([86.184.243.112] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h0Uq8-0003k5-0R; Sun, 03 Mar 2019 17:23:52 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Sun, 3 Mar 2019 17:23:41 +0000 Message-Id: <20190303172343.13406-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> References: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.184.243.112 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH 6/8] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When VSX support was initially added, the fpr registers were added at offset 0 of the VSR register and the vsrl registers were added at offset 1. This is in contrast to the VMX registers (the last 32 VSX registers) whi= ch are stored in host-endian order. Switch the fpr/vsrl registers so that the lower 32 VSX registers are now al= so stored in host endian order to match the VMX registers. This ensures that T= CG vector operations involving mixed VMX and VSX registers will function correctly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 4 ++-- target/ppc/internal.h | 8 ++++---- target/ppc/machine.c | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 89651988ab..faae25a566 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2585,7 +2585,7 @@ static inline bool lsw_reg_in_range(int start, int nr= egs, int rx) =20 static inline int fpr_offset(int i) { - return offsetof(CPUPPCState, vsr[i].u64[0]); + return offsetof(CPUPPCState, vsr[i].VsrD(0)); } =20 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) @@ -2595,7 +2595,7 @@ static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env,= int i) =20 static inline int vsrl_offset(int i) { - return offsetof(CPUPPCState, vsr[i].u64[1]); + return offsetof(CPUPPCState, vsr[i].VsrD(1)); } =20 static inline int vsr_full_offset(int i) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 3ebbdf4da4..fb6f64ed1e 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -206,14 +206,14 @@ EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1,= 6, 6); =20 static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - vsr->VsrD(0) =3D env->vsr[n].u64[0]; - vsr->VsrD(1) =3D env->vsr[n].u64[1]; + vsr->VsrD(0) =3D env->vsr[n].VsrD(0); + vsr->VsrD(1) =3D env->vsr[n].VsrD(1); } =20 static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - env->vsr[n].u64[0] =3D vsr->VsrD(0); - env->vsr[n].u64[1] =3D vsr->VsrD(1); + env->vsr[n].VsrD(0) =3D vsr->VsrD(0); + env->vsr[n].VsrD(1) =3D vsr->VsrD(1); } =20 void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 756b6d2971..a92d0ad3a3 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -150,7 +150,7 @@ static int get_fpr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v =3D pv; =20 - v->u64[0] =3D qemu_get_be64(f); + v->VsrD(0) =3D qemu_get_be64(f); =20 return 0; } @@ -160,7 +160,7 @@ static int put_fpr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v =3D pv; =20 - qemu_put_be64(f, v->u64[0]); + qemu_put_be64(f, v->VsrD(0)); return 0; } =20 @@ -181,7 +181,7 @@ static int get_vsr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v =3D pv; =20 - v->u64[1] =3D qemu_get_be64(f); + v->VsrD(1) =3D qemu_get_be64(f); =20 return 0; } @@ -191,7 +191,7 @@ static int put_vsr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v =3D pv; =20 - qemu_put_be64(f, v->u64[1]); + qemu_put_be64(f, v->VsrD(1)); return 0; } =20 --=20 2.11.0