From nobody Sun Nov 9 17:55:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551633964370818.4626169656733; Sun, 3 Mar 2019 09:26:04 -0800 (PST) Received: from localhost ([127.0.0.1]:42152 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0Us9-00068Y-01 for importer@patchew.org; Sun, 03 Mar 2019 12:25:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UqA-0004vj-RP for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0UqA-0001qA-0O for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:54 -0500 Received: from mail.default.ilande.uk0.bigv.io ([2001:41c9:1:41f::167]:42494) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0Uq9-0001pQ-PO; Sun, 03 Mar 2019 12:23:53 -0500 Received: from host86-184-243-112.range86-184.btcentralplus.com ([86.184.243.112] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h0Uq6-0003k5-0h; Sun, 03 Mar 2019 17:23:50 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Sun, 3 Mar 2019 17:23:36 +0000 Message-Id: <20190303172343.13406-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> References: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.184.243.112 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH 1/8] target/ppc: introduce single fpr_offset() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Instead of having multiple copies of the offset calculation logic, move it = to a single fpr_offset() function. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 7 ++++++- target/ppc/translate.c | 4 ++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 26604ddf98..4bb4e42670 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2563,9 +2563,14 @@ static inline bool lsw_reg_in_range(int start, int n= regs, int rx) } =20 /* Accessors for FP, VMX and VSX registers */ +static inline int fpr_offset(int i) +{ + return offsetof(CPUPPCState, vsr[i].u64[0]); +} + static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) { - return &env->vsr[i].u64[0]; + return (uint64_t *)((uintptr_t)env + fpr_offset(i)); } =20 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 819221f246..3b1992faf1 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6677,12 +6677,12 @@ GEN_TM_PRIV_NOOP(trechkpt); =20 static inline void get_fpr(TCGv_i64 dst, int regno) { - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); + tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); } =20 static inline void set_fpr(int regno, TCGv_i64 src) { - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); + tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); } =20 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) --=20 2.11.0 From nobody Sun Nov 9 17:55:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551634138427728.0691406986034; Sun, 3 Mar 2019 09:28:58 -0800 (PST) Received: from localhost ([127.0.0.1]:42173 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0Uv0-0008R0-Bk for importer@patchew.org; Sun, 03 Mar 2019 12:28:54 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UqA-0004vk-VV for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0UqA-0001qS-3K for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:54 -0500 Received: from mail.default.ilande.uk0.bigv.io ([2001:41c9:1:41f::167]:42470) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0Uq9-0001oV-Rb; Sun, 03 Mar 2019 12:23:54 -0500 Received: from host86-184-243-112.range86-184.btcentralplus.com ([86.184.243.112] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h0Uq6-0003k5-Cv; Sun, 03 Mar 2019 17:23:50 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Sun, 3 Mar 2019 17:23:37 +0000 Message-Id: <20190303172343.13406-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> References: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.184.243.112 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH 2/8] target/ppc: introduce single vsrl_offset() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Instead of having multiple copies of the offset calculation logic, move it = to a single vsrl_offset() function. This commit also renames the existing get_vsr()/set_vsr() functions to get_vsrl()/set_vsrl() which better describes their purpose. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 7 ++++++- target/ppc/translate/vsx-impl.inc.c | 12 ++++++------ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 4bb4e42670..4a7df13c2d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2573,9 +2573,14 @@ static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env= , int i) return (uint64_t *)((uintptr_t)env + fpr_offset(i)); } =20 +static inline int vsrl_offset(int i) +{ + return offsetof(CPUPPCState, vsr[i].u64[1]); +} + static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) { - return &env->vsr[i].u64[1]; + return (uint64_t *)((uintptr_t)env + vsrl_offset(i)); } =20 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index e73197e717..381ae0f2e9 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1,13 +1,13 @@ /*** VSX extension = ***/ =20 -static inline void get_vsr(TCGv_i64 dst, int n) +static inline void get_vsrl(TCGv_i64 dst, int n) { - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1])); + tcg_gen_ld_i64(dst, cpu_env, vsrl_offset(n)); } =20 -static inline void set_vsr(int n, TCGv_i64 src) +static inline void set_vsrl(int n, TCGv_i64 src) { - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1])); + tcg_gen_st_i64(src, cpu_env, vsrl_offset(n)); } =20 static inline int vsr_full_offset(int n) @@ -27,7 +27,7 @@ static inline void get_cpu_vsrh(TCGv_i64 dst, int n) static inline void get_cpu_vsrl(TCGv_i64 dst, int n) { if (n < 32) { - get_vsr(dst, n); + get_vsrl(dst, n); } else { get_avr64(dst, n - 32, false); } @@ -45,7 +45,7 @@ static inline void set_cpu_vsrh(int n, TCGv_i64 src) static inline void set_cpu_vsrl(int n, TCGv_i64 src) { if (n < 32) { - set_vsr(n, src); + set_vsrl(n, src); } else { set_avr64(n - 32, src, false); } --=20 2.11.0 From nobody Sun Nov 9 17:55:24 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551634370616446.9461785475852; Sun, 3 Mar 2019 09:32:50 -0800 (PST) Received: from localhost ([127.0.0.1]:42247 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0Uyl-00036J-LE for importer@patchew.org; Sun, 03 Mar 2019 12:32:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UqB-0004vo-Ai for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0UqA-0001qY-5J for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:55 -0500 Received: from mail.default.ilande.uk0.bigv.io ([2001:41c9:1:41f::167]:42506) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0Uq9-0001pg-TJ; Sun, 03 Mar 2019 12:23:54 -0500 Received: from host86-184-243-112.range86-184.btcentralplus.com ([86.184.243.112] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h0Uq6-0003k5-Qe; Sun, 03 Mar 2019 17:23:51 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Sun, 3 Mar 2019 17:23:38 +0000 Message-Id: <20190303172343.13406-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> References: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.184.243.112 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH 3/8] target/ppc: move Vsr* macros from internal.h to cpu.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It isn't possible to include internal.h from cpu.h so move the Vsr* macros into cpu.h alongside the other VMX/VSX register access functions. Signed-off-by: Mark Cave-Ayland --- target/ppc/cpu.h | 20 ++++++++++++++++++++ target/ppc/internal.h | 19 ------------------- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 4a7df13c2d..d0580c6b6d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2563,6 +2563,26 @@ static inline bool lsw_reg_in_range(int start, int n= regs, int rx) } =20 /* Accessors for FP, VMX and VSX registers */ +#if defined(HOST_WORDS_BIGENDIAN) +#define VsrB(i) u8[i] +#define VsrSB(i) s8[i] +#define VsrH(i) u16[i] +#define VsrSH(i) s16[i] +#define VsrW(i) u32[i] +#define VsrSW(i) s32[i] +#define VsrD(i) u64[i] +#define VsrSD(i) s64[i] +#else +#define VsrB(i) u8[15 - (i)] +#define VsrSB(i) s8[15 - (i)] +#define VsrH(i) u16[7 - (i)] +#define VsrSH(i) s16[7 - (i)] +#define VsrW(i) u32[3 - (i)] +#define VsrSW(i) s32[3 - (i)] +#define VsrD(i) u64[1 - (i)] +#define VsrSD(i) s64[1 - (i)] +#endif + static inline int fpr_offset(int i) { return offsetof(CPUPPCState, vsr[i].u64[0]); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index f26a71ffcf..3ebbdf4da4 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -204,25 +204,6 @@ EXTRACT_HELPER(IMM8, 11, 8); EXTRACT_HELPER(DCMX, 16, 7); EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6); =20 -#if defined(HOST_WORDS_BIGENDIAN) -#define VsrB(i) u8[i] -#define VsrSB(i) s8[i] -#define VsrH(i) u16[i] -#define VsrSH(i) s16[i] -#define VsrW(i) u32[i] -#define VsrSW(i) s32[i] -#define VsrD(i) u64[i] -#define VsrSD(i) s64[i] -#else -#define VsrB(i) u8[15 - (i)] -#define VsrSB(i) s8[15 - (i)] -#define VsrH(i) u16[7 - (i)] -#define VsrSH(i) s16[7 - (i)] -#define VsrW(i) u32[3 - (i)] -#define VsrSW(i) s32[3 - (i)] -#define VsrD(i) u64[1 - (i)] -#define VsrSD(i) s64[1 - (i)] -#endif static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { vsr->VsrD(0) =3D env->vsr[n].u64[0]; --=20 2.11.0 From nobody Sun Nov 9 17:55:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551633964288760.469870409832; Sun, 3 Mar 2019 09:26:04 -0800 (PST) Received: from localhost ([127.0.0.1]:42149 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0Us8-00066V-SA for importer@patchew.org; Sun, 03 Mar 2019 12:25:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45464) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UqA-0004vl-Vu for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0UqA-0001qG-1C for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:54 -0500 Received: from mail.default.ilande.uk0.bigv.io ([2001:41c9:1:41f::167]:42478) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0Uq9-0001ot-PP; Sun, 03 Mar 2019 12:23:53 -0500 Received: from host86-184-243-112.range86-184.btcentralplus.com ([86.184.243.112] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h0Uq7-0003k5-7t; Sun, 03 Mar 2019 17:23:51 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Sun, 3 Mar 2019 17:23:39 +0000 Message-Id: <20190303172343.13406-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> References: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.184.243.112 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH 4/8] target/ppc: introduce avrh_offset() and avrl_offset() functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These will become more useful later, but initially use this as an aid to simplify the offset calculation by replacing the HOST_TARGET_BIGENDIAN sections with the VsrD macro. Signed-off-by: Mark Cave-Ayland --- target/ppc/cpu.h | 10 ++++++++++ target/ppc/translate.c | 24 ++++++++++-------------- 2 files changed, 20 insertions(+), 14 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d0580c6b6d..326593e0e7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2603,6 +2603,16 @@ static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *en= v, int i) return (uint64_t *)((uintptr_t)env + vsrl_offset(i)); } =20 +static inline int avrh_offset(int i) +{ + return offsetof(CPUPPCState, vsr[32 + i].VsrD(0)); +} + +static inline int avrl_offset(int i) +{ + return offsetof(CPUPPCState, vsr[32 + i].VsrD(1)); +} + static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i) { return &env->vsr[32 + i]; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3b1992faf1..f646f359e7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6687,24 +6687,20 @@ static inline void set_fpr(int regno, TCGv_i64 src) =20 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) { -#ifdef HOST_WORDS_BIGENDIAN - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, - vsr[32 + regno].u64[(high ? 0 : = 1)])); -#else - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, - vsr[32 + regno].u64[(high ? 1 : = 0)])); -#endif + if (high) { + tcg_gen_ld_i64(dst, cpu_env, avrh_offset(regno)); + } else { + tcg_gen_ld_i64(dst, cpu_env, avrl_offset(regno)); + } } =20 static inline void set_avr64(int regno, TCGv_i64 src, bool high) { -#ifdef HOST_WORDS_BIGENDIAN - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, - vsr[32 + regno].u64[(high ? 0 : = 1)])); -#else - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, - vsr[32 + regno].u64[(high ? 1 : = 0)])); -#endif + if (high) { + tcg_gen_st_i64(src, cpu_env, avrh_offset(regno)); + } else { + tcg_gen_st_i64(src, cpu_env, avrl_offset(regno)); + } } =20 #include "translate/fp-impl.inc.c" --=20 2.11.0 From nobody Sun Nov 9 17:55:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551634140742829.2067955288232; Sun, 3 Mar 2019 09:29:00 -0800 (PST) Received: from localhost ([127.0.0.1]:42175 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0Uv2-0008TA-JL for importer@patchew.org; Sun, 03 Mar 2019 12:28:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45505) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UqC-0004vq-25 for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0UqA-0001qy-Io for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:56 -0500 Received: from mail.default.ilande.uk0.bigv.io ([2001:41c9:1:41f::167]:42514) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0UqA-0001py-Bw; Sun, 03 Mar 2019 12:23:54 -0500 Received: from host86-184-243-112.range86-184.btcentralplus.com ([86.184.243.112] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h0Uq7-0003k5-JS; Sun, 03 Mar 2019 17:23:51 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Sun, 3 Mar 2019 17:23:40 +0000 Message-Id: <20190303172343.13406-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> References: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.184.243.112 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH 5/8] target/ppc: introduce avr_offset() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" All TCG vector operations require pointers to the base address of the vector rather than separate access to the top and bottom 64-bits. Convert the VMX TCG instructions to use a new avr_offset() function instead of avr64_offset(), which can itself be written as a simple wrapper onto vsr_full_offset(). After the conversion is complete then avr64_offset() can be removed since i= ts functionality is now completely within get_avr64()/set_avr64(). Signed-off-by: Mark Cave-Ayland --- target/ppc/cpu.h | 12 +++++++++++- target/ppc/translate/vmx-impl.inc.c | 27 +++++++++++---------------- target/ppc/translate/vsx-impl.inc.c | 5 ----- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 326593e0e7..89651988ab 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2598,6 +2598,11 @@ static inline int vsrl_offset(int i) return offsetof(CPUPPCState, vsr[i].u64[1]); } =20 +static inline int vsr_full_offset(int i) +{ + return offsetof(CPUPPCState, vsr[i].u64[0]); +} + static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) { return (uint64_t *)((uintptr_t)env + vsrl_offset(i)); @@ -2613,9 +2618,14 @@ static inline int avrl_offset(int i) return offsetof(CPUPPCState, vsr[32 + i].VsrD(1)); } =20 +static inline int avr_offset(int i) +{ + return vsr_full_offset(i + 32); +} + static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i) { - return &env->vsr[32 + i]; + return (ppc_avr_t *)((uintptr_t)env + avr_offset(i)); } =20 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index f1b15ae2cb..5f0c96a5e9 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -10,15 +10,10 @@ static inline TCGv_ptr gen_avr_ptr(int reg) { TCGv_ptr r =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[32 + reg].u64[0= ])); + tcg_gen_addi_ptr(r, cpu_env, avr_offset(reg)); return r; } =20 -static inline long avr64_offset(int reg, bool high) -{ - return offsetof(CPUPPCState, vsr[32 + reg].u64[(high ? 0 : 1)]); -} - #define GEN_VR_LDX(name, opc2, opc3) = \ static void glue(gen_, name)(DisasContext *ctx) = \ { = \ @@ -205,7 +200,7 @@ static void gen_mtvscr(DisasContext *ctx) } =20 val =3D tcg_temp_new_i32(); - bofs =3D avr64_offset(rB(ctx->opcode), true); + bofs =3D avr_offset(rB(ctx->opcode)); #ifdef HOST_WORDS_BIGENDIAN bofs +=3D 3 * 4; #endif @@ -284,9 +279,9 @@ static void glue(gen_, name)(DisasContext *ctx) = \ } \ \ tcg_op(vece, \ - avr64_offset(rD(ctx->opcode), true), \ - avr64_offset(rA(ctx->opcode), true), \ - avr64_offset(rB(ctx->opcode), true), \ + avr_offset(rD(ctx->opcode)), \ + avr_offset(rA(ctx->opcode)), \ + avr_offset(rB(ctx->opcode)), \ 16, 16); \ } =20 @@ -578,10 +573,10 @@ static void glue(gen_, NAME)(DisasContext *ctx) = \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ - tcg_gen_gvec_4(avr64_offset(rD(ctx->opcode), true), \ + tcg_gen_gvec_4(avr_offset(rD(ctx->opcode)), \ offsetof(CPUPPCState, vscr_sat), \ - avr64_offset(rA(ctx->opcode), true), \ - avr64_offset(rB(ctx->opcode), true), \ + avr_offset(rA(ctx->opcode)), \ + avr_offset(rB(ctx->opcode)), \ 16, 16, &g); \ } =20 @@ -755,7 +750,7 @@ static void glue(gen_, name)(DisasContext *ctx) = \ return; \ } \ simm =3D SIMM5(ctx->opcode); \ - tcg_op(avr64_offset(rD(ctx->opcode), true), 16, 16, simm); \ + tcg_op(avr_offset(rD(ctx->opcode)), 16, 16, simm); \ } =20 GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12); @@ -850,8 +845,8 @@ static void gen_vsplt(DisasContext *ctx, int vece) } =20 uimm =3D UIMM5(ctx->opcode); - bofs =3D avr64_offset(rB(ctx->opcode), true); - dofs =3D avr64_offset(rD(ctx->opcode), true); + bofs =3D avr_offset(rB(ctx->opcode)); + dofs =3D avr_offset(rD(ctx->opcode)); =20 /* Experimental testing shows that hardware masks the immediate. */ bofs +=3D (uimm << vece) & 15; diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 381ae0f2e9..7d02a235e7 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -10,11 +10,6 @@ static inline void set_vsrl(int n, TCGv_i64 src) tcg_gen_st_i64(src, cpu_env, vsrl_offset(n)); } =20 -static inline int vsr_full_offset(int n) -{ - return offsetof(CPUPPCState, vsr[n].u64[0]); -} - static inline void get_cpu_vsrh(TCGv_i64 dst, int n) { if (n < 32) { --=20 2.11.0 From nobody Sun Nov 9 17:55:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155163407422649.879523981690795; Sun, 3 Mar 2019 09:27:54 -0800 (PST) Received: from localhost ([127.0.0.1]:42169 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0Utz-0007dP-5Q for importer@patchew.org; Sun, 03 Mar 2019 12:27:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45516) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UqC-0004vr-FE for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0UqB-0001s8-Jr for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:56 -0500 Received: from mail.default.ilande.uk0.bigv.io ([2001:41c9:1:41f::167]:42484) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0UqB-0001pG-Bz; Sun, 03 Mar 2019 12:23:55 -0500 Received: from host86-184-243-112.range86-184.btcentralplus.com ([86.184.243.112] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h0Uq8-0003k5-0R; Sun, 03 Mar 2019 17:23:52 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Sun, 3 Mar 2019 17:23:41 +0000 Message-Id: <20190303172343.13406-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> References: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.184.243.112 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH 6/8] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When VSX support was initially added, the fpr registers were added at offset 0 of the VSR register and the vsrl registers were added at offset 1. This is in contrast to the VMX registers (the last 32 VSX registers) whi= ch are stored in host-endian order. Switch the fpr/vsrl registers so that the lower 32 VSX registers are now al= so stored in host endian order to match the VMX registers. This ensures that T= CG vector operations involving mixed VMX and VSX registers will function correctly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 4 ++-- target/ppc/internal.h | 8 ++++---- target/ppc/machine.c | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 89651988ab..faae25a566 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2585,7 +2585,7 @@ static inline bool lsw_reg_in_range(int start, int nr= egs, int rx) =20 static inline int fpr_offset(int i) { - return offsetof(CPUPPCState, vsr[i].u64[0]); + return offsetof(CPUPPCState, vsr[i].VsrD(0)); } =20 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) @@ -2595,7 +2595,7 @@ static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env,= int i) =20 static inline int vsrl_offset(int i) { - return offsetof(CPUPPCState, vsr[i].u64[1]); + return offsetof(CPUPPCState, vsr[i].VsrD(1)); } =20 static inline int vsr_full_offset(int i) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 3ebbdf4da4..fb6f64ed1e 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -206,14 +206,14 @@ EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1,= 6, 6); =20 static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - vsr->VsrD(0) =3D env->vsr[n].u64[0]; - vsr->VsrD(1) =3D env->vsr[n].u64[1]; + vsr->VsrD(0) =3D env->vsr[n].VsrD(0); + vsr->VsrD(1) =3D env->vsr[n].VsrD(1); } =20 static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - env->vsr[n].u64[0] =3D vsr->VsrD(0); - env->vsr[n].u64[1] =3D vsr->VsrD(1); + env->vsr[n].VsrD(0) =3D vsr->VsrD(0); + env->vsr[n].VsrD(1) =3D vsr->VsrD(1); } =20 void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 756b6d2971..a92d0ad3a3 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -150,7 +150,7 @@ static int get_fpr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v =3D pv; =20 - v->u64[0] =3D qemu_get_be64(f); + v->VsrD(0) =3D qemu_get_be64(f); =20 return 0; } @@ -160,7 +160,7 @@ static int put_fpr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v =3D pv; =20 - qemu_put_be64(f, v->u64[0]); + qemu_put_be64(f, v->VsrD(0)); return 0; } =20 @@ -181,7 +181,7 @@ static int get_vsr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v =3D pv; =20 - v->u64[1] =3D qemu_get_be64(f); + v->VsrD(1) =3D qemu_get_be64(f); =20 return 0; } @@ -191,7 +191,7 @@ static int put_vsr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v =3D pv; =20 - qemu_put_be64(f, v->u64[1]); + qemu_put_be64(f, v->VsrD(1)); return 0; } =20 --=20 2.11.0 From nobody Sun Nov 9 17:55:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15516342966223.6981354567307108; Sun, 3 Mar 2019 09:31:36 -0800 (PST) Received: from localhost ([127.0.0.1]:42235 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UxW-0002HB-FO for importer@patchew.org; Sun, 03 Mar 2019 12:31:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45471) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UqB-0004vn-Ag for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0UqA-0001qe-7k for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:55 -0500 Received: from mail.default.ilande.uk0.bigv.io ([2001:41c9:1:41f::167]:42502) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0UqA-0001pY-0V; Sun, 03 Mar 2019 12:23:54 -0500 Received: from host86-184-243-112.range86-184.btcentralplus.com ([86.184.243.112] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h0Uq8-0003k5-CN; Sun, 03 Mar 2019 17:23:52 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Sun, 3 Mar 2019 17:23:42 +0000 Message-Id: <20190303172343.13406-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> References: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.184.243.112 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH 7/8] target/ppc: introduce vsrh_offset() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that both VSX and VMX registers are in host-endian order we can introdu= ce a vsrh_offset() function as a replacement for fpr_offset(). In addition the avrh_offset() and avrl_offset() functions can be simplified= in terms of vsrh_offset() and vsrl_offset(). Signed-off-by: Mark Cave-Ayland --- target/ppc/cpu.h | 16 ++++++++-------- target/ppc/translate.c | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index faae25a566..9f8eb0bdc0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2583,16 +2583,11 @@ static inline bool lsw_reg_in_range(int start, int = nregs, int rx) #define VsrSD(i) s64[1 - (i)] #endif =20 -static inline int fpr_offset(int i) +static inline int vsrh_offset(int i) { return offsetof(CPUPPCState, vsr[i].VsrD(0)); } =20 -static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) -{ - return (uint64_t *)((uintptr_t)env + fpr_offset(i)); -} - static inline int vsrl_offset(int i) { return offsetof(CPUPPCState, vsr[i].VsrD(1)); @@ -2603,6 +2598,11 @@ static inline int vsr_full_offset(int i) return offsetof(CPUPPCState, vsr[i].u64[0]); } =20 +static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) +{ + return (uint64_t *)((uintptr_t)env + vsrh_offset(i)); +} + static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) { return (uint64_t *)((uintptr_t)env + vsrl_offset(i)); @@ -2610,12 +2610,12 @@ static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *e= nv, int i) =20 static inline int avrh_offset(int i) { - return offsetof(CPUPPCState, vsr[32 + i].VsrD(0)); + return vsrh_offset(i + 32); } =20 static inline int avrl_offset(int i) { - return offsetof(CPUPPCState, vsr[32 + i].VsrD(1)); + return vsrl_offset(i + 32); } =20 static inline int avr_offset(int i) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f646f359e7..1c7377d588 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6677,12 +6677,12 @@ GEN_TM_PRIV_NOOP(trechkpt); =20 static inline void get_fpr(TCGv_i64 dst, int regno) { - tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); + tcg_gen_ld_i64(dst, cpu_env, vsrh_offset(regno)); } =20 static inline void set_fpr(int regno, TCGv_i64 src) { - tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); + tcg_gen_st_i64(src, cpu_env, vsrh_offset(regno)); } =20 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) --=20 2.11.0 From nobody Sun Nov 9 17:55:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551634471698820.7759740508177; Sun, 3 Mar 2019 09:34:31 -0800 (PST) Received: from localhost ([127.0.0.1]:42261 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0V0N-0004Et-Jp for importer@patchew.org; Sun, 03 Mar 2019 12:34:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45473) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0UqB-0004vp-B3 for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0UqA-0001qk-8m for qemu-devel@nongnu.org; Sun, 03 Mar 2019 12:23:55 -0500 Received: from mail.default.ilande.uk0.bigv.io ([2001:41c9:1:41f::167]:42510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0UqA-0001pq-1b; Sun, 03 Mar 2019 12:23:54 -0500 Received: from host86-184-243-112.range86-184.btcentralplus.com ([86.184.243.112] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h0Uq8-0003k5-OG; Sun, 03 Mar 2019 17:23:53 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Sun, 3 Mar 2019 17:23:43 +0000 Message-Id: <20190303172343.13406-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> References: <20190303172343.13406-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.184.243.112 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH 8/8] target/ppc: simplify get_cpu_vsrh() and get_cpu_vsrl() functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that the VSX registers are all in host endian order, there is no need to go via different accessors depending upon the register number. Instead the high and low parts can be accessed directly via vsrh_offset() and vsrl_offs= et() accordingly. Signed-off-by: Mark Cave-Ayland --- target/ppc/translate/vsx-impl.inc.c | 34 ++++------------------------------ 1 file changed, 4 insertions(+), 30 deletions(-) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 7d02a235e7..43e97756a2 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1,49 +1,23 @@ /*** VSX extension = ***/ =20 -static inline void get_vsrl(TCGv_i64 dst, int n) -{ - tcg_gen_ld_i64(dst, cpu_env, vsrl_offset(n)); -} - -static inline void set_vsrl(int n, TCGv_i64 src) -{ - tcg_gen_st_i64(src, cpu_env, vsrl_offset(n)); -} - static inline void get_cpu_vsrh(TCGv_i64 dst, int n) { - if (n < 32) { - get_fpr(dst, n); - } else { - get_avr64(dst, n - 32, true); - } + tcg_gen_ld_i64(dst, cpu_env, vsrh_offset(n)); } =20 static inline void get_cpu_vsrl(TCGv_i64 dst, int n) { - if (n < 32) { - get_vsrl(dst, n); - } else { - get_avr64(dst, n - 32, false); - } + tcg_gen_ld_i64(dst, cpu_env, vsrl_offset(n)); } =20 static inline void set_cpu_vsrh(int n, TCGv_i64 src) { - if (n < 32) { - set_fpr(n, src); - } else { - set_avr64(n - 32, src, true); - } + tcg_gen_st_i64(src, cpu_env, vsrh_offset(n)); } =20 static inline void set_cpu_vsrl(int n, TCGv_i64 src) { - if (n < 32) { - set_vsrl(n, src); - } else { - set_avr64(n - 32, src, false); - } + tcg_gen_st_i64(src, cpu_env, vsrl_offset(n)); } =20 #define VSX_LOAD_SCALAR(name, operation) \ --=20 2.11.0