From nobody Sun Feb 8 12:37:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551507987193160.57046418301616; Fri, 1 Mar 2019 22:26:27 -0800 (PST) Received: from localhost ([127.0.0.1]:49127 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzy6E-0004EI-9d for importer@patchew.org; Sat, 02 Mar 2019 01:26:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzy48-0002vM-OO for qemu-devel@nongnu.org; Sat, 02 Mar 2019 01:24:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzy2C-00032x-8I for qemu-devel@nongnu.org; Sat, 02 Mar 2019 01:22:10 -0500 Received: from mail01.asahi-net.or.jp ([202.224.55.13]:48784) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzy2B-0002yH-4g for qemu-devel@nongnu.org; Sat, 02 Mar 2019 01:22:07 -0500 Received: from h61-195-96-97.vps.ablenet.jp (h61-195-96-97.vps.ablenet.jp [61.195.96.97]) (Authenticated sender: PQ4Y-STU) by mail01.asahi-net.or.jp (Postfix) with ESMTPA id E5CD410C40C; Sat, 2 Mar 2019 15:21:50 +0900 (JST) Received: from ysato.dip.jp (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by h61-195-96-97.vps.ablenet.jp (Postfix) with ESMTPSA id A6F6A24008A; Sat, 2 Mar 2019 15:21:50 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Date: Sat, 2 Mar 2019 15:21:35 +0900 Message-Id: <20190302062138.10713-9-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190302062138.10713-1-ysato@users.sourceforge.jp> References: <20190122121413.31437-1-ysato@users.sourceforge.jp> <20190302062138.10713-1-ysato@users.sourceforge.jp> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 202.224.55.13 Subject: [Qemu-devel] [PATCH RFC v3 08/11] RX62N internal serial communication interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej= 0140_rx62n.pdf?key=3D086621e01bd70347c18ea7f794aa9cc3 Signed-off-by: Yoshinori Sato --- hw/char/Makefile.objs | 2 +- hw/char/renesas_sci.c | 288 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/char/renesas_sci.h | 42 ++++++ 3 files changed, 331 insertions(+), 1 deletion(-) create mode 100644 hw/char/renesas_sci.c create mode 100644 include/hw/char/renesas_sci.h diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index c4947d7ae7..68eae7b9a5 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -15,7 +15,7 @@ common-obj-$(CONFIG_CADENCE) +=3D cadence_uart.o obj-$(CONFIG_EXYNOS4) +=3D exynos4210_uart.o obj-$(CONFIG_COLDFIRE) +=3D mcf_uart.o obj-$(CONFIG_OMAP) +=3D omap_uart.o -obj-$(CONFIG_SH4) +=3D sh_serial.o +obj-$(CONFIG_RENESAS_SCI) +=3D renesas_sci.o obj-$(CONFIG_PSERIES) +=3D spapr_vty.o obj-$(CONFIG_DIGIC) +=3D digic-uart.o obj-$(CONFIG_STM32F2XX_USART) +=3D stm32f2xx_usart.o diff --git a/hw/char/renesas_sci.c b/hw/char/renesas_sci.c new file mode 100644 index 0000000000..56d070a329 --- /dev/null +++ b/hw/char/renesas_sci.c @@ -0,0 +1,288 @@ +/* + * Renesas Serial Communication Interface + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/char/renesas_sci.h" +#include "qemu/error-report.h" + +#define freq_to_ns(freq) (1000000000LL / freq) + +static int can_receive(void *opaque) +{ + RSCIState *sci =3D RSCI(opaque); + if (sci->rx_next > qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { + return 0; + } else { + return sci->scr & 0x10; + } +} + +static void receive(void *opaque, const uint8_t *buf, int size) +{ + RSCIState *sci =3D RSCI(opaque); + sci->rdr =3D buf[0]; + if (sci->ssr & 0x40 || size > 1) { + sci->ssr |=3D 0x20; + if (sci->scr & 0x40) { + qemu_set_irq(sci->irq[ERI], 1); + } + } else { + sci->ssr |=3D 0x40; + sci->rx_next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trti= me; + if (sci->scr & 0x40) { + qemu_set_irq(sci->irq[RXI], 1); + qemu_set_irq(sci->irq[RXI], 0); + } + } +} + +static void send_byte(RSCIState *sci) +{ + if (qemu_chr_fe_backend_connected(&sci->chr)) { + qemu_chr_fe_write_all(&sci->chr, &sci->tdr, 1); + } + timer_mod(sci->timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime); + sci->ssr &=3D ~0x04; + sci->ssr |=3D 0x80; + qemu_set_irq(sci->irq[TEI], 0); + if (sci->scr & 0x80) { + qemu_set_irq(sci->irq[TXI], 1); + qemu_set_irq(sci->irq[TXI], 0); + } +} + +static void txend(void *opaque) +{ + RSCIState *sci =3D RSCI(opaque); + if ((sci->ssr & 0x80) =3D=3D 0) { + send_byte(sci); + } else { + sci->ssr |=3D 0x04; + if (sci->scr & 0x04) { + qemu_set_irq(sci->irq[TEI], 1); + } + } +} + +static void update_trtime(RSCIState *sci) +{ + static const int div[] =3D {1, 4, 16, 64}; + int w; + + w =3D (sci->smr & 0x40) ? 7 : 8; /* CHR */ + w +=3D (sci->smr >> 5) & 1; /* PE */ + w +=3D (sci->smr & 0x08) ? 2 : 1; /* STOP */ + sci->trtime =3D w * freq_to_ns(sci->input_freq) * + 32 * div[sci->smr & 0x03] * sci->brr; +} + +static void sci_write(void *opaque, hwaddr addr, uint64_t val, unsigned si= ze) +{ + hwaddr offset =3D addr & 0x07; + RSCIState *sci =3D RSCI(opaque); + int error =3D 0; + + switch (offset) { + case 0: /* SMR */ + if ((sci->scr & 0x30) =3D=3D 0) { + sci->smr =3D val; + update_trtime(sci); + } + break; + case 1: /* BRR */ + if ((sci->scr & 0x30) =3D=3D 0) { + sci->brr =3D val; + update_trtime(sci); + } + break; + case 2: /* SCR */ + sci->scr =3D val; + if (sci->scr & 0x20) { + sci->ssr |=3D 0x84; + qemu_set_irq(sci->irq[TXI], 1); + qemu_set_irq(sci->irq[TXI], 0); + } + if ((sci->scr & 0x04) =3D=3D 0) { + qemu_set_irq(sci->irq[TEI], 0); + } + if ((sci->scr & 0x40) =3D=3D 0) { + qemu_set_irq(sci->irq[ERI], 0); + } + break; + case 3: /* TDR */ + sci->tdr =3D val; + if (sci->ssr & 0x04) { + send_byte(sci); + } else{ + sci->ssr &=3D ~0x80; + } + break; + case 4: /* SSR */ + sci->ssr &=3D ~0x38 | (val & 0x38); + if (((sci->read_ssr & 0x38) ^ (sci->ssr & 0x38)) && + (sci->ssr & 0x38) =3D=3D 0) { + qemu_set_irq(sci->irq[ERI], 0); + } + break; + case 5: /* RDR */ + error =3D 1; break; + case 6: /* SCMR */ + sci->scmr =3D val; break; + case 7: /* SEMR */ + sci->semr =3D val; break; + } + + if (error) { + error_report("rsci: unsupported write request to %08lx", addr); + } +} + +static uint64_t sci_read(void *opaque, hwaddr addr, unsigned size) +{ + hwaddr offset =3D addr & 0x07; + RSCIState *sci =3D RSCI(opaque); + int error =3D 0; + switch (offset) { + case 0: /* SMR */ + return sci->smr; + case 1: /* BRR */ + return sci->brr; + case 2: /* SCR */ + return sci->scr; + case 3: /* TDR */ + return sci->tdr; + case 4: /* SSR */ + sci->read_ssr =3D sci->ssr; + return sci->ssr; + case 5: /* RDR */ + sci->ssr &=3D ~0x40; + return sci->rdr; + case 6: /* SCMR */ + return sci->scmr; + case 7: /* SEMR */ + return sci->semr; + } + + if (error) { + error_report("rsci: unsupported write request to %08lx", addr); + } + return -1; +} + +static const MemoryRegionOps sci_ops =3D { + .write =3D sci_write, + .read =3D sci_read, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static void rsci_reset(DeviceState *dev) +{ + RSCIState *sci =3D RSCI(dev); + sci->smr =3D sci->scr =3D 0x00; + sci->brr =3D 0xff; + sci->tdr =3D 0xff; + sci->rdr =3D 0x00; + sci->ssr =3D 0x84; + sci->scmr =3D 0x00; + sci->semr =3D 0x00; + sci->rx_next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); +} + +static void sci_event(void *opaque, int event) +{ + RSCIState *sci =3D RSCI(opaque); + if (event =3D=3D CHR_EVENT_BREAK) { + sci->ssr |=3D 0x10; + if (sci->scr & 0x40) { + qemu_set_irq(sci->irq[ERI], 1); + } + } +} + +static void rsci_realize(DeviceState *dev, Error **errp) +{ + RSCIState *sci =3D RSCI(dev); + + qemu_chr_fe_set_handlers(&sci->chr, can_receive, receive, + sci_event, NULL, sci, NULL, true); +} + +static void rsci_init(Object *obj) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + RSCIState *sci =3D RSCI(obj); + int i; + + memory_region_init_io(&sci->memory, OBJECT(sci), &sci_ops, + sci, "renesas-sci", 0x8); + sysbus_init_mmio(d, &sci->memory); + + for (i =3D 0; i < 4; i++) { + sysbus_init_irq(d, &sci->irq[i]); + } + sci->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, txend, sci); +} + +static const VMStateDescription vmstate_rcmt =3D { + .name =3D "renesas-sci", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_END_OF_LIST() + } +}; + +static Property rsci_properties[] =3D { + DEFINE_PROP_UINT64("input-freq", RSCIState, input_freq, 0), + DEFINE_PROP_CHR("chardev", RSCIState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void rsci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D rsci_realize; + dc->props =3D rsci_properties; + dc->vmsd =3D &vmstate_rcmt; + dc->reset =3D rsci_reset; +} + +static const TypeInfo rsci_info =3D { + .name =3D TYPE_RENESAS_SCI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RSCIState), + .instance_init =3D rsci_init, + .class_init =3D rsci_class_init, +}; + +static void rsci_register_types(void) +{ + type_register_static(&rsci_info); +} + +type_init(rsci_register_types) diff --git a/include/hw/char/renesas_sci.h b/include/hw/char/renesas_sci.h new file mode 100644 index 0000000000..47e3e7a5d7 --- /dev/null +++ b/include/hw/char/renesas_sci.h @@ -0,0 +1,42 @@ +/* + * Renesas Serial Communication Interface + * + * Copyright (c) 2018 Yoshinori Sato + * + * This code is licensed under the GPL version 2 or later. + * + */ + +#include "chardev/char-fe.h" +#include "qemu/timer.h" +#include "hw/sysbus.h" + +#define TYPE_RENESAS_SCI "renesas-sci" +#define RSCI(obj) OBJECT_CHECK(RSCIState, (obj), TYPE_RENESAS_SCI) + +#define ERI 0 +#define RXI 1 +#define TXI 2 +#define TEI 3 + +typedef struct { + SysBusDevice parent_obj; + MemoryRegion memory; + + uint8_t smr; + uint8_t brr; + uint8_t scr; + uint8_t tdr; + uint8_t ssr; + uint8_t rdr; + uint8_t scmr; + uint8_t semr; + + uint8_t read_ssr; + long long trtime; + long long rx_next; + QEMUTimer *timer; + CharBackend chr; + uint64_t input_freq; + qemu_irq irq[4]; +} RSCIState; --=20 2.11.0