From nobody Sun Feb 8 14:52:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551508268161312.60466849848945; Fri, 1 Mar 2019 22:31:08 -0800 (PST) Received: from localhost ([127.0.0.1]:49195 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzyAn-00081f-2j for importer@patchew.org; Sat, 02 Mar 2019 01:31:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzy4I-0002vM-Sn for qemu-devel@nongnu.org; Sat, 02 Mar 2019 01:24:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzy29-000306-7u for qemu-devel@nongnu.org; Sat, 02 Mar 2019 01:22:07 -0500 Received: from mail01.asahi-net.or.jp ([202.224.55.13]:48770) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzy27-0002t4-V5 for qemu-devel@nongnu.org; Sat, 02 Mar 2019 01:22:04 -0500 Received: from h61-195-96-97.vps.ablenet.jp (h61-195-96-97.vps.ablenet.jp [61.195.96.97]) (Authenticated sender: PQ4Y-STU) by mail01.asahi-net.or.jp (Postfix) with ESMTPA id A4EB310C367; Sat, 2 Mar 2019 15:21:49 +0900 (JST) Received: from ysato.dip.jp (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by h61-195-96-97.vps.ablenet.jp (Postfix) with ESMTPSA id 5E7C024008E; Sat, 2 Mar 2019 15:21:49 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Date: Sat, 2 Mar 2019 15:21:30 +0900 Message-Id: <20190302062138.10713-4-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190302062138.10713-1-ysato@users.sourceforge.jp> References: <20190122121413.31437-1-ysato@users.sourceforge.jp> <20190302062138.10713-1-ysato@users.sourceforge.jp> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 202.224.55.13 Subject: [Qemu-devel] [PATCH RFC v3 03/11] target/rx: CPU definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Yoshinori Sato --- target/rx/cpu-qom.h | 52 ++++++++++++ target/rx/cpu.c | 224 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ target/rx/cpu.h | 214 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 490 insertions(+) create mode 100644 target/rx/cpu-qom.h create mode 100644 target/rx/cpu.c create mode 100644 target/rx/cpu.h diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h new file mode 100644 index 0000000000..bad6d2c75d --- /dev/null +++ b/target/rx/cpu-qom.h @@ -0,0 +1,52 @@ +/* + * QEMU RX CPU + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef QEMU_RX_CPU_QOM_H +#define QEMU_RX_CPU_QOM_H + +#include "qom/cpu.h" + +#define TYPE_RXCPU "rxcpu" + +#define RXCPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(RXCPUClass, (klass), TYPE_RXCPU) +#define RXCPU(obj) \ + OBJECT_CHECK(RXCPU, (obj), TYPE_RXCPU) +#define RXCPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(RXCPUClass, (obj), TYPE_RXCPU) + +/* + * RXCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_reset: The parent class' reset handler. + * + * A RX CPU model. + */ +typedef struct RXCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + DeviceRealize parent_realize; + void (*parent_reset)(CPUState *cpu); + +} RXCPUClass; + +typedef struct RXCPU RXCPU; + +#endif diff --git a/target/rx/cpu.c b/target/rx/cpu.c new file mode 100644 index 0000000000..1d0a2ff03b --- /dev/null +++ b/target/rx/cpu.c @@ -0,0 +1,224 @@ +/* + * QEMU RX CPU + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "qemu-common.h" +#include "migration/vmstate.h" +#include "exec/exec-all.h" +#include "hw/loader.h" + +static void rx_cpu_set_pc(CPUState *cs, vaddr value) +{ + RXCPU *cpu =3D RXCPU(cs); + + cpu->env.pc =3D value; +} + +static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + RXCPU *cpu =3D RXCPU(cs); + + cpu->env.pc =3D tb->pc; +} + +static bool rx_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + +static void rx_cpu_reset(CPUState *s) +{ + RXCPU *cpu =3D RXCPU(s); + RXCPUClass *rcc =3D RXCPU_GET_CLASS(cpu); + CPURXState *env =3D &cpu->env; + uint32_t *resetvec; + + rcc->parent_reset(s); + + memset(env, 0, offsetof(CPURXState, end_reset_fields)); + + resetvec =3D rom_ptr(0xfffffffc, 4); + if (resetvec) { + /* In the case of kernel, it is ignored because it is not set. */ + env->pc =3D ldl_p(resetvec); + } + env->psw =3D 0x00000000; +} + +typedef struct RXCPUListState { + fprintf_function cpu_fprintf; + FILE *file; +} RXCPUListState; + +static void rx_cpu_list_entry(gpointer data, gpointer user_data) +{ + RXCPUListState *s =3D user_data; + const char *typename =3D object_class_get_name(OBJECT_CLASS(data)); + int len =3D strlen(typename) - strlen(RX_CPU_TYPE_SUFFIX); + + (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename); +} + +void rx_cpu_list(FILE *f, fprintf_function cpu_fprintf) +{ + RXCPUListState s =3D { + .cpu_fprintf =3D cpu_fprintf, + .file =3D f, + }; + GSList *list; + + list =3D object_class_get_list_sorted(TYPE_RXCPU, false); + g_slist_foreach(list, rx_cpu_list_entry, &s); + g_slist_free(list); +} + +static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc; + char *typename =3D NULL; + + typename =3D g_strdup_printf(RX_CPU_TYPE_NAME("")); + oc =3D object_class_by_name(typename); + if (oc !=3D NULL && object_class_is_abstract(oc)) { + oc =3D NULL; + } + + g_free(typename); + return oc; +} + +static void rx_cpu_realize(DeviceState *dev, Error **errp) +{ + CPUState *cs =3D CPU(dev); + RXCPUClass *rcc =3D RXCPU_GET_CLASS(dev); + Error *local_err =3D NULL; + + cpu_exec_realizefn(cs, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + cpu_reset(cs); + qemu_init_vcpu(cs); + + rcc->parent_realize(dev, errp); +} + +static void rxcpu_set_irq(void *opaque, int no, int request) +{ + RXCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + int irq =3D request & 0xff; + + static const int mask[] =3D { + [RX_CPU_IRQ] =3D CPU_INTERRUPT_HARD, + [RX_CPU_FIR] =3D CPU_INTERRUPT_FIR, + }; + if (request & 0x1000) { + cpu->env.irq =3D irq; + cpu->env.intlevel =3D (request >> 8) & 0x0f; + cpu_interrupt(cs, mask[no]); + } else + cpu_reset_interrupt(cs, mask[no]); +} + +static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + info->mach =3D bfd_mach_rx; + info->print_insn =3D print_insn_rx; +} + +static void rx_cpu_init(Object *obj) +{ + CPUState *cs =3D CPU(obj); + RXCPU *cpu =3D RXCPU(obj); + CPURXState *env =3D &cpu->env; + + cs->env_ptr =3D env; + qdev_init_gpio_in(DEVICE(cpu), rxcpu_set_irq, 2); +} + +static void rxcpu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + CPUClass *cc =3D CPU_CLASS(klass); + RXCPUClass *rcc =3D RXCPU_CLASS(klass); + + device_class_set_parent_realize(dc, rx_cpu_realize, + &rcc->parent_realize); + + rcc->parent_reset =3D cc->reset; + cc->reset =3D rx_cpu_reset; + + cc->class_by_name =3D rx_cpu_class_by_name; + cc->has_work =3D rx_cpu_has_work; + cc->do_interrupt =3D rx_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D rx_cpu_exec_interrupt; + cc->dump_state =3D rx_cpu_dump_state; + cc->set_pc =3D rx_cpu_set_pc; + cc->synchronize_from_tb =3D rx_cpu_synchronize_from_tb; + cc->gdb_read_register =3D rx_cpu_gdb_read_register; + cc->gdb_write_register =3D rx_cpu_gdb_write_register; + cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; + cc->disas_set_info =3D rx_cpu_disas_set_info; + cc->tcg_initialize =3D rx_translate_init; + + cc->gdb_num_core_regs =3D 26; +} + +static const TypeInfo rxcpu_info =3D { + .name =3D TYPE_RXCPU, + .parent =3D TYPE_CPU, + .instance_size =3D sizeof(RXCPU), + .instance_init =3D rx_cpu_init, + .abstract =3D false, + .class_size =3D sizeof(RXCPUClass), + .class_init =3D rxcpu_class_init, +}; + +static void rxcpu_register_types(void) +{ + type_register_static(&rxcpu_info); +} + +type_init(rxcpu_register_types) + +static uint32_t extable[32]; + +void rx_load_image(RXCPU *cpu, const char *filename, + uint32_t start, uint32_t size) +{ + long kernel_size; + int i; + + kernel_size =3D load_image_targphys(filename, start, size); + if (kernel_size < 0) { + fprintf(stderr, "qemu: could not load kernel '%s'\n", filename); + exit(1); + } + cpu->env.pc =3D start; + + /* setup exception trap trampoline */ + for (i =3D 0; i < 32; i++) { + extable[i] =3D 0x10 + i * 4; + } + rom_add_blob_fixed("extable", extable, sizeof(extable), 0xffffff80); +} diff --git a/target/rx/cpu.h b/target/rx/cpu.h new file mode 100644 index 0000000000..aa4229d76a --- /dev/null +++ b/target/rx/cpu.h @@ -0,0 +1,214 @@ +/* + * RX emulation definition + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RX_CPU_H +#define RX_CPU_H + +#include "qemu-common.h" +#include "cpu-qom.h" + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 + +#define CPUArchState struct CPURXState + +#include "exec/cpu-defs.h" + +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + +#define PSW_I3 27 +#define PSW_I2 26 +#define PSW_I1 25 +#define PSW_I0 24 +#define PSW_IPL PSW_I0 +#define PSW_PM 20 +#define PSW_U 17 +#define PSW_I 16 +#define PSW_O 3 +#define PSW_S 2 +#define PSW_Z 1 +#define PSW_C 0 + +#define FPSW_MASK 0xfc007cff +#define FPSW_RM_MASK 0x00000003 +#define FPSW_DN (1 << 8) +#define FPSW_CAUSE_MASK 0x000000fc +#define FPSW_CAUSE_SHIFT 2 +#define FPSW_CAUSE_V (1 << 2) +#define FPSW_CAUSE_O (1 << 3) +#define FPSW_CAUSE_Z (1 << 4) +#define FPSW_CAUSE_U (1 << 5) +#define FPSW_CAUSE_X (1 << 6) +#define FPSW_CAUSE_E (1 << 7) +#define FPSW_ENABLE_MASK 0x00007c00 +#define FPSW_ENABLE_SHIFT 10 +#define FPSW_ENABLE_V (1 << 10) +#define FPSW_ENABLE_O (1 << 11) +#define FPSW_ENABLE_Z (1 << 12) +#define FPSW_ENABLE_U (1 << 13) +#define FPSW_ENABLE_X (1 << 14) +#define FPSW_FLAG_SHIFT 26 +#define FPSW_FLAG_V 26 +#define FPSW_FLAG_O 27 +#define FPSW_FLAG_Z 28 +#define FPSW_FLAG_U 29 +#define FPSW_FLAG_X 30 +#define FPSW_FLAG_S 31 + +#define NB_MMU_MODES 1 +#define MMU_MODE0_SUFFIX _all + +#define RX_PSW_OP_NONE 0 +#define RX_PSW_OP_SUB 1 +#define RX_PSW_OP_ADD 2 +#define RX_PSW_OP_SHLL 3 +#define RX_PSW_OP_NEG 4 + +#define RX_BYTE 0 +#define RX_WORD 1 +#define RX_LONG 2 + +typedef struct memory_content { + uint32_t address; + struct memory_content *next; +} memory_content; + +struct CCop; + +typedef struct CPURXState { + /* CPU registers */ + uint32_t regs[16]; /* general registers */ + uint32_t psw; /* processor status */ + uint32_t psw_o; /* O bit of status register */ + uint32_t psw_s; /* S bit of status register */ + uint32_t psw_z; /* Z bit of status register */ + uint32_t psw_c; /* C bit of status register */ + uint32_t psw_u; + uint32_t psw_i; + uint32_t psw_pm; + uint32_t psw_ipl; + uint32_t bpsw; /* backup status */ + uint32_t bpc; /* backup pc */ + uint32_t isp; /* global base register */ + uint32_t usp; /* vector base register */ + uint32_t pc; /* program counter */ + uint32_t intb; /* interrupt vector */ + uint32_t fintv; + uint32_t fpsw; + uint64_t acc; + + /* Internal use */ + uint32_t in_sleep; + uint32_t intlevel; /* Requested interrupt level */ + uint32_t irq; /* Requested interrupt no (hard) */ + uint32_t sirq; /* Requested interrupt no (soft) */ + float_status fp_status; + + /* Flag operation */ + uint32_t psw_op; + uint32_t psw_v[3]; + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; + + CPU_COMMON + + void *ack; +} CPURXState; + +/* + * RXCPU: + * @env: #CPURXState + * + * A RX CPU + */ +struct RXCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPURXState env; +}; + +static inline RXCPU *rx_env_get_cpu(CPURXState *env) +{ + return container_of(env, RXCPU, env); +} + +#define ENV_GET_CPU(e) CPU(rx_env_get_cpu(e)) + +#define ENV_OFFSET offsetof(RXCPU, env) + +#define RX_CPU_TYPE_SUFFIX "-" TYPE_RXCPU +#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX +#define CPU_RESOLVING_TYPE TYPE_RXCPU + +void rx_cpu_do_interrupt(CPUState *cpu); +bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); +void rx_cpu_dump_state(CPUState *cpu, FILE *f, + fprintf_function cpu_fprintf, int flags); +int rx_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + +void rx_translate_init(void); +int cpu_rx_signal_handler(int host_signum, void *pinfo, + void *puc); + +void rx_cpu_list(FILE *f, fprintf_function cpu_fprintf); +void rx_load_image(RXCPU *cpu, const char *filename, + uint32_t start, uint32_t size); +void rx_cpu_pack_psw(CPURXState *env); +void rx_cpu_unpack_psw(CPURXState *env, int all); +uint32_t rx_get_psw_low(CPURXState *env); +uint32_t update_psw_o(CPURXState *env); +uint32_t psw_cond(CPURXState *env, uint32_t cond); + +#define cpu_signal_handler cpu_rx_signal_handler +#define cpu_list rx_cpu_list + +#include "exec/cpu-all.h" + +#define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0 +#define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1 + +#define RX_CPU_IRQ 0 +#define RX_CPU_FIR 1 + +static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *f= lags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D 0; +} + +static inline int cpu_mmu_index(CPURXState *env, bool ifetch) +{ + return 0; +} + +static inline uint32_t pack_psw(CPURXState *env) +{ + return (env->psw_ipl << 24) | (env->psw_pm << 20) | + (env->psw_u << 17) | (env->psw_i << 16) | + (env->psw_o << 3) | (env->psw_s << 2) | + (env->psw_z << 1) | (env->psw_c << 0); +} + +#endif /* RX_CPU_H */ --=20 2.11.0