From nobody Sun Nov 9 20:18:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155147113053713.504516179669963; Fri, 1 Mar 2019 12:12:10 -0800 (PST) Received: from localhost ([127.0.0.1]:43547 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoVq-0004i3-Hr for importer@patchew.org; Fri, 01 Mar 2019 15:12:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44660) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoPM-0004Ic-Dn for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzoPJ-0001nm-TP for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:23 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:40799) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzoPH-0001iJ-Pe for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:20 -0500 Received: by mail-pg1-x542.google.com with SMTP id u9so11929339pgo.7 for ; Fri, 01 Mar 2019 12:05:17 -0800 (PST) Received: from cloudburst.twiddle.net (cpe-72-132-238-51.dc.res.rr.com. [72.132.238.51]) by smtp.gmail.com with ESMTPSA id x8sm31869206pfn.137.2019.03.01.12.05.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Mar 2019 12:05:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eOEqjwU+gxLJhyhEjN31Tao3yE+OznWOjc56kznMM8E=; b=Jwaroq/uHmzHxhc6ANXzjlrxwhGbSaNvkLoS6aHu/mEJWhAC+HZAR2v+/4tTgvDJv0 /93uZWRTBB77Kv0S7LMR38isXa6sfjq11tcV2znGZl4yotEH7zxjt/s4Rhxf48qN8Rrv Qt7yjaQ3IIOoPL1NIyfwtrkOEulWzC2YcAkuqqwJkURUkHNhVNB0VhKgOXLxnfud3a9U 3AOohqQ2d0dGA+RI+QR9U0/id1wsa1GiGVgu2e7kboDDMgnrVVPo7g+GBFk3mdunhPvt L02deU23duLFK2dsDmb1qApFASkokMnYeWK1t5s8z1kGwTyqoP4ibArguBl+KoEgSwnq 92uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eOEqjwU+gxLJhyhEjN31Tao3yE+OznWOjc56kznMM8E=; b=ORwkBhU9O/EZE65HM9OwvNfdgJc9iIwiN2534FVSxeU9R2uWFlEEA9T4SONsvD5QE7 K8mZaywGYl0NUH3J6Pe8VPJqzJOB6HgOIQ5dN/XJnpzYVuEnENZujrAxAvlDFnepJUBS 3m9BVADMexh2YI/IOe1sa6C4L5iJdGVFXMJ0MQw4cA32FEIfGQFxc9PcRDDU38jIPwTo iVLO+BrcL3OTbmL3aW5uDBI0PucrA4Pb5aTdlaJY/uNjMNQiXxxa7bsUSnRgIjQBIpGP dYA8UnJl0K1wDt+ZQ3gO3mhE3rN/xgOQZnc13bhvDO+eE3yuWC4FFiL9Iw8YrzWwoMEc yB/Q== X-Gm-Message-State: APjAAAVJp/MPT+HdwKGfn1PGwz8Nwmv9W6mvorvNAsZlrqQzWFLduRc3 fp8yXajl26Oi7yFHYr185XYRuTw2MP4= X-Google-Smtp-Source: APXvYqwFEQWE7EljL82FDqH8jHeaDnVeQO50RHhrDISBoaKvXNEdSR1ZdKUQZh6YTBxF7YEiKwSwtw== X-Received: by 2002:a63:e553:: with SMTP id z19mr6509309pgj.331.1551470716244; Fri, 01 Mar 2019 12:05:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 1 Mar 2019 12:04:59 -0800 Message-Id: <20190301200501.16533-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190301200501.16533-1-richard.henderson@linaro.org> References: <20190301200501.16533-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 08/10] target/arm: Implement ARMv8.5-CondM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Laurent Desnogues Signed-off-by: Richard Henderson --- v2: Update ID_AA64ISAR0.TS. --- target/arm/cpu.h | 5 ++++ target/arm/cpu64.c | 2 +- target/arm/translate-a64.c | 58 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fc2909ea6d..a7aaec63d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3436,6 +3436,11 @@ static inline bool isar_feature_aa64_condm_4(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) !=3D 0; } =20 +static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >=3D 2; +} + static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index fcf79321e2..9fe0844a82 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -309,7 +309,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 49a09b58e3..c2b9e800c8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1646,6 +1646,48 @@ static void handle_sync(DisasContext *s, uint32_t in= sn, } } =20 +static void gen_xaflag(void) +{ + TCGv_i32 z =3D tcg_temp_new_i32(); + + tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); + + /* + * (!C & !Z) << 31 + * (!(C | Z)) << 31 + * ~((C | Z) << 31) + * ~-(C | Z) + * (C | Z) - 1 + */ + tcg_gen_or_i32(cpu_NF, cpu_CF, z); + tcg_gen_subi_i32(cpu_NF, cpu_NF, 1); + + /* !(Z & C) */ + tcg_gen_and_i32(cpu_ZF, z, cpu_CF); + tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1); + + /* (!C & Z) << 31 -> -(Z & ~C) */ + tcg_gen_andc_i32(cpu_VF, z, cpu_CF); + tcg_gen_neg_i32(cpu_VF, cpu_VF); + + /* C | Z */ + tcg_gen_or_i32(cpu_CF, cpu_CF, z); + + tcg_temp_free_i32(z); +} + +static void gen_axflag(void) +{ + tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ + tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ + + /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */ + tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF); + + tcg_gen_movi_i32(cpu_NF, 0); + tcg_gen_movi_i32(cpu_VF, 0); +} + /* MSR (immediate) - move immediate to processor state field */ static void handle_msr_i(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int = crm) @@ -1665,6 +1707,22 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_NEXT; break; =20 + case 0x01: /* XAFlag */ + if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { + goto do_unallocated; + } + gen_xaflag(); + s->base.is_jmp =3D DISAS_NEXT; + break; + + case 0x02: /* AXFlag */ + if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { + goto do_unallocated; + } + gen_axflag(); + s->base.is_jmp =3D DISAS_NEXT; + break; + case 0x05: /* SPSel */ if (s->current_el =3D=3D 0) { goto do_unallocated; --=20 2.17.2