From nobody Sun Nov 9 20:18:02 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551471300186496.47859821344605; Fri, 1 Mar 2019 12:15:00 -0800 (PST) Received: from localhost ([127.0.0.1]:43569 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoYa-0006vp-4h for importer@patchew.org; Fri, 01 Mar 2019 15:14:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44724) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoPd-0004kR-JN for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzoPM-0001qe-2t for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:29 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:36773) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzoPH-0001eP-Vb for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:22 -0500 Received: by mail-pf1-x441.google.com with SMTP id n22so11916212pfa.3 for ; Fri, 01 Mar 2019 12:05:09 -0800 (PST) Received: from cloudburst.twiddle.net (cpe-72-132-238-51.dc.res.rr.com. [72.132.238.51]) by smtp.gmail.com with ESMTPSA id x8sm31869206pfn.137.2019.03.01.12.05.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Mar 2019 12:05:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=e5S+wkc/GorK1btTXbXOPpamD5OJCnpi6JpWnmoa3L8=; b=y1u8B99N6ugESVQViJP/shOR4NIGwvuQHF4L+uEOZ479/H1LKM0wIFicJHahLW2MSY ka0O0FIK4SrCjUo8sbi++Mp6WHuZbyaY/0wGLvWobSwXyxq8t76mJYkcUmV7G0a+MyU2 zOF9iEcYtFXqDMwh+nixFNQk80KzI5TV0gheKc5wr8G02BH0vIllZ5822DRoEWXbS75u 14ZRFp6k9YBry66inb7veDWxjpCySwoGxuHW5e118nUUfAfjHI+k59JDibOWLhDKQpB6 7aAeCKTWnSd+YFnleOXaF0egUVIbVp/fZhIGzmbaYnPMcdslcs4i4BkeDpd9CKv/JJoA LVUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=e5S+wkc/GorK1btTXbXOPpamD5OJCnpi6JpWnmoa3L8=; b=Ychzj0shio/sUIpUH3lZCa3D8krTB10IWmLAvnybqQtpexcOgd35fHIcYDK9dxRiyI Vrvd54uEaMBBuyqp5rRsd73qUs3lIA9idU1RclUt3JdDuO7lRbXx4xSwzjj2BURCDDAi yKozfuhsInJa61YfZ7Y28bxHI18kWQ0lvH7HBe79AQZrHu3LCIBiyqNh3uK7JiN+eWHf ttaXgQy1GMWmcBRI6MGsM+cU4VwvUw3Z0bIS2uMwS75mC6ZarPR0XqJMGp0J2iOYxbvb VbjuTeG+WTAUcMVkzUl7ZiNRBQhL1wv3ExSBl5sRVbJvT65RIZhgTB13wlVFnOI9YoDy ta3w== X-Gm-Message-State: APjAAAVtWr0HHdjI5o7mnycCgAq6iLto4AInEP3m0k/CJ/21b2Jzfh8j HoTlUhU5i2c4g+DB3U0g2M7eebmkGL0= X-Google-Smtp-Source: APXvYqwrghyrXIaJWyPdryAQe0FpR15uESpVz+QOFAc6jdFXvSqZscVRqPEYAzFeiE2wK107d6USzA== X-Received: by 2002:a65:4844:: with SMTP id i4mr6314062pgs.347.1551470708259; Fri, 01 Mar 2019 12:05:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 1 Mar 2019 12:04:54 -0800 Message-Id: <20190301200501.16533-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190301200501.16533-1-richard.henderson@linaro.org> References: <20190301200501.16533-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 03/10] target/arm: Implement ARMv8.0-PredInv X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 13 ++++++++++- target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ target/arm/helper.c | 55 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 361e51143c..c822f94236 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1060,7 +1060,8 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ #define SCTLR_F (1U << 10) /* up to v6 */ -#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ +#define SCTLR_SW (1U << 10) /* v7 */ +#define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ #define SCTLR_I (1U << 12) @@ -3312,6 +3313,11 @@ static inline bool isar_feature_aa32_sb(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; } =20 +static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* @@ -3455,6 +3461,11 @@ static inline bool isar_feature_aa64_sb(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; } =20 +static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) !=3D 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ef069c268d..96f0ff0ec7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2022,6 +2022,7 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D t; =20 t =3D cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6788c0f6ff..87337b6385 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -319,6 +319,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; @@ -351,6 +352,7 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D u; =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 49ff79a146..2607d39ad1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5719,6 +5719,50 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { }; #endif =20 +static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 0) { + uint64_t sctlr =3D arm_sctlr(env, el); + if (!(sctlr & SCTLR_EnRCTX)) { + return CP_ACCESS_TRAP; + } + } else if (el =3D=3D 1) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_NV) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo predinv_reginfo[] =3D { + { .name =3D "CFP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "DVP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "CPP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + /* + * Note the AArch32 opcodes have a different OPC1. + */ + { .name =3D "CFPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "DVPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -6618,6 +6662,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, pauth_reginfo); } #endif + + /* + * While all v8.0 cpus support aarch64, QEMU does have configurations + * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max, + * which will set ID_ISAR6. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) + ? cpu_isar_feature(aa64_predinv, cpu) + : cpu_isar_feature(aa32_predinv, cpu)) { + define_arm_cp_regs(cpu, predinv_reginfo); + } } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) --=20 2.17.2