From nobody Sun Nov 9 20:18:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551471021757506.920672999831; Fri, 1 Mar 2019 12:10:21 -0800 (PST) Received: from localhost ([127.0.0.1]:43492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoU6-0002W4-Ip for importer@patchew.org; Fri, 01 Mar 2019 15:10:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44874) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoPq-00058G-3r for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzoPm-0002Dx-0j for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:51 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:41349) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzoPj-0001mu-JK for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:48 -0500 Received: by mail-pf1-x435.google.com with SMTP id d25so11902426pfn.8 for ; Fri, 01 Mar 2019 12:05:21 -0800 (PST) Received: from cloudburst.twiddle.net (cpe-72-132-238-51.dc.res.rr.com. [72.132.238.51]) by smtp.gmail.com with ESMTPSA id x8sm31869206pfn.137.2019.03.01.12.05.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Mar 2019 12:05:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GafLDqNAv1anJDaQUiHVFlVMz+oIDUkfEJC6k0M99LM=; b=zdkI3hCpUrSYz4wdRBWKILSmY6SDy7NNGhNWjF0CgNzwQxxrJnHF1vTScc69b7VhvE GoO8Q1zYmP4PRnIm+8KY3tT06qw2u7cCdvHv6HE+L9iSsJINTDqkLsWecbg0exQ3mBkU 1sfhZkUu9AgNHhGwBu26Ce5KO2+v1FpQ7M1Spc0TP4ECl5SeIM0I20fDBhHw66ZjWekk eqQuWxZxZMinaKzfDjHlVfFAc9+0tfhZ01O0yiVEFMXBECXN/Tifq/nswgc7SxicoERr 3zq0EPPMU4D30kWNkXFx5HhL+v5xAiquySXJDuUjsKfpXWs5TrQfdyy9b6qkpEZ9faef lVpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GafLDqNAv1anJDaQUiHVFlVMz+oIDUkfEJC6k0M99LM=; b=mby5usvfWmmw1kB6Z6nCdPjX1GEMYIWpJKpZPAPLx2EOIl11lj/k6OM3ByiYUP9pU+ V2WidQ/vf2ezzczCq6VUIScsg/o3CjxwYdE23s+tS21hJ8Eo3AwlnYmc8N1XBApRNd6b pjkE0SCNlJ4qd2+LmglqxfLWjMQst4zJPnqVNdvE/i9Ume2YUADwNLwKs6xHly8asfWO l7kYZEQu5co+QmlZksOI6G8ko0KfyHPl20YVjoaV04PBf8z6scO5d0m0mTe+xSeybp0q 5GR/VrALeN+9Otfjd1s3wvH9OXASLuu08kgYfGS0MhpAFo1WGr53ro7cC5Jh9cMqh5qF jj2Q== X-Gm-Message-State: APjAAAXf6NBcYpcNhYeWlQDE9mIFlRVC0oYtGWSKcjnvfRpHgBv/Jtke ktKktMmBgZrxFAnUS3pi/2F8wfd6Nkk= X-Google-Smtp-Source: APXvYqzh27WRMLB+39Ec/PYvXrKPuc58kZIEAh1/eXXJremJU35P9cyRR7y7sRNjVQkIQcQ/8RpflA== X-Received: by 2002:a63:4a0a:: with SMTP id x10mr6559779pga.325.1551470719717; Fri, 01 Mar 2019 12:05:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 1 Mar 2019 12:05:01 -0800 Message-Id: <20190301200501.16533-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190301200501.16533-1-richard.henderson@linaro.org> References: <20190301200501.16533-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::435 Subject: [Qemu-devel] [PATCH v3 10/10] target/arm: Implement ARMv8.5-FRINT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++ target/arm/helper.h | 5 ++ target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++-- target/arm/vfp_helper.c | 96 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 173 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a7aaec63d7..5f23c62132 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3476,6 +3476,11 @@ static inline bool isar_feature_aa64_predinv(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) !=3D 0; } =20 +static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) !=3D 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 583adba9b0..a09566f795 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -683,6 +683,11 @@ DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9fe0844a82..228906f267 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -321,6 +321,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 94184ea5af..8907cc950a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5721,6 +5721,20 @@ static void handle_fp_1src_single(DisasContext *s, i= nt opcode, int rd, int rn) case 0xf: /* FRINTI */ gen_fpst =3D gen_helper_rints; break; + case 0x10: /* FRINT32Z */ + rmode =3D float_round_to_zero; + gen_fpst =3D gen_helper_frint32_s; + break; + case 0x11: /* FRINT32X */ + gen_fpst =3D gen_helper_frint32_s; + break; + case 0x12: /* FRINT64Z */ + rmode =3D float_round_to_zero; + gen_fpst =3D gen_helper_frint64_s; + break; + case 0x13: /* FRINT64X */ + gen_fpst =3D gen_helper_frint64_s; + break; default: g_assert_not_reached(); } @@ -5784,6 +5798,20 @@ static void handle_fp_1src_double(DisasContext *s, i= nt opcode, int rd, int rn) case 0xf: /* FRINTI */ gen_fpst =3D gen_helper_rintd; break; + case 0x10: /* FRINT32Z */ + rmode =3D float_round_to_zero; + gen_fpst =3D gen_helper_frint32_d; + break; + case 0x11: /* FRINT32X */ + gen_fpst =3D gen_helper_frint32_d; + break; + case 0x12: /* FRINT64Z */ + rmode =3D float_round_to_zero; + gen_fpst =3D gen_helper_frint64_d; + break; + case 0x13: /* FRINT64X */ + gen_fpst =3D gen_helper_frint64_d; + break; default: g_assert_not_reached(); } @@ -5920,6 +5948,13 @@ static void disas_fp_1src(DisasContext *s, uint32_t = insn) handle_fp_fcvt(s, opcode, rd, rn, dtype, type); break; } + + case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */ + if (type > 1 || !dc_isar_feature(aa64_frint, s)) { + unallocated_encoding(s); + return; + } + /* fall through */ case 0x0 ... 0x3: case 0x8 ... 0xc: case 0xe ... 0xf: @@ -5929,14 +5964,12 @@ static void disas_fp_1src(DisasContext *s, uint32_t= insn) if (!fp_access_check(s)) { return; } - handle_fp_1src_single(s, opcode, rd, rn); break; case 1: if (!fp_access_check(s)) { return; } - handle_fp_1src_double(s, opcode, rd, rn); break; case 3: @@ -5948,13 +5981,13 @@ static void disas_fp_1src(DisasContext *s, uint32_t= insn) if (!fp_access_check(s)) { return; } - handle_fp_1src_half(s, opcode, rd, rn); break; default: unallocated_encoding(s); } break; + default: unallocated_encoding(s); break; @@ -9482,6 +9515,14 @@ static void handle_2misc_64(DisasContext *s, int opc= ode, bool u, case 0x59: /* FRINTX */ gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus); break; + case 0x1e: /* FRINT32Z */ + case 0x5e: /* FRINT32X */ + gen_helper_frint32_d(tcg_rd, tcg_rn, tcg_fpstatus); + break; + case 0x1f: /* FRINT64Z */ + case 0x5f: /* FRINT64X */ + gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus); + break; default: g_assert_not_reached(); } @@ -12132,8 +12173,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) } break; case 0xc ... 0xf: - case 0x16 ... 0x1d: - case 0x1f: + case 0x16 ... 0x1f: { /* Floating point: U, size[1] and opcode indicate operation; * size[0] indicates single or double precision. @@ -12276,6 +12316,19 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) } need_fpstatus =3D true; break; + case 0x1e: /* FRINT32Z */ + case 0x1f: /* FRINT64Z */ + need_rmode =3D true; + rmode =3D FPROUNDING_ZERO; + /* fall through */ + case 0x5e: /* FRINT32X */ + case 0x5f: /* FRINT64X */ + need_fpstatus =3D true; + if ((size =3D=3D 3 && !is_q) || !dc_isar_feature(aa64_frint, s= )) { + unallocated_encoding(s); + return; + } + break; default: unallocated_encoding(s); return; @@ -12441,6 +12494,14 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) case 0x7c: /* URSQRTE */ gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x1e: /* FRINT32Z */ + case 0x5e: /* FRINT32X */ + gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x1f: /* FRINT64Z */ + case 0x5f: /* FRINT64X */ + gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus); + break; default: g_assert_not_reached(); } diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index cc7f9f5cb1..2468fc1629 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -1174,3 +1174,99 @@ uint32_t HELPER(vjcvt)(float64 value, CPUARMState *e= nv) =20 return result; } + +/* Round a float32 to an integer that fits in int32_t or int64_t. */ +static float32 frint_s(float32 f, float_status *fpst, int intsize) +{ + int old_flags =3D get_float_exception_flags(fpst); + uint32_t exp =3D extract32(f, 23, 8); + + if (unlikely(exp =3D=3D 0xff)) { + /* NaN or Inf. */ + goto overflow; + } + + /* Round and re-extract the exponent. */ + f =3D float32_round_to_int(f, fpst); + exp =3D extract32(f, 23, 8); + + /* Validate the range of the result. */ + if (exp < 126 + intsize) { + /* abs(F) <=3D INT{N}_MAX */ + return f; + } + if (exp =3D=3D 126 + intsize) { + uint32_t sign =3D extract32(f, 31, 1); + uint32_t frac =3D extract32(f, 0, 23); + if (sign && frac =3D=3D 0) { + /* F =3D=3D INT{N}_MIN */ + return f; + } + } + + overflow: + /* + * Raise Invalid and return INT{N}_MIN as a float. Revert any + * inexact exception float32_round_to_int may have raised. + */ + set_float_exception_flags(old_flags | float_flag_invalid, fpst); + return (0x100u + 126u + intsize) << 23; +} + +float32 HELPER(frint32_s)(float32 f, void *fpst) +{ + return frint_s(f, fpst, 32); +} + +float32 HELPER(frint64_s)(float32 f, void *fpst) +{ + return frint_s(f, fpst, 64); +} + +/* Round a float64 to an integer that fits in int32_t or int64_t. */ +static float64 frint_d(float64 f, float_status *fpst, int intsize) +{ + int old_flags =3D get_float_exception_flags(fpst); + uint32_t exp =3D extract64(f, 52, 11); + + if (unlikely(exp =3D=3D 0x7ff)) { + /* NaN or Inf. */ + goto overflow; + } + + /* Round and re-extract the exponent. */ + f =3D float64_round_to_int(f, fpst); + exp =3D extract64(f, 52, 11); + + /* Validate the range of the result. */ + if (exp < 1022 + intsize) { + /* abs(F) <=3D INT{N}_MAX */ + return f; + } + if (exp =3D=3D 1022 + intsize) { + uint64_t sign =3D extract64(f, 63, 1); + uint64_t frac =3D extract64(f, 0, 52); + if (sign && frac =3D=3D 0) { + /* F =3D=3D INT{N}_MIN */ + return f; + } + } + + overflow: + /* + * Raise Invalid and return INT{N}_MIN as a float. Revert any + * inexact exception float64_round_to_int may have raised. + */ + set_float_exception_flags(old_flags | float_flag_invalid, fpst); + return (uint64_t)(0x800 + 1022 + intsize) << 52; +} + +float64 HELPER(frint32_d)(float64 f, void *fpst) +{ + return frint_d(f, fpst, 32); +} + +float64 HELPER(frint64_d)(float64 f, void *fpst) +{ + return frint_d(f, fpst, 64); +} --=20 2.17.2