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[72.132.238.51]) by smtp.gmail.com with ESMTPSA id x8sm31869206pfn.137.2019.03.01.12.05.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Mar 2019 12:05:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=snPPjJnUHGdCTSecn79/tXDjxGHKZDIkeDVTp9ppzI0=; b=vM+8NDRW8LCjws/XYTWWGW9o4olT/16N6snh2uHKpWdzPJF8wH93CvoIwOzWImIqAx qWORrWziVPT4LZjxq9Otyy1fchV6iSplwKDLMal9sIo+iXIL+eGjE4lpVlTT9BE4J3Wk xKjty4dgeawocO8Vj8/j8UArDD+ztAUdBTn+KyL/kpEj04lUmZcRc70YVfDQY5zlHsjf wvpfRClShd+5AEZpwSaNCsTiYiicqawGHguPClcbdFOpJolBApX2zja9BreSKL8Ia8xK E8O7uC81VsBX6x6R9VMLh2fhbuZCDpjHBpWMiv4GhPolkF0J/YA42xhHZqDab7bJa889 ZBvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=snPPjJnUHGdCTSecn79/tXDjxGHKZDIkeDVTp9ppzI0=; b=oElHPuJGu1B3dkHz45+MKEWFkKVyiUPVK9+OVo5sjkXCJqJeQVoxTzar09hAV/UBgz /URwo95z5SvfUbojn4dlk2wF2vlEhmNGcquzHwKM4mhbjZ/QSqj7DtkcLoSyIJLVt2/I lQC02BNDf9iNjo6yFY8zyZciaSWMw2pVsWPH1FM9P0mbXyOjpJmyQ5hnBezda3Van+Pz mWiLdGgZ0dQMNK8qTup3l7rpBJdpayU8XusQkhFX45TkkZdARy6A7eeyv0WpLRTxftUT hgYc/mZb6SCzAlEjR8NaSSer4WrQcOb8KmlB1YkuWpcmJVeBFLoAiXTXRb5irO52Ye3H wAPg== X-Gm-Message-State: APjAAAXhq6C/C03g3D/0UfeJUFhzVh10WxXLq2nIbXrjqRAwnkT8CEI5 35Yb6XpVZYv7G2mX+IOopewkkCnynnw= X-Google-Smtp-Source: AHgI3IaRkBHdM3C/ibua6D/M3PNXqmzDtG8JSogtHLrcvDoJgbtgVwfFkIdBS2ugJ+3ebVQEDCUqgg== X-Received: by 2002:a62:3990:: with SMTP id u16mr7379475pfj.80.1551470704931; Fri, 01 Mar 2019 12:05:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 1 Mar 2019 12:04:52 -0800 Message-Id: <20190301200501.16533-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190301200501.16533-1-richard.henderson@linaro.org> References: <20190301200501.16533-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 01/10] target/arm: Split out arm_sctlr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Minimize the number of places that will need updating when the virtual host extensions are added. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 26 ++++++++++++++++---------- target/arm/helper.c | 8 ++------ 2 files changed, 18 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 36cd365efa..67b06bfad0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3042,11 +3042,20 @@ static inline bool arm_sctlr_b(CPUARMState *env) (env->cp15.sctlr_el[1] & SCTLR_B) !=3D 0; } =20 +static inline uint64_t arm_sctlr(CPUARMState *env, int el) +{ + if (el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + return env->cp15.sctlr_el[1]; + } else { + return env->cp15.sctlr_el[el]; + } +} + + /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) { - int cur_el; - /* In 32bit endianness is determined by looking at CPSR's E bit */ if (!is_a64(env)) { return @@ -3065,15 +3074,12 @@ static inline bool arm_cpu_data_is_big_endian(CPUAR= MState *env) arm_sctlr_b(env) || #endif ((env->uncached_cpsr & CPSR_E) ? 1 : 0); + } else { + int cur_el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, cur_el); + + return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) !=3D 0; } - - cur_el =3D arm_current_el(env); - - if (cur_el =3D=3D 0) { - return (env->cp15.sctlr_el[1] & SCTLR_E0E) !=3D 0; - } - - return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) !=3D 0; } =20 #include "exec/cpu-all.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 1fa282a7fc..49ff79a146 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12854,12 +12854,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } =20 - if (current_el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr =3D env->cp15.sctlr_el[1]; - } else { - sctlr =3D env->cp15.sctlr_el[current_el]; - } + sctlr =3D arm_sctlr(env, current_el); + if (cpu_isar_feature(aa64_pauth, cpu)) { /* * In order to save space in flags, we record only whether --=20 2.17.2 From nobody Sun Nov 9 17:51:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551470843158963.2225677200192; Fri, 1 Mar 2019 12:07:23 -0800 (PST) Received: from localhost ([127.0.0.1]:43461 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoRA-0006SL-Mn for importer@patchew.org; Fri, 01 Mar 2019 15:07:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44598) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoPH-0004At-Pq for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzoPF-0001jA-P1 for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:19 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:38301) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzoP9-0001cf-UQ for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:15 -0500 Received: by mail-pg1-x543.google.com with SMTP id m2so11930978pgl.5 for ; Fri, 01 Mar 2019 12:05:08 -0800 (PST) Received: from cloudburst.twiddle.net (cpe-72-132-238-51.dc.res.rr.com. [72.132.238.51]) by smtp.gmail.com with ESMTPSA id x8sm31869206pfn.137.2019.03.01.12.05.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Mar 2019 12:05:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kTul6r+YHLG/twWO20Fci4nsTs7i/YjyXbAZy8P0wPU=; b=EwT0Wl00W4Zta4lfHyhL717d4SIshQWoluiENA5OWQ+7DDUzD5zDQfZWXMhiFprvzD ZfurlKcLKa6OshXgqOAKuWtLKDSLIgeChog0MzUuV2ExIm79AvxUljKe5o5I1Fx1elK8 tkCRxs2aGu3CPJpybgifzhJqnqahozG/IkADpJ3INmcQrfa7NScbgYLLq2e63WfW0Yv1 33BeO7zUHWAZ0W4a0Ma/FM1JE97bc/T7/1BjZX9r/w2/2vwTcDqJ25U1GNTgegPFxqWN Fav1Hu4aQTMmA9SXSOx1q/WK4oP7JMIzxuWq3O9NAhkxheOSqkDcNUguypNTB3sJDgS+ A2Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kTul6r+YHLG/twWO20Fci4nsTs7i/YjyXbAZy8P0wPU=; b=rU2nPCyN/PsNxsbNXKrurLZCbDWeKmzYygKd/J+S53zjxpM/jQeC1CZ7a6UYSLBkGu 7vPsRFS0VEUcEckEjgyFjeW5vO85UqIeP1e/jiI1FUV1x/S38B74pFTmxr+t5yIfFqAl Pfpp66yBBwaIWEHkdgoxB4hY043CLWWHt495a2Uk8KGekIApLkoI3PLXlFJtQGYQgZVo V8wT4gBjAJsDh+1j7AzFEJzVsEejR+a1T++LnhT2Ss9vv99S5o6LtKRzahayKcAxjiM5 qeOrpPQXWJib4Ql1HixzOEKy04ImGbCfGrTst0pWFTeCLuqkA4BvrZcFwDYEus7C0zg7 1ejA== X-Gm-Message-State: AHQUAuacuJV15asrwOJyZrm+d0LBCRe+bgfRu0FToeXY8Rd80dR2dWtc woK4Qyn4qBao1v0f3q4XU+YB6+rfHyM= X-Google-Smtp-Source: AHgI3IZJ6xiUfFMZCaIHL4FonM8XgPMj1ORwDvTFifLixpIuUGjfCys+1Beed+jzaAtM7DJugoEOSg== X-Received: by 2002:aa7:80c8:: with SMTP id a8mr7279156pfn.27.1551470706938; Fri, 01 Mar 2019 12:05:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 1 Mar 2019 12:04:53 -0800 Message-Id: <20190301200501.16533-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190301200501.16533-1-richard.henderson@linaro.org> References: <20190301200501.16533-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 02/10] target/arm: Implement ARMv8.0-SB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++++++ linux-user/elfload.c | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ target/arm/translate-a64.c | 14 ++++++++++++++ target/arm/translate.c | 22 ++++++++++++++++++++++ 6 files changed, 50 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 67b06bfad0..361e51143c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3307,6 +3307,11 @@ static inline bool isar_feature_aa32_fhm(const ARMIS= ARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) !=3D 0; } =20 +static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* @@ -3445,6 +3450,11 @@ static inline bool isar_feature_aa64_pauth(const ARM= ISARegisters *id) FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) !=3D 0; } =20 +static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index b9f7cbbdc1..6cfebe1446 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -604,6 +604,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM); GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); + GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); =20 #undef GET_FEATURE_ID =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 54b61f917b..ef069c268d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2021,6 +2021,7 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); cpu->isar.id_isar6 =3D t; =20 t =3D cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1b0c427277..6788c0f6ff 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -318,6 +318,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; @@ -349,6 +350,7 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); cpu->isar.id_isar6 =3D u; =20 /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d3c8eaf089..4aa5a307e4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1637,7 +1637,21 @@ static void handle_sync(DisasContext *s, uint32_t in= sn, reset_btype(s); gen_goto_tb(s, 0, s->pc); return; + + case 7: /* SB */ + if (crm !=3D 0 || !dc_isar_feature(aa64_sb, s)) { + goto do_unallocated; + } + /* + * TODO: There is no speculation barrier opcode for TCG; + * MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc); + return; + default: + do_unallocated: unallocated_encoding(s); return; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 8f7f5b95aa..61adefb328 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9282,6 +9282,17 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) */ gen_goto_tb(s, 0, s->pc & ~1); return; + case 7: /* sb */ + if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { + goto illegal_op; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc & ~1); + return; default: goto illegal_op; } @@ -11900,6 +11911,17 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) */ gen_goto_tb(s, 0, s->pc & ~1); break; + case 7: /* sb */ + if ((insn & 0xf) || !dc_isar_feature(aa32_sb, = s)) { + goto illegal_op; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc & ~1); + break; default: goto illegal_op; } --=20 2.17.2 From nobody Sun Nov 9 17:51:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 03/10] target/arm: Implement ARMv8.0-PredInv X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 13 ++++++++++- target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ target/arm/helper.c | 55 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 361e51143c..c822f94236 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1060,7 +1060,8 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ #define SCTLR_F (1U << 10) /* up to v6 */ -#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ +#define SCTLR_SW (1U << 10) /* v7 */ +#define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ #define SCTLR_I (1U << 12) @@ -3312,6 +3313,11 @@ static inline bool isar_feature_aa32_sb(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; } =20 +static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* @@ -3455,6 +3461,11 @@ static inline bool isar_feature_aa64_sb(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; } =20 +static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) !=3D 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ef069c268d..96f0ff0ec7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2022,6 +2022,7 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D t; =20 t =3D cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6788c0f6ff..87337b6385 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -319,6 +319,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; @@ -351,6 +352,7 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D u; =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 49ff79a146..2607d39ad1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5719,6 +5719,50 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { }; #endif =20 +static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 0) { + uint64_t sctlr =3D arm_sctlr(env, el); + if (!(sctlr & SCTLR_EnRCTX)) { + return CP_ACCESS_TRAP; + } + } else if (el =3D=3D 1) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_NV) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo predinv_reginfo[] =3D { + { .name =3D "CFP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "DVP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "CPP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + /* + * Note the AArch32 opcodes have a different OPC1. + */ + { .name =3D "CFPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "DVPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -6618,6 +6662,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, pauth_reginfo); } #endif + + /* + * While all v8.0 cpus support aarch64, QEMU does have configurations + * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max, + * which will set ID_ISAR6. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) + ? cpu_isar_feature(aa64_predinv, cpu) + : cpu_isar_feature(aa32_predinv, cpu)) { + define_arm_cp_regs(cpu, predinv_reginfo); + } } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) --=20 2.17.2 From nobody Sun Nov 9 17:51:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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[72.132.238.51]) by smtp.gmail.com with ESMTPSA id x8sm31869206pfn.137.2019.03.01.12.05.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Mar 2019 12:05:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SVxej404JeqYSoeOtDsixmlnz9jOeVJ+T9kAKItyhFs=; b=B8+RVJx1di4Z6gnfT5wsl+WXyIedlNuoPefZ1vDcpQN4muzBA1/c0aqaPKJKR1NjYx bXugzOJzs5vVv1rJ7LvI6PQnbJVi25CCyKM6BI7GFMteyJ/sCzZPPkf+U75oelfhxViH 2jPkXA4jFQ4ChAZtvI+VXRVHTGdhOZXTv1lzfkQm2Fc4g6exU/EleAUOSkjfnNnee7WX qC7HOzZkQtH3TTKIKZTTPZXifB5N9vhl3F0mxr2zmeXAlsJfIIGAo49JMP4R2mDULEfK j0C9Mk/1Wvw0nkHltL9Iky1zvRc+D14OFcWktkaqDWCTYaG5KfZwSqLlFpNhj87rqIL6 iDaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SVxej404JeqYSoeOtDsixmlnz9jOeVJ+T9kAKItyhFs=; b=AQJj2frw5cEIhOJD0US6DG6hPBAIlwd1ySSwegVX2x+PD+45Ne+5hkSZEfkaUck4h0 vbcJb/ni5RgvbbsOwzW3bBpemqI+rCfQRk/DoK+H7rdxC5d1LzG0i3zFsuXpjuaXC0mu 3jSpZ3LLILYHCWP+vNVOVyJ5OVnLNrrtpmAbnr3dI93Gwkmr/ueeOLawrfqB7bXLXQbJ bRGaNYHXAFWH4XRePdKM61sijSIW0p2hpfwPeR25LeiXsICTXZ8oj+3tIxZrokABcGMq rQICibzCmmUl47VMGvMi5T6XeA5ajQYWtljAiTGmZPhkdzVD3x9aEEapd20SrjfrvYmp lG1g== X-Gm-Message-State: APjAAAVYb3r7WTJuHS0LDgBRZD0CN3Uk0ek0x0Xy6YL45rNQrt5x7w3o Uq65SPtPlAPhj8LlzCM+c7YZ0EtBOMQ= X-Google-Smtp-Source: APXvYqz8qTiHw8ZC3RQ9XShg8p/U5Yeu5Lup7rgK85XR621Ew9BQpeN72W9ChfedZeoGePOMCV99+A== X-Received: by 2002:a62:4287:: with SMTP id h7mr7527105pfd.110.1551470709837; Fri, 01 Mar 2019 12:05:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 1 Mar 2019 12:04:55 -0800 Message-Id: <20190301200501.16533-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190301200501.16533-1-richard.henderson@linaro.org> References: <20190301200501.16533-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 04/10] target/arm: Split helper_msr_i_pstate into 3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The EL0+UMA check is unique to DAIF. While SPSel had avoided the check by nature of already checking EL >=3D 1, the other post v8.0 extensions to MSR (imm) allow EL0 and do not require UMA. Avoid the unconditional write to pc and use raise_exception_ra to unwind. Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 3 +++ target/arm/helper.h | 1 - target/arm/internals.h | 15 ++++++++++++++ target/arm/helper-a64.c | 30 +++++++++++++++++++++++++++ target/arm/op_helper.c | 42 -------------------------------------- target/arm/translate-a64.c | 41 ++++++++++++++++++++++--------------- 6 files changed, 73 insertions(+), 59 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index aff8d6c9f3..a915c1247f 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -19,6 +19,9 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_2(msr_i_spsel, void, env, i32) +DEF_HELPER_2(msr_i_daifset, void, env, i32) +DEF_HELPER_2(msr_i_daifclear, void, env, i32) DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) diff --git a/target/arm/helper.h b/target/arm/helper.h index d363904278..6f0f386926 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -77,7 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) =20 -DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) DEF_HELPER_1(clear_pstate_ss, void, env) =20 DEF_HELPER_2(get_r13_banked, i32, env, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index a4bd1becb7..587a1ddf58 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -968,4 +968,19 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *e= nv, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); =20 +static inline int exception_target_el(CPUARMState *env) +{ + int target_el =3D MAX(1, arm_current_el(env)); + + /* + * No such thing as secure EL1 if EL3 is aarch32, + * so update the target EL to EL3 in this case. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el =3D=3D = 1) { + target_el =3D 3; + } + + return target_el; +} + #endif diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 70850e564d..796ef34b55 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -61,6 +61,36 @@ uint64_t HELPER(rbit64)(uint64_t x) return revbit64(x); } =20 +void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm) +{ + update_spsel(env, imm); +} + +static void daif_check(CPUARMState *env, uint32_t op, + uint32_t imm, uintptr_t ra) +{ + /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ + if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { + raise_exception_ra(env, EXCP_UDEF, + syn_aa64_sysregtrap(0, extract32(op, 0, 3), + extract32(op, 3, 3), 4, + imm, 0x1f, 0), + exception_target_el(env), ra); + } +} + +void HELPER(msr_i_daifset)(CPUARMState *env, uint32_t imm) +{ + daif_check(env, 0x1e, imm, GETPC()); + env->daif |=3D (imm << 6) & PSTATE_DAIF; +} + +void HELPER(msr_i_daifclear)(CPUARMState *env, uint32_t imm) +{ + daif_check(env, 0x1f, imm, GETPC()); + env->daif &=3D ~((imm << 6) & PSTATE_DAIF); +} + /* Convert a softfloat float_relation_ (as returned by * the float*_compare functions) to the correct ARM * NZCV flag state. diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c998eadfaa..c5721a866d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -68,20 +68,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp,= uint32_t syndrome, cpu_loop_exit_restore(cs, ra); } =20 -static int exception_target_el(CPUARMState *env) -{ - int target_el =3D MAX(1, arm_current_el(env)); - - /* No such thing as secure EL1 if EL3 is aarch32, so update the target= EL - * to EL3 in this case. - */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el =3D=3D = 1) { - target_el =3D 3; - } - - return target_el; -} - uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, uint32_t maxindex) { @@ -875,34 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *= rip) return res; } =20 -void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) -{ - /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set. - * Note that SPSel is never OK from EL0; we rely on handle_msr_i() - * to catch that case at translate time. - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { - uint32_t syndrome =3D syn_aa64_sysregtrap(0, extract32(op, 0, 3), - extract32(op, 3, 3), 4, - imm, 0x1f, 0); - raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)= ); - } - - switch (op) { - case 0x05: /* SPSel */ - update_spsel(env, imm); - break; - case 0x1e: /* DAIFSet */ - env->daif |=3D (imm << 6) & PSTATE_DAIF; - break; - case 0x1f: /* DAIFClear */ - env->daif &=3D ~((imm << 6) & PSTATE_DAIF); - break; - default: - g_assert_not_reached(); - } -} - void HELPER(clear_pstate_ss)(CPUARMState *env) { env->pstate &=3D ~PSTATE_SS; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4aa5a307e4..1e49d33365 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1661,29 +1661,38 @@ static void handle_sync(DisasContext *s, uint32_t i= nsn, static void handle_msr_i(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int = crm) { + TCGv_i32 t1; int op =3D op1 << 3 | op2; + + /* End the TB by default, chaining is ok. */ + s->base.is_jmp =3D DISAS_TOO_MANY; + switch (op) { case 0x05: /* SPSel */ if (s->current_el =3D=3D 0) { - unallocated_encoding(s); - return; + goto do_unallocated; } - /* fall through */ - case 0x1e: /* DAIFSet */ - case 0x1f: /* DAIFClear */ - { - TCGv_i32 tcg_imm =3D tcg_const_i32(crm); - TCGv_i32 tcg_op =3D tcg_const_i32(op); - gen_a64_set_pc_im(s->pc - 4); - gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); - tcg_temp_free_i32(tcg_imm); - tcg_temp_free_i32(tcg_op); - /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ - gen_a64_set_pc_im(s->pc); - s->base.is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); + t1 =3D tcg_const_i32(crm & PSTATE_SP); + gen_helper_msr_i_spsel(cpu_env, t1); + tcg_temp_free_i32(t1); break; - } + + case 0x1e: /* DAIFSet */ + t1 =3D tcg_const_i32(crm); + gen_helper_msr_i_daifset(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + + case 0x1f: /* DAIFClear */ + t1 =3D tcg_const_i32(crm); + gen_helper_msr_i_daifclear(cpu_env, t1); + tcg_temp_free_i32(t1); + /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ + s->base.is_jmp =3D DISAS_UPDATE; + break; + default: + do_unallocated: unallocated_encoding(s); return; } --=20 2.17.2 From nobody Sun Nov 9 17:51:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551470847458606.7284021257574; Fri, 1 Mar 2019 12:07:27 -0800 (PST) Received: from localhost ([127.0.0.1]:43463 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoRF-0006eD-8y for importer@patchew.org; Fri, 01 Mar 2019 15:07:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44646) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoPL-0004HR-S5 for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzoPH-0001mG-T4 for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:21 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:41668) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzoPG-0001g0-CA for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:19 -0500 Received: by mail-pl1-x62a.google.com with SMTP id y5so11968509plk.8 for ; Fri, 01 Mar 2019 12:05:12 -0800 (PST) Received: from cloudburst.twiddle.net (cpe-72-132-238-51.dc.res.rr.com. [72.132.238.51]) by smtp.gmail.com with ESMTPSA id x8sm31869206pfn.137.2019.03.01.12.05.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Mar 2019 12:05:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5II3W0GCv38vy4xT1Ex+ISMHLuNEGK1jNjKYydxihwE=; b=MerERbuaofV26kXjUh1K6BayADEgmgDlWIYurPPlBSxNoH/lzMh0UWecdxMeInrsA6 82AlH/vRCtbgC17BeVNK9RW1c8aTRwQVZn7CqFHA+EcCf/7H9gNoNFqa0tSV7guN8zp/ jHoG8sEITstUzBn0FVXyZfYPJEtDKZpvYgU+iBrq7A7QhVlU3G+Z+NyVtRc7OIoN77S2 cL+K7jD9aBHu5YVg1tE9qJdN0H67cSZ/cFpFyb7kk3O+Vkry/9VIxtFliMnwfBt6JksK eH2z/BmSKdoX8ge0J2JGfLoNBDGt6NYJ0Yb705xfLIkx5+vG8EIvlWUMxQlagacNjiB8 uV0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5II3W0GCv38vy4xT1Ex+ISMHLuNEGK1jNjKYydxihwE=; b=fOxHAvW2HkP8Kk0uGuAqv5/2fDktSeyDhPK9PpH2ZkMSqBc31o8Or6hhn21DV4L3qh VTaezCXYTUb8SCWGeWolNayxjJtb2wNt9vk/ZpBd8u9VWaPhRhdW2p0kiUmpNG7nBHJG xA4CDQb1cQuItlajZtb9bN7PYYoBoIwCpw76iYcVeaWAOpihTwU1xv9KMVOLzIhZKOYw bwpnKksa5zyV07dMykuIJSVo8yS8rMusWc5avvywZ6LoDbHOVT3FNVLwk9Ps2YI9tDfI BTl4bA6lWaxxCc1Jxq6U7veOur9Ti7TQxd6z7m3EODxmIt7tXyRgTEHoZmclHBuiHpSB 46Zw== X-Gm-Message-State: APjAAAVkBoObMPj1O3rADOLRTUfx1QL3x4imxZitiMN4ODonHHwh/8ED JZq5DMw4CTLSTTZ7N9UWt9qfEHQlLts= X-Google-Smtp-Source: APXvYqzc3jRxIDCfpNcTYyHcDzcv2qqByABqjQW9TsYuk8pzbnqAOc89T36pat9TV2bPf71w4TFukA== X-Received: by 2002:a17:902:b416:: with SMTP id x22mr7326291plr.285.1551470711499; Fri, 01 Mar 2019 12:05:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 1 Mar 2019 12:04:56 -0800 Message-Id: <20190301200501.16533-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190301200501.16533-1-richard.henderson@linaro.org> References: <20190301200501.16533-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62a Subject: [Qemu-devel] [PATCH v3 05/10] target/arm: Add set/clear_pstate_bits, share gen_ss_advance X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We do not need an out-of-line helper for manipulating bits in pstate. While changing things, share the implementation of gen_ss_advance. Signed-off-by: Richard Henderson --- v3: Assert no manual change to CACHED_PSTATE_BITS, merged in from a previously separate patch. --- target/arm/helper.h | 2 -- target/arm/translate.h | 34 ++++++++++++++++++++++++++++++++++ target/arm/op_helper.c | 5 ----- target/arm/translate-a64.c | 11 ----------- target/arm/translate.c | 11 ----------- 5 files changed, 34 insertions(+), 29 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 6f0f386926..583adba9b0 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -77,8 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) =20 -DEF_HELPER_1(clear_pstate_ss, void, env) - DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) =20 diff --git a/target/arm/translate.h b/target/arm/translate.h index f25fe75685..912cc2a4a5 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -202,6 +202,40 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } =20 +/* Set bits within PSTATE. */ +static inline void set_pstate_bits(uint32_t bits) +{ + TCGv_i32 p =3D tcg_temp_new_i32(); + + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_ori_i32(p, p, bits); + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(p); +} + +/* Clear bits within PSTATE. */ +static inline void clear_pstate_bits(uint32_t bits) +{ + TCGv_i32 p =3D tcg_temp_new_i32(); + + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_andi_i32(p, p, ~bits); + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(p); +} + +/* If the singlestep state is Active-not-pending, advance to Active-pendin= g. */ +static inline void gen_ss_advance(DisasContext *s) +{ + if (s->ss_active) { + s->pstate_ss =3D 0; + clear_pstate_bits(PSTATE_SS); + } +} =20 /* Vector operations shared between ARM and AArch64. */ extern const GVecGen3 bsl_op; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c5721a866d..8698b4dc83 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -861,11 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *= rip) return res; } =20 -void HELPER(clear_pstate_ss)(CPUARMState *env) -{ - env->pstate &=3D ~PSTATE_SS; -} - void HELPER(pre_hvc)(CPUARMState *env) { ARMCPU *cpu =3D arm_env_get_cpu(env); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1e49d33365..eaeb43577d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -421,17 +421,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, i= nt offset, s->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_ss_advance(DisasContext *s) -{ - /* If the singlestep state is Active-not-pending, advance to - * Active-pending. - */ - if (s->ss_active) { - s->pstate_ss =3D 0; - gen_helper_clear_pstate_ss(cpu_env); - } -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. Move from Active-not-pending diff --git a/target/arm/translate.c b/target/arm/translate.c index 61adefb328..57b1b20287 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -298,17 +298,6 @@ static void gen_exception(int excp, uint32_t syndrome,= uint32_t target_el) tcg_temp_free_i32(tcg_excp); } =20 -static void gen_ss_advance(DisasContext *s) -{ - /* If the singlestep state is Active-not-pending, advance to - * Active-pending. - */ - if (s->ss_active) { - s->pstate_ss =3D 0; - gen_helper_clear_pstate_ss(cpu_env); - } -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. Move from Active-not-pending --=20 2.17.2 From nobody Sun Nov 9 17:51:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551471004711508.9133870223724; Fri, 1 Mar 2019 12:10:04 -0800 (PST) Received: from localhost ([127.0.0.1]:43488 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoTp-0002FX-Fv for importer@patchew.org; Fri, 01 Mar 2019 15:10:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoPq-00058D-3v for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzoPm-0002Dp-1h for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:51 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:43172) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzoPj-0001gz-HH for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:48 -0500 Received: by mail-pf1-x42a.google.com with SMTP id q17so11895252pfh.10 for ; Fri, 01 Mar 2019 12:05:14 -0800 (PST) Received: from cloudburst.twiddle.net (cpe-72-132-238-51.dc.res.rr.com. [72.132.238.51]) by smtp.gmail.com with ESMTPSA id x8sm31869206pfn.137.2019.03.01.12.05.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Mar 2019 12:05:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7E29T0HDlFgU1q0mOVCwGp4O+vEXm9+HF8E2P+7ECrw=; b=OZJdylyriVQkrsJgxYoBQuZ6G1bXa+MVszDqkFN3hitETosqtYhpvgMhs6Hgun4beP 2dwKUCAV/mjd1rb7A+fjRvlgHeFWkBm1xb0ICJMc2bY60ShJ6n+Rz7fXUJEdxHQaBma/ pqdnoBN9nFyK6NK406CqcAZ5wso24+IyruJNvxM+cT0/+q6oyNqXkpTUXtkGKh+KEme2 QzTxQwbs99PYyrwoJxXVga9rzKs8hLWKMiW885Mqh3FsGE+4XaMdjyUIMwCiD25y7zwI ZbIV/1yD2OD+byhQcQ1YhYq6NE6LSX556kkzSdznqNXsRG3tmjWKBVULgelrPLT6FHN+ tEiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7E29T0HDlFgU1q0mOVCwGp4O+vEXm9+HF8E2P+7ECrw=; b=cgERdCxQEQV7S2n2XowChWTUavL8kGw/KqZkHSdmFVyQ5k3uvSP0VguQcNHu4e8uIO ERzFjLqdGXFpIq8vpwCDh+HkpSvJHpuyjb6cYMtJOylAtZpsgUd2YlI4jeSC4pKrKMd0 xWp9Bl429CasbzqnJDGJLEs1QiSPRdMjrmhDoYGsv1lpK3NpOLF7qAY44sR6UHAOK7AL jCc1+fnqZtasMgFymlQAqm+ccnp18LBLFFBT1a7AXmnvI1zrNyvd29y6vXd4iIU2BS0U WEDrxntTYjnA2kBZy90bpOTbQe0gvKATQQmgPKX0ZYDflaBJVzp64NvIqssmj5k3k11A qK+w== X-Gm-Message-State: APjAAAXvgTGevkJdst1vIAZSNr/AvxLJLSNTI6eLjL/loWgdLd7K7cvJ Wqs2LnPtpL0NX5w6GpqDwNj13aMc7gY= X-Google-Smtp-Source: APXvYqxUk5pplfOHCEaq32JCgAfDlHZSGNTx06XVb5P6r4egCUEKurgR1TYUu8kkbkF4m3JdoQDE+g== X-Received: by 2002:a65:6294:: with SMTP id f20mr6483452pgv.174.1551470713132; Fri, 01 Mar 2019 12:05:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 1 Mar 2019 12:04:57 -0800 Message-Id: <20190301200501.16533-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190301200501.16533-1-richard.henderson@linaro.org> References: <20190301200501.16533-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PATCH v3 06/10] target/arm: Rearrange disas_data_proc_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This decoding more closely matches the ARMv8.4 Table C4-6, Encoding table for Data Processing - Register Group. In particular, op2 =3D=3D 0 is now more than just Add/sub (with carry). Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 98 ++++++++++++++++++++++---------------- 1 file changed, 57 insertions(+), 41 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index eaeb43577d..12d2649c20 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4494,11 +4494,10 @@ static void disas_data_proc_3src(DisasContext *s, u= int32_t insn) } =20 /* Add/subtract (with carry) - * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 - * +--+--+--+------------------------+------+---------+------+-----+ - * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd | - * +--+--+--+------------------------+------+---------+------+-----+ - * [000000] + * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 + * +--+--+--+------------------------+------+-------------+------+-----+ + * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd | + * +--+--+--+------------------------+------+-------------+------+-----+ */ =20 static void disas_adc_sbc(DisasContext *s, uint32_t insn) @@ -4506,11 +4505,6 @@ static void disas_adc_sbc(DisasContext *s, uint32_t = insn) unsigned int sf, op, setflags, rm, rn, rd; TCGv_i64 tcg_y, tcg_rn, tcg_rd; =20 - if (extract32(insn, 10, 6) !=3D 0) { - unallocated_encoding(s); - return; - } - sf =3D extract32(insn, 31, 1); op =3D extract32(insn, 30, 1); setflags =3D extract32(insn, 29, 1); @@ -5164,47 +5158,69 @@ static void disas_data_proc_2src(DisasContext *s, u= int32_t insn) } } =20 -/* Data processing - register */ +/* + * Data processing - register + * 31 30 29 28 25 21 20 16 10 0 + * +--+---+--+---+-------+-----+-------+-------+---------+ + * | |op0| |op1| 1 0 1 | op2 | | op3 | | + * +--+---+--+---+-------+-----+-------+-------+---------+ + */ static void disas_data_proc_reg(DisasContext *s, uint32_t insn) { - switch (extract32(insn, 24, 5)) { - case 0x0a: /* Logical (shifted register) */ - disas_logic_reg(s, insn); - break; - case 0x0b: /* Add/subtract */ - if (insn & (1 << 21)) { /* (extended register) */ - disas_add_sub_ext_reg(s, insn); + int op0 =3D extract32(insn, 30, 1); + int op1 =3D extract32(insn, 28, 1); + int op2 =3D extract32(insn, 21, 4); + int op3 =3D extract32(insn, 10, 6); + + if (!op1) { + if (op2 & 8) { + if (op2 & 1) { + /* Add/sub (extended register) */ + disas_add_sub_ext_reg(s, insn); + } else { + /* Add/sub (shifted register) */ + disas_add_sub_reg(s, insn); + } } else { - disas_add_sub_reg(s, insn); + /* Logical (shifted register) */ + disas_logic_reg(s, insn); } - break; - case 0x1b: /* Data-processing (3 source) */ - disas_data_proc_3src(s, insn); - break; - case 0x1a: - switch (extract32(insn, 21, 3)) { - case 0x0: /* Add/subtract (with carry) */ + return; + } + + switch (op2) { + case 0x0: + switch (op3) { + case 0x00: /* Add/subtract (with carry) */ disas_adc_sbc(s, insn); break; - case 0x2: /* Conditional compare */ - disas_cc(s, insn); /* both imm and reg forms */ - break; - case 0x4: /* Conditional select */ - disas_cond_select(s, insn); - break; - case 0x6: /* Data-processing */ - if (insn & (1 << 30)) { /* (1 source) */ - disas_data_proc_1src(s, insn); - } else { /* (2 source) */ - disas_data_proc_2src(s, insn); - } - break; + default: - unallocated_encoding(s); - break; + goto do_unallocated; } break; + + case 0x2: /* Conditional compare */ + disas_cc(s, insn); /* both imm and reg forms */ + break; + + case 0x4: /* Conditional select */ + disas_cond_select(s, insn); + break; + + case 0x6: /* Data-processing */ + if (op0) { /* (1 source) */ + disas_data_proc_1src(s, insn); + } else { /* (2 source) */ + disas_data_proc_2src(s, insn); + } + break; + case 0x8 ... 0xf: /* (3 source) */ + disas_data_proc_3src(s, insn); + break; + default: + do_unallocated: unallocated_encoding(s); break; } --=20 2.17.2 From nobody Sun Nov 9 17:51:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[72.132.238.51]) by smtp.gmail.com with ESMTPSA id x8sm31869206pfn.137.2019.03.01.12.05.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Mar 2019 12:05:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Kg6P2uEJ+aoxoinkMArLjz3096awj3cjZO5y9GHc4bg=; b=H1PRpSOkIobt+ZnE9Ul00dToONR/GMdaSmAhpm4tfWzp50qUtU77qGP53xcmizjwZF AZQkhw4uGnyIMpqdZszWxnn3WOHIyn+4xxpg2Siua+rsm6As5eaEE1v79U6OMu3YiVVo cMHQ80fBRSlmTwAPM6E7JAIw0it3jLNZYPxVOGR9WuTQYzp/521UxSrkGpRsb1syMqBo zqMgAKlvEUDXTxcB6Zu3oJernUEyk0SYlR2WIDE36a0+4BwqVYgyxJh9SbNZlAQ6Pg83 AOnfASnGhuP6UJLhXgQO6pWEjW3OvA5qyLDka3TgAINwtU5zevxeG2mQsqSPDJOv7l8Z pEWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Kg6P2uEJ+aoxoinkMArLjz3096awj3cjZO5y9GHc4bg=; b=TDYCMBgjSHjDUbD9G6+lvNnWPwfkz68AHONS9xipKsHEsytw2AsIjfVH5gSbEjKukn 5ipYvu8jAe9NtD3C9FX04O2Edrj3cAs13JcbGe+1Pu3CErrV57xxq7PcP4nW+g7g/ti3 uYcGE2UIbfvPbAqQZCrV+kJcCMK7/Sk3IDzYMfOjfaAzr+NYxv9L0VcUtfxcMOyRfyX4 yANm8df2qujUQlHIXhTrqQATY5nLpSRF0qQvX1Q5Qinj5Y/GZSKknmFmMX23jCz/06uo H3mov+68LJFTpCmYxMK6bW5GnWCm0f03scA1uHSnboRfYhTAz9Ay3voRyGIdIyXFuiOI AArw== X-Gm-Message-State: APjAAAWVXGpaV6sCCrjUicAuHqDWNMal1TGVqKo/z9k4lhvBmIPGj7BH BVnT9XYS6xC03VVYt1J4savjz92Sekg= X-Google-Smtp-Source: APXvYqzqdJP/v+HfL5iawzXN+CkClr3oKF9twtL3CsG/1Aq/TLiNVegfnByKpERLyGazuAdr0PjoXA== X-Received: by 2002:a63:4287:: with SMTP id p129mr6308689pga.84.1551470714585; Fri, 01 Mar 2019 12:05:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 1 Mar 2019 12:04:58 -0800 Message-Id: <20190301200501.16533-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190301200501.16533-1-richard.henderson@linaro.org> References: <20190301200501.16533-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 07/10] target/arm: Implement ARMv8.4-CondM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++ linux-user/elfload.c | 1 + target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 97 +++++++++++++++++++++++++++++++++++++- 4 files changed, 103 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c822f94236..fc2909ea6d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3431,6 +3431,11 @@ static inline bool isar_feature_aa64_fhm(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) !=3D 0; } =20 +static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) !=3D 0; +} + static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 6cfebe1446..6e8762b40d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -605,6 +605,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM); GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); + GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); =20 #undef GET_FEATURE_ID =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 87337b6385..fcf79321e2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -309,6 +309,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 1); cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 12d2649c20..49a09b58e3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1657,6 +1657,14 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_TOO_MANY; =20 switch (op) { + case 0x00: /* CFINV */ + if (crm !=3D 0 || !dc_isar_feature(aa64_condm_4, s)) { + goto do_unallocated; + } + tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); + s->base.is_jmp =3D DISAS_NEXT; + break; + case 0x05: /* SPSel */ if (s->current_el =3D=3D 0) { goto do_unallocated; @@ -1710,7 +1718,6 @@ static void gen_get_nzcv(TCGv_i64 tcg_rt) } =20 static void gen_set_nzcv(TCGv_i64 tcg_rt) - { TCGv_i32 nzcv =3D tcg_temp_new_i32(); =20 @@ -4529,6 +4536,82 @@ static void disas_adc_sbc(DisasContext *s, uint32_t = insn) } } =20 +/* Rotate right into flags + * 31 30 29 21 15 10 5 4 0 + * +--+--+--+-----------------+--------+-----------+------+--+------+ + * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask | + * +--+--+--+-----------------+--------+-----------+------+--+------+ + */ +static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn) +{ + int mask =3D extract32(insn, 0, 4); + int o2 =3D extract32(insn, 4, 1); + int rn =3D extract32(insn, 5, 5); + int imm6 =3D extract32(insn, 15, 6); + int sf_op_s =3D extract32(insn, 29, 3); + TCGv_i64 tcg_rn; + TCGv_i32 nzcv; + + if (sf_op_s !=3D 5 || o2 !=3D 0 || !dc_isar_feature(aa64_condm_4, s)) { + unallocated_encoding(s); + return; + } + + tcg_rn =3D read_cpu_reg(s, rn, 1); + tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6); + + nzcv =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(nzcv, tcg_rn); + + if (mask & 8) { /* N */ + tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3); + } + if (mask & 4) { /* Z */ + tcg_gen_not_i32(cpu_ZF, nzcv); + tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4); + } + if (mask & 2) { /* C */ + tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1); + } + if (mask & 1) { /* V */ + tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0); + } + + tcg_temp_free_i32(nzcv); +} + +/* Evaluate into flags + * 31 30 29 21 15 14 10 5 4 0 + * +--+--+--+-----------------+---------+----+---------+------+--+------+ + * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask | + * +--+--+--+-----------------+---------+----+---------+------+--+------+ + */ +static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn) +{ + int o3_mask =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + int o2 =3D extract32(insn, 15, 6); + int sz =3D extract32(insn, 14, 1); + int sf_op_s =3D extract32(insn, 29, 3); + TCGv_i32 tmp; + int shift; + + if (sf_op_s !=3D 1 || o2 !=3D 0 || o3_mask !=3D 0xd || + !dc_isar_feature(aa64_condm_4, s)) { + unallocated_encoding(s); + return; + } + shift =3D sz ? 16 : 24; /* SETF16 or SETF8 */ + + tmp =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn)); + tcg_gen_shli_i32(cpu_NF, tmp, shift); + tcg_gen_shli_i32(cpu_VF, tmp, shift - 1); + tcg_gen_mov_i32(cpu_ZF, cpu_NF); + tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF); + tcg_temp_free_i32(tmp); +} + /* Conditional compare (immediate / register) * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 = 0 * +--+--+--+------------------------+--------+------+----+--+------+--+--= ---+ @@ -5195,6 +5278,18 @@ static void disas_data_proc_reg(DisasContext *s, uin= t32_t insn) disas_adc_sbc(s, insn); break; =20 + case 0x01: /* Rotate right into flags */ + case 0x21: + disas_rotate_right_into_flags(s, insn); + break; + + case 0x02: /* Evaluate into flags */ + case 0x12: + case 0x22: + case 0x32: + disas_evaluate_into_flags(s, insn); + break; + default: goto do_unallocated; } --=20 2.17.2 From nobody Sun Nov 9 17:51:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155147113053713.504516179669963; Fri, 1 Mar 2019 12:12:10 -0800 (PST) Received: from localhost ([127.0.0.1]:43547 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoVq-0004i3-Hr for importer@patchew.org; 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 08/10] target/arm: Implement ARMv8.5-CondM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Laurent Desnogues Signed-off-by: Richard Henderson --- v2: Update ID_AA64ISAR0.TS. --- target/arm/cpu.h | 5 ++++ target/arm/cpu64.c | 2 +- target/arm/translate-a64.c | 58 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fc2909ea6d..a7aaec63d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3436,6 +3436,11 @@ static inline bool isar_feature_aa64_condm_4(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) !=3D 0; } =20 +static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >=3D 2; +} + static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index fcf79321e2..9fe0844a82 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -309,7 +309,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 49a09b58e3..c2b9e800c8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1646,6 +1646,48 @@ static void handle_sync(DisasContext *s, uint32_t in= sn, } } =20 +static void gen_xaflag(void) +{ + TCGv_i32 z =3D tcg_temp_new_i32(); + + tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); + + /* + * (!C & !Z) << 31 + * (!(C | Z)) << 31 + * ~((C | Z) << 31) + * ~-(C | Z) + * (C | Z) - 1 + */ + tcg_gen_or_i32(cpu_NF, cpu_CF, z); + tcg_gen_subi_i32(cpu_NF, cpu_NF, 1); + + /* !(Z & C) */ + tcg_gen_and_i32(cpu_ZF, z, cpu_CF); + tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1); + + /* (!C & Z) << 31 -> -(Z & ~C) */ + tcg_gen_andc_i32(cpu_VF, z, cpu_CF); + tcg_gen_neg_i32(cpu_VF, cpu_VF); + + /* C | Z */ + tcg_gen_or_i32(cpu_CF, cpu_CF, z); + + tcg_temp_free_i32(z); +} + +static void gen_axflag(void) +{ + tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ + tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ + + /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */ + tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF); + + tcg_gen_movi_i32(cpu_NF, 0); + tcg_gen_movi_i32(cpu_VF, 0); +} + /* MSR (immediate) - move immediate to processor state field */ static void handle_msr_i(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int = crm) @@ -1665,6 +1707,22 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_NEXT; break; =20 + case 0x01: /* XAFlag */ + if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { + goto do_unallocated; + } + gen_xaflag(); + s->base.is_jmp =3D DISAS_NEXT; + break; + + case 0x02: /* AXFlag */ + if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { + goto do_unallocated; + } + gen_axflag(); + s->base.is_jmp =3D DISAS_NEXT; + break; + case 0x05: /* SPSel */ if (s->current_el =3D=3D 0) { goto do_unallocated; --=20 2.17.2 From nobody Sun Nov 9 17:51:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551471004001503.44840937439585; Fri, 1 Mar 2019 12:10:04 -0800 (PST) Received: from localhost ([127.0.0.1]:43486 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoTl-0002Ap-R1 for importer@patchew.org; Fri, 01 Mar 2019 15:09:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44719) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzoPd-0004kO-JL for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzoPM-0001rz-H6 for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:29 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:45111) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzoPJ-0001lJ-RT for qemu-devel@nongnu.org; Fri, 01 Mar 2019 15:05:23 -0500 Received: by mail-pg1-x52a.google.com with SMTP id y4so11905105pgc.12 for ; Fri, 01 Mar 2019 12:05:19 -0800 (PST) Received: from cloudburst.twiddle.net (cpe-72-132-238-51.dc.res.rr.com. [72.132.238.51]) by smtp.gmail.com with ESMTPSA id x8sm31869206pfn.137.2019.03.01.12.05.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Mar 2019 12:05:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tUyLPFYqwpjAIVN/Lq+PNWoyDi0ukBwdF+if0JEltxc=; b=M0j7hOzDI/Fi8wWVeYBBJgnfFzTuxhPgVNo8jCiFMfnl6sIPovfBCGz82abnluic1x 1zkX3HZhjxQ770OcHWifaeuAD5CVOjxAVhg/gAskNZeRPKW8Xq5SgdvqOANOmRK+MN8n eE5Ahkj9Yf8IDwDlQATNG7sZpDzsxGfYoxHHlPz8xkDexBwVX4Wowl3slqwIPgWhIUyt ihRAmfHJ5PnBpROO8tiS9bqDinWqINVS7JoWP5D/eRQvEC07W2RrPK4AiKHaUsYT79PQ LfDRAuwwKOuykHZ5Mp/dL2RRF4ESpcSTEJz9NnIIC5RZllX8zVswk15cXPaxYXBO/aui 9ojg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tUyLPFYqwpjAIVN/Lq+PNWoyDi0ukBwdF+if0JEltxc=; b=fBQFZcVXcuXWIW4XgAuhrObF0n7ceSvGoeFiBg4JWZn2cFuHAhm4iXwXqzdVkLKJPL B+swLKtMSqVTNVeMTBR+QVrxsWOHI2sTuoLk3dOy8NnyVglgFf+d7UbFaH8XbFaBxmfQ j8AUKxxFnuHW267ONQDyxzuDUz2dQTk25Jy/dI62Pg247qtfXB0M3M6sAeav7OwwAVLN ECaVTgjzvwRR2MRE7Sn6lYCE78WclxWqfmh05ZMHHfY3h5GSlJV8w7FpSJDOTPTQoqNd RGQuJYvTgF0pXYeFqC5Op3//RS/qed5h7Kx2ubRYzUrpTSZiH+qDunSeir+EGgYfM7vn f2dQ== X-Gm-Message-State: APjAAAWKgL3HwOLA5A63LAYCE5ejQdBuZBzTwx4WojjLdQ0nrQUFZk7r YuLd1E4yxzkumbWpT8KNjNkjXkjCGB0= X-Google-Smtp-Source: APXvYqwwPnN53Dh7/79BiUoj5oJ0oMRkCI9XaPbjGAdLUYFQyo2NC1UtwzNyIais7W3og4KPoXwAbg== X-Received: by 2002:a65:520a:: with SMTP id o10mr6736883pgp.276.1551470718125; Fri, 01 Mar 2019 12:05:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 1 Mar 2019 12:05:00 -0800 Message-Id: <20190301200501.16533-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190301200501.16533-1-richard.henderson@linaro.org> References: <20190301200501.16533-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH v3 09/10] target/arm: Restructure handle_fp_1src_{single, double} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will allow sharing code that adjusts rmode beyond the existing users. Tested-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 90 +++++++++++++++++++++----------------- 1 file changed, 49 insertions(+), 41 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c2b9e800c8..94184ea5af 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5686,55 +5686,59 @@ static void handle_fp_1src_half(DisasContext *s, in= t opcode, int rd, int rn) /* Floating-point data-processing (1 source) - single precision */ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int= rn) { + void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr); + TCGv_i32 tcg_op, tcg_res; TCGv_ptr fpst; - TCGv_i32 tcg_op; - TCGv_i32 tcg_res; + int rmode =3D -1; =20 - fpst =3D get_fpstatus_ptr(false); tcg_op =3D read_fp_sreg(s, rn); tcg_res =3D tcg_temp_new_i32(); =20 switch (opcode) { case 0x0: /* FMOV */ tcg_gen_mov_i32(tcg_res, tcg_op); - break; + goto done; case 0x1: /* FABS */ gen_helper_vfp_abss(tcg_res, tcg_op); - break; + goto done; case 0x2: /* FNEG */ gen_helper_vfp_negs(tcg_res, tcg_op); - break; + goto done; case 0x3: /* FSQRT */ gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); - break; + goto done; case 0x8: /* FRINTN */ case 0x9: /* FRINTP */ case 0xa: /* FRINTM */ case 0xb: /* FRINTZ */ case 0xc: /* FRINTA */ - { - TCGv_i32 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(opcode & 7)); - - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - gen_helper_rints(tcg_res, tcg_op, fpst); - - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); + rmode =3D arm_rmode_to_sf(opcode & 7); + gen_fpst =3D gen_helper_rints; break; - } case 0xe: /* FRINTX */ - gen_helper_rints_exact(tcg_res, tcg_op, fpst); + gen_fpst =3D gen_helper_rints_exact; break; case 0xf: /* FRINTI */ - gen_helper_rints(tcg_res, tcg_op, fpst); + gen_fpst =3D gen_helper_rints; break; default: - abort(); + g_assert_not_reached(); } =20 - write_fp_sreg(s, rd, tcg_res); - + fpst =3D get_fpstatus_ptr(false); + if (rmode >=3D 0) { + TCGv_i32 tcg_rmode =3D tcg_const_i32(rmode); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_fpst(tcg_res, tcg_op, fpst); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_temp_free_i32(tcg_rmode); + } else { + gen_fpst(tcg_res, tcg_op, fpst); + } tcg_temp_free_ptr(fpst); + + done: + write_fp_sreg(s, rd, tcg_res); tcg_temp_free_i32(tcg_op); tcg_temp_free_i32(tcg_res); } @@ -5742,9 +5746,10 @@ static void handle_fp_1src_single(DisasContext *s, i= nt opcode, int rd, int rn) /* Floating-point data-processing (1 source) - double precision */ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int= rn) { + void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr); + TCGv_i64 tcg_op, tcg_res; TCGv_ptr fpst; - TCGv_i64 tcg_op; - TCGv_i64 tcg_res; + int rmode =3D -1; =20 switch (opcode) { case 0x0: /* FMOV */ @@ -5752,48 +5757,51 @@ static void handle_fp_1src_double(DisasContext *s, = int opcode, int rd, int rn) return; } =20 - fpst =3D get_fpstatus_ptr(false); tcg_op =3D read_fp_dreg(s, rn); tcg_res =3D tcg_temp_new_i64(); =20 switch (opcode) { case 0x1: /* FABS */ gen_helper_vfp_absd(tcg_res, tcg_op); - break; + goto done; case 0x2: /* FNEG */ gen_helper_vfp_negd(tcg_res, tcg_op); - break; + goto done; case 0x3: /* FSQRT */ gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); - break; + goto done; case 0x8: /* FRINTN */ case 0x9: /* FRINTP */ case 0xa: /* FRINTM */ case 0xb: /* FRINTZ */ case 0xc: /* FRINTA */ - { - TCGv_i32 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(opcode & 7)); - - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - gen_helper_rintd(tcg_res, tcg_op, fpst); - - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); + rmode =3D arm_rmode_to_sf(opcode & 7); + gen_fpst =3D gen_helper_rintd; break; - } case 0xe: /* FRINTX */ - gen_helper_rintd_exact(tcg_res, tcg_op, fpst); + gen_fpst =3D gen_helper_rintd_exact; break; case 0xf: /* FRINTI */ - gen_helper_rintd(tcg_res, tcg_op, fpst); + gen_fpst =3D gen_helper_rintd; break; default: - abort(); + g_assert_not_reached(); } =20 - write_fp_dreg(s, rd, tcg_res); - + fpst =3D get_fpstatus_ptr(false); + if (rmode >=3D 0) { + TCGv_i32 tcg_rmode =3D tcg_const_i32(rmode); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_fpst(tcg_res, tcg_op, fpst); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_temp_free_i32(tcg_rmode); + } else { + gen_fpst(tcg_res, tcg_op, fpst); + } tcg_temp_free_ptr(fpst); + + done: + write_fp_dreg(s, rd, tcg_res); tcg_temp_free_i64(tcg_op); tcg_temp_free_i64(tcg_res); } --=20 2.17.2 From nobody Sun Nov 9 17:51:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551471021757506.920672999831; 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X-Received-From: 2607:f8b0:4864:20::435 Subject: [Qemu-devel] [PATCH v3 10/10] target/arm: Implement ARMv8.5-FRINT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++ target/arm/helper.h | 5 ++ target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++-- target/arm/vfp_helper.c | 96 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 173 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a7aaec63d7..5f23c62132 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3476,6 +3476,11 @@ static inline bool isar_feature_aa64_predinv(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) !=3D 0; } =20 +static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) !=3D 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 583adba9b0..a09566f795 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -683,6 +683,11 @@ DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9fe0844a82..228906f267 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -321,6 +321,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 94184ea5af..8907cc950a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5721,6 +5721,20 @@ static void handle_fp_1src_single(DisasContext *s, i= nt opcode, int rd, int rn) case 0xf: /* FRINTI */ gen_fpst =3D gen_helper_rints; break; + case 0x10: /* FRINT32Z */ + rmode =3D float_round_to_zero; + gen_fpst =3D gen_helper_frint32_s; + break; + case 0x11: /* FRINT32X */ + gen_fpst =3D gen_helper_frint32_s; + break; + case 0x12: /* FRINT64Z */ + rmode =3D float_round_to_zero; + gen_fpst =3D gen_helper_frint64_s; + break; + case 0x13: /* FRINT64X */ + gen_fpst =3D gen_helper_frint64_s; + break; default: g_assert_not_reached(); } @@ -5784,6 +5798,20 @@ static void handle_fp_1src_double(DisasContext *s, i= nt opcode, int rd, int rn) case 0xf: /* FRINTI */ gen_fpst =3D gen_helper_rintd; break; + case 0x10: /* FRINT32Z */ + rmode =3D float_round_to_zero; + gen_fpst =3D gen_helper_frint32_d; + break; + case 0x11: /* FRINT32X */ + gen_fpst =3D gen_helper_frint32_d; + break; + case 0x12: /* FRINT64Z */ + rmode =3D float_round_to_zero; + gen_fpst =3D gen_helper_frint64_d; + break; + case 0x13: /* FRINT64X */ + gen_fpst =3D gen_helper_frint64_d; + break; default: g_assert_not_reached(); } @@ -5920,6 +5948,13 @@ static void disas_fp_1src(DisasContext *s, uint32_t = insn) handle_fp_fcvt(s, opcode, rd, rn, dtype, type); break; } + + case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */ + if (type > 1 || !dc_isar_feature(aa64_frint, s)) { + unallocated_encoding(s); + return; + } + /* fall through */ case 0x0 ... 0x3: case 0x8 ... 0xc: case 0xe ... 0xf: @@ -5929,14 +5964,12 @@ static void disas_fp_1src(DisasContext *s, uint32_t= insn) if (!fp_access_check(s)) { return; } - handle_fp_1src_single(s, opcode, rd, rn); break; case 1: if (!fp_access_check(s)) { return; } - handle_fp_1src_double(s, opcode, rd, rn); break; case 3: @@ -5948,13 +5981,13 @@ static void disas_fp_1src(DisasContext *s, uint32_t= insn) if (!fp_access_check(s)) { return; } - handle_fp_1src_half(s, opcode, rd, rn); break; default: unallocated_encoding(s); } break; + default: unallocated_encoding(s); break; @@ -9482,6 +9515,14 @@ static void handle_2misc_64(DisasContext *s, int opc= ode, bool u, case 0x59: /* FRINTX */ gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus); break; + case 0x1e: /* FRINT32Z */ + case 0x5e: /* FRINT32X */ + gen_helper_frint32_d(tcg_rd, tcg_rn, tcg_fpstatus); + break; + case 0x1f: /* FRINT64Z */ + case 0x5f: /* FRINT64X */ + gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus); + break; default: g_assert_not_reached(); } @@ -12132,8 +12173,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) } break; case 0xc ... 0xf: - case 0x16 ... 0x1d: - case 0x1f: + case 0x16 ... 0x1f: { /* Floating point: U, size[1] and opcode indicate operation; * size[0] indicates single or double precision. @@ -12276,6 +12316,19 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) } need_fpstatus =3D true; break; + case 0x1e: /* FRINT32Z */ + case 0x1f: /* FRINT64Z */ + need_rmode =3D true; + rmode =3D FPROUNDING_ZERO; + /* fall through */ + case 0x5e: /* FRINT32X */ + case 0x5f: /* FRINT64X */ + need_fpstatus =3D true; + if ((size =3D=3D 3 && !is_q) || !dc_isar_feature(aa64_frint, s= )) { + unallocated_encoding(s); + return; + } + break; default: unallocated_encoding(s); return; @@ -12441,6 +12494,14 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) case 0x7c: /* URSQRTE */ gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x1e: /* FRINT32Z */ + case 0x5e: /* FRINT32X */ + gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x1f: /* FRINT64Z */ + case 0x5f: /* FRINT64X */ + gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus); + break; default: g_assert_not_reached(); } diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index cc7f9f5cb1..2468fc1629 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -1174,3 +1174,99 @@ uint32_t HELPER(vjcvt)(float64 value, CPUARMState *e= nv) =20 return result; } + +/* Round a float32 to an integer that fits in int32_t or int64_t. */ +static float32 frint_s(float32 f, float_status *fpst, int intsize) +{ + int old_flags =3D get_float_exception_flags(fpst); + uint32_t exp =3D extract32(f, 23, 8); + + if (unlikely(exp =3D=3D 0xff)) { + /* NaN or Inf. */ + goto overflow; + } + + /* Round and re-extract the exponent. */ + f =3D float32_round_to_int(f, fpst); + exp =3D extract32(f, 23, 8); + + /* Validate the range of the result. */ + if (exp < 126 + intsize) { + /* abs(F) <=3D INT{N}_MAX */ + return f; + } + if (exp =3D=3D 126 + intsize) { + uint32_t sign =3D extract32(f, 31, 1); + uint32_t frac =3D extract32(f, 0, 23); + if (sign && frac =3D=3D 0) { + /* F =3D=3D INT{N}_MIN */ + return f; + } + } + + overflow: + /* + * Raise Invalid and return INT{N}_MIN as a float. Revert any + * inexact exception float32_round_to_int may have raised. + */ + set_float_exception_flags(old_flags | float_flag_invalid, fpst); + return (0x100u + 126u + intsize) << 23; +} + +float32 HELPER(frint32_s)(float32 f, void *fpst) +{ + return frint_s(f, fpst, 32); +} + +float32 HELPER(frint64_s)(float32 f, void *fpst) +{ + return frint_s(f, fpst, 64); +} + +/* Round a float64 to an integer that fits in int32_t or int64_t. */ +static float64 frint_d(float64 f, float_status *fpst, int intsize) +{ + int old_flags =3D get_float_exception_flags(fpst); + uint32_t exp =3D extract64(f, 52, 11); + + if (unlikely(exp =3D=3D 0x7ff)) { + /* NaN or Inf. */ + goto overflow; + } + + /* Round and re-extract the exponent. */ + f =3D float64_round_to_int(f, fpst); + exp =3D extract64(f, 52, 11); + + /* Validate the range of the result. */ + if (exp < 1022 + intsize) { + /* abs(F) <=3D INT{N}_MAX */ + return f; + } + if (exp =3D=3D 1022 + intsize) { + uint64_t sign =3D extract64(f, 63, 1); + uint64_t frac =3D extract64(f, 0, 52); + if (sign && frac =3D=3D 0) { + /* F =3D=3D INT{N}_MIN */ + return f; + } + } + + overflow: + /* + * Raise Invalid and return INT{N}_MIN as a float. Revert any + * inexact exception float64_round_to_int may have raised. + */ + set_float_exception_flags(old_flags | float_flag_invalid, fpst); + return (uint64_t)(0x800 + 1022 + intsize) << 52; +} + +float64 HELPER(frint32_d)(float64 f, void *fpst) +{ + return frint_d(f, fpst, 32); +} + +float64 HELPER(frint64_d)(float64 f, void *fpst) +{ + return frint_d(f, fpst, 64); +} --=20 2.17.2