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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c17sm13153241wrs.17.2019.02.28.03.09.03 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Feb 2019 03:09:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XjCGnSnCXQfwQWnE+Cqw6ObXlfzc2cL7JgXyZiEugYc=; b=wqfZv/44VBVeJgAUsC3rCf3JQnup7Sg+JwpUT8SYinFh+Iv/5Ns1ZYyM8gD9b+g30C QDu4+NviT18/HlHzUGVTvOI2lOcBfYncJgea6xdoiriJ4z5sTA4qkRrpwxlrMI4EZA6c oDm0eBmqF9KLq1uWSg5N9WBxRQLdOwfUBiUClMhWFth0DPMwg5bstZM2R1joTjGcHBts d0J496ae3quVaKL2J3tlzd9wCdul6KfJEkcEYdslofPknOsQKEq2seBMEUsWHajIbZME a2r30D4bLOthk1cUBD5MwOMaJFKzgIJqvq4AbnAiRk0F8DYJVMnU4gB7cdH4r9Sf46i5 4dHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XjCGnSnCXQfwQWnE+Cqw6ObXlfzc2cL7JgXyZiEugYc=; b=c4t5gUS13FywjQ5eF8qkTNYDHBwM7FNG2XdWFIfUV0sjqsHZKNa/IvoJwq1H99ApGy wF9pyv+LO+vs5NH/dn/hohbhzNn8T9vabEZ9sunGfic/7x97NPpvOyiDblG4CzN3E+Xn SdJctSmSidfCZtM/AGiksfTHQsKCQgJA8EID5r4y5D30nzw0Vae3dme29/esWPsl/di7 5/1sti2gx4WHLBTwYJ9K26r0mpoH7+3Lwpx6GmI3qjKONQXvJPS5+FsVT+PzVdeN0ZYY rC1ZNPKoMGTo9OPcMnCSIO61ixjCFcwr1SXIQY9apUIGIB4BldKBEQq7KKIaDxRY+Dhk 75yQ== X-Gm-Message-State: APjAAAWnw7gbfVQMefSPoOZ+H8Qal4EGIss4Vz5PU2bXoWiQbjkPDcbX IMs3Y4PpA8RTQRLiacn3nkuPzJL0Dl4= X-Google-Smtp-Source: APXvYqw6uW0OOS/npd6AzRd4iI2UZYx/nXDWsg66SJcaW6okCGUpDIQxpvuLiijpoWW/B1yjVb52GQ== X-Received: by 2002:adf:e8c7:: with SMTP id k7mr6090881wrn.298.1551352145107; Thu, 28 Feb 2019 03:09:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 28 Feb 2019 11:08:26 +0000 Message-Id: <20190228110835.16159-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190228110835.16159-1-peter.maydell@linaro.org> References: <20190228110835.16159-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 Subject: [Qemu-devel] [PULL 07/16] hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The CPUWAIT register acts as a sort of power-control: if a bit in it is 1 then the CPU will have been forced into waiting when the system was reset (which in QEMU we model as the CPU starting powered off). Writing a 0 to the register will allow the CPU to boot (for QEMU, we model this as powering it on). Note that writing 0 to the register does not power off a CPU. For this to work correctly we need to also honour the INITSVTOR* registers, which let the guest control where the CPU will load its SP and PC from when it comes out of reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190219125808.25174-8-peter.maydell@linaro.org --- hw/misc/iotkit-sysctl.c | 41 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 05606017fc2..e333c8169a3 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -25,6 +25,8 @@ #include "hw/sysbus.h" #include "hw/registerfields.h" #include "hw/misc/iotkit-sysctl.h" +#include "target/arm/arm-powerctl.h" +#include "target/arm/cpu.h" =20 REG32(SECDBGSTAT, 0x0) REG32(SECDBGSET, 0x4) @@ -69,6 +71,21 @@ static const int sysctl_id[] =3D { 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; =20 +/* + * Set the initial secure vector table offset address for the core. + * This will take effect when the CPU next resets. + */ +static void set_init_vtor(uint64_t cpuid, uint32_t vtor) +{ + Object *cpuobj =3D OBJECT(arm_get_cpu_by_id(cpuid)); + + if (cpuobj) { + if (object_property_find(cpuobj, "init-svtor", NULL)) { + object_property_set_uint(cpuobj, vtor, "init-svtor", &error_ab= ort); + } + } +} + static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset, unsigned size) { @@ -229,11 +246,18 @@ static void iotkit_sysctl_write(void *opaque, hwaddr = offset, s->gretreg =3D value; break; case A_INITSVTOR0: - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n= "); s->initsvtor0 =3D value; + set_init_vtor(0, s->initsvtor0); break; case A_CPUWAIT: - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n"); + if ((s->cpuwait & 1) && !(value & 1)) { + /* Powering up CPU 0 */ + arm_set_cpu_on_and_reset(0); + } + if ((s->cpuwait & 2) && !(value & 2)) { + /* Powering up CPU 1 */ + arm_set_cpu_on_and_reset(1); + } s->cpuwait =3D value; break; case A_WICCTRL: @@ -287,8 +311,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, if (!s->is_sse200) { goto bad_offset; } - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n= "); s->initsvtor1 =3D value; + set_init_vtor(1, s->initsvtor1); break; case A_EWCTRL: if (!s->is_sse200) { @@ -382,7 +406,16 @@ static void iotkit_sysctl_reset(DeviceState *dev) s->gretreg =3D 0; s->initsvtor0 =3D 0x10000000; s->initsvtor1 =3D 0x10000000; - s->cpuwait =3D 0; + if (s->is_sse200) { + /* + * CPU 0 starts on, CPU 1 starts off. In real hardware this is + * configurable by the SoC integrator as a verilog parameter. + */ + s->cpuwait =3D 2; + } else { + /* CPU 0 starts on */ + s->cpuwait =3D 0; + } s->wicctrl =3D 0; s->scsecctrl =3D 0; s->fclk_div =3D 0; --=20 2.20.1