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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c17sm13153241wrs.17.2019.02.28.03.09.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Feb 2019 03:09:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=O3inQbSsYLCVkQrFe2EgIgcett+yWKAr1jUUsNM0bEo=; b=tdJamvkx8McaZI+fH3cuqHEES/KP14H4GSQv1nzHZ6PniBz8gFB0LcNw9tLehz0Xj7 07QHquHeY5z6XmqoYCcCU/DiZxj39Y2oSJ0JxsUyoFql8RWWRp8JgVI+k2WDixeNQg4Y gmfLjpgC4XI0uo7Xx3TpP3uiBr35wu5ijZPTbgMI0umSNkGeN9jjQglUh1zW3HNkOZ4W cmKkmrn5hoMvLINReg2OoWRlkDTwONgTc9M0/+OqKHjc0K6xh0Er4JpHxUzFcG3sZpnH wCjAfyF87ktBYCSSFSTLlqUPpfTG4mWqtjnmvbRnCZngib9K6YBYDoGcz/xRv8Nd9gm/ 6TQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O3inQbSsYLCVkQrFe2EgIgcett+yWKAr1jUUsNM0bEo=; b=KXZyXRqtod/oh5W3ajNt4XGAVwo3VQCkpkqAClcuXvYKIiEG8LC5u7JNqKB9LpLVgY cK33ntj3WrQscHiuLBi/JTdfveyHBUZ3tpchq2qbLHwZaeqipOgM//8xAREhtSOdAAty p/yyNnfJeJnKE0OFiXcmexCCdqA0DlNXTkBoksS+tE2tvTKDE3KLMqGOijr1WIY0JOO2 D84PquZobc3R8kSv+CyofjbZerx/RXhbgKARYq7aDqHxSGkPG8bXp2+z2+s6GQjBXN4S juBswFEfGPQugB/Hg/58o5qv45WFvOjnCDVuw5BiZJqwr5jP/7/Sgfix04sUV3FtyUZY e4Eg== X-Gm-Message-State: APjAAAUIYDYgFNgHL1Tu6wDXgq8jvkqvGok14jWbs0KWxX6ykuM0AABU aYPjthA5TDcbXaKVH+jpvdAboYPhNwQ= X-Google-Smtp-Source: AHgI3IZEfkHCrKH+a+tXdZrWldstQXNATdPB6YCirLiMPLL9NDKd1NenuoMSC1MGYyTLfIbY4Fe3yg== X-Received: by 2002:a7b:cbcd:: with SMTP id n13mr2631783wmi.92.1551352167228; Thu, 28 Feb 2019 03:09:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 28 Feb 2019 11:08:33 +0000 Message-Id: <20190228110835.16159-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190228110835.16159-1-peter.maydell@linaro.org> References: <20190228110835.16159-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PULL 14/16] target/arm: Implement VFMAL and VFMSL for aarch32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20190219222952.22183-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 ++ target/arm/translate.c | 129 ++++++++++++++++++++++++++++++----------- 2 files changed, 101 insertions(+), 33 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8f52914649d..36cd365efaf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3296,6 +3296,11 @@ static inline bool isar_feature_aa32_dp(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) !=3D 0; } =20 +static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) !=3D 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* diff --git a/target/arm/translate.c b/target/arm/translate.c index d845923a96b..8f7f5b95aab 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8383,15 +8383,9 @@ static int disas_neon_insn_3same_ext(DisasContext *s= , uint32_t insn) gen_helper_gvec_3_ptr *fn_gvec_ptr =3D NULL; int rd, rn, rm, opr_sz; int data =3D 0; - bool q; - - q =3D extract32(insn, 6, 1); - VFP_DREG_D(rd, insn); - VFP_DREG_N(rn, insn); - VFP_DREG_M(rm, insn); - if ((rd | rn | rm) & q) { - return 1; - } + int off_rn, off_rm; + bool is_long =3D false, q =3D extract32(insn, 6, 1); + bool ptr_is_env =3D false; =20 if ((insn & 0xfe200f10) =3D=3D 0xfc200800) { /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */ @@ -8418,10 +8412,39 @@ static int disas_neon_insn_3same_ext(DisasContext *= s, uint32_t insn) return 1; } fn_gvec =3D u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b; + } else if ((insn & 0xff300f10) =3D=3D 0xfc200810) { + /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */ + int is_s =3D extract32(insn, 23, 1); + if (!dc_isar_feature(aa32_fhm, s)) { + return 1; + } + is_long =3D true; + data =3D is_s; /* is_2 =3D=3D 0 */ + fn_gvec_ptr =3D gen_helper_gvec_fmlal_a32; + ptr_is_env =3D true; } else { return 1; } =20 + VFP_DREG_D(rd, insn); + if (rd & q) { + return 1; + } + if (q || !is_long) { + VFP_DREG_N(rn, insn); + VFP_DREG_M(rm, insn); + if ((rn | rm) & q & !is_long) { + return 1; + } + off_rn =3D vfp_reg_offset(1, rn); + off_rm =3D vfp_reg_offset(1, rm); + } else { + rn =3D VFP_SREG_N(insn); + rm =3D VFP_SREG_M(insn); + off_rn =3D vfp_reg_offset(0, rn); + off_rm =3D vfp_reg_offset(0, rm); + } + if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, syn_simd_access_trap(1, 0xe, false), s->fp_excp= _el); @@ -8433,16 +8456,19 @@ static int disas_neon_insn_3same_ext(DisasContext *= s, uint32_t insn) =20 opr_sz =3D (1 + q) * 8; if (fn_gvec_ptr) { - TCGv_ptr fpst =3D get_fpstatus_ptr(1); - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), fpst, + TCGv_ptr ptr; + if (ptr_is_env) { + ptr =3D cpu_env; + } else { + ptr =3D get_fpstatus_ptr(1); + } + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr, opr_sz, opr_sz, data, fn_gvec_ptr); - tcg_temp_free_ptr(fpst); + if (!ptr_is_env) { + tcg_temp_free_ptr(ptr); + } } else { - tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), + tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm, opr_sz, opr_sz, data, fn_gvec); } return 0; @@ -8461,14 +8487,9 @@ static int disas_neon_insn_2reg_scalar_ext(DisasCont= ext *s, uint32_t insn) gen_helper_gvec_3 *fn_gvec =3D NULL; gen_helper_gvec_3_ptr *fn_gvec_ptr =3D NULL; int rd, rn, rm, opr_sz, data; - bool q; - - q =3D extract32(insn, 6, 1); - VFP_DREG_D(rd, insn); - VFP_DREG_N(rn, insn); - if ((rd | rn) & q) { - return 1; - } + int off_rn, off_rm; + bool is_long =3D false, q =3D extract32(insn, 6, 1); + bool ptr_is_env =3D false; =20 if ((insn & 0xff000f10) =3D=3D 0xfe000800) { /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */ @@ -8497,6 +8518,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasConte= xt *s, uint32_t insn) } else if ((insn & 0xffb00f00) =3D=3D 0xfe200d00) { /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */ int u =3D extract32(insn, 4, 1); + if (!dc_isar_feature(aa32_dp, s)) { return 1; } @@ -8504,10 +8526,48 @@ static int disas_neon_insn_2reg_scalar_ext(DisasCon= text *s, uint32_t insn) /* rm is just Vm, and index is M. */ data =3D extract32(insn, 5, 1); /* index */ rm =3D extract32(insn, 0, 4); + } else if ((insn & 0xffa00f10) =3D=3D 0xfe000810) { + /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */ + int is_s =3D extract32(insn, 20, 1); + int vm20 =3D extract32(insn, 0, 3); + int vm3 =3D extract32(insn, 3, 1); + int m =3D extract32(insn, 5, 1); + int index; + + if (!dc_isar_feature(aa32_fhm, s)) { + return 1; + } + if (q) { + rm =3D vm20; + index =3D m * 2 + vm3; + } else { + rm =3D vm20 * 2 + m; + index =3D vm3; + } + is_long =3D true; + data =3D (index << 2) | is_s; /* is_2 =3D=3D 0 */ + fn_gvec_ptr =3D gen_helper_gvec_fmlal_idx_a32; + ptr_is_env =3D true; } else { return 1; } =20 + VFP_DREG_D(rd, insn); + if (rd & q) { + return 1; + } + if (q || !is_long) { + VFP_DREG_N(rn, insn); + if (rn & q & !is_long) { + return 1; + } + off_rn =3D vfp_reg_offset(1, rn); + off_rm =3D vfp_reg_offset(1, rm); + } else { + rn =3D VFP_SREG_N(insn); + off_rn =3D vfp_reg_offset(0, rn); + off_rm =3D vfp_reg_offset(0, rm); + } if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, syn_simd_access_trap(1, 0xe, false), s->fp_excp= _el); @@ -8519,16 +8579,19 @@ static int disas_neon_insn_2reg_scalar_ext(DisasCon= text *s, uint32_t insn) =20 opr_sz =3D (1 + q) * 8; if (fn_gvec_ptr) { - TCGv_ptr fpst =3D get_fpstatus_ptr(1); - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), fpst, + TCGv_ptr ptr; + if (ptr_is_env) { + ptr =3D cpu_env; + } else { + ptr =3D get_fpstatus_ptr(1); + } + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr, opr_sz, opr_sz, data, fn_gvec_ptr); - tcg_temp_free_ptr(fpst); + if (!ptr_is_env) { + tcg_temp_free_ptr(ptr); + } } else { - tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), + tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm, opr_sz, opr_sz, data, fn_gvec); } return 0; --=20 2.20.1