From nobody Sun Nov 9 13:11:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551320944443107.21698101554762; Wed, 27 Feb 2019 18:29:04 -0800 (PST) Received: from localhost ([127.0.0.1]:55900 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzBRT-0006XY-SY for importer@patchew.org; Wed, 27 Feb 2019 21:28:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43948) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzBN9-0003OJ-Ha for qemu-devel@nongnu.org; Wed, 27 Feb 2019 21:24:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzBMz-00053N-4W for qemu-devel@nongnu.org; Wed, 27 Feb 2019 21:24:21 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:40170) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzBMy-000522-Sp for qemu-devel@nongnu.org; Wed, 27 Feb 2019 21:24:21 -0500 Received: by mail-pf1-x444.google.com with SMTP id h1so8937762pfo.7 for ; Wed, 27 Feb 2019 18:24:20 -0800 (PST) Received: from cloudburst.dc.rr.com ([2605:e000:100e:478c:cfa2:eb27:db4f:e85]) by smtp.gmail.com with ESMTPSA id l28sm11928346pfi.186.2019.02.27.18.24.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Feb 2019 18:24:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xvID2qgXqZj1yGEiZojx46MlPX9UnBo71CxlwZmoZ40=; b=xCTNdYeWRjgqo7ok6xeWY3ZVoD9buli3q+Ooz/Cwtx9k6CN//5r1sAOlS2eIU/QZz/ T31zAw7ms9Rr77j9oqqp/wqAk9KAXK8Q9pH3aOwRG8InA83aDoDCKuv0ZQDQSSrA3bKV CwEC5bvk6HOD3wcKklL6Q4LR6ziv5GViDizGlmEe/rZpVug4W+piK0Lj6NM+A1jzP7hu rPVomHrKPUL0GNpoCtQ2892s5WQ2sOGhF4IyAgNsdKW2Pm2Psgj6/QHnwLuzINZzlFW1 t+Y3ILRo6VsRjwGohiBoMVltJAnnpTk3v2jwfFgf1M0y8EbI7Q6Cqd45f+THDBAqn1ZP TISQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xvID2qgXqZj1yGEiZojx46MlPX9UnBo71CxlwZmoZ40=; b=jfbRxpnhkhkyAWHvRpo5x6ywh+c9BydAs2RCdcJak1AxnbkzbYinIpuvfjiwCB7uXj Puam8bR1aK0qPoDnnLYEvKFd88XMi4GwDKf6PIrIHr5CnLK4kRtYnA8Z5HT06H2uItuw Ma856dB4ee1IFRIsQ5IchneZ8BsQPJJyexE0RnK9M4AdNtcmnGQ71FXDVLd6szMJ2aKT 14JfRLfT9cQVI6v1vyI0PBiWWcB35LomgUb4Ind4k4s7Ec2movnMzMvnxGRHVS1Xoywp 1KUEsZj9Zc4u0ggxlD6OHFb7xQ9mHMMspNcIbtIm3NFq+tG3fANTuwpnW5mQE06VHoZ6 IxbA== X-Gm-Message-State: AHQUAuZF6MNJfFzcIpbT5e0xuOZk77i6zTpkdx7DRv6CEteJAYVwcUCU vs9BG2suZ7T6NijxDTCXjRVU58Xx6q0= X-Google-Smtp-Source: AHgI3IYm2MAQLQ/KjvF/D41Hb6kBRDP0s+NvW2M5YSnoqtv8vQU25JNbRuJbXiJIyKyT/x2+b98JkQ== X-Received: by 2002:a63:455f:: with SMTP id u31mr6053273pgk.241.1551320659482; Wed, 27 Feb 2019 18:24:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Feb 2019 18:24:13 -0800 Message-Id: <20190228022415.27878-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190228022415.27878-1-richard.henderson@linaro.org> References: <20190228022415.27878-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 1/3] target/arm: Split out arm_sctlr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Minimize the number of places that will need updating when the virtual host extensions are added. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 26 ++++++++++++++++---------- target/arm/helper.c | 8 ++------ 2 files changed, 18 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1eea1a408b..9a4c56826a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3029,11 +3029,20 @@ static inline bool arm_sctlr_b(CPUARMState *env) (env->cp15.sctlr_el[1] & SCTLR_B) !=3D 0; } =20 +static inline uint64_t arm_sctlr(CPUARMState *env, int el) +{ + if (el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + return env->cp15.sctlr_el[1]; + } else { + return env->cp15.sctlr_el[el]; + } +} + + /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) { - int cur_el; - /* In 32bit endianness is determined by looking at CPSR's E bit */ if (!is_a64(env)) { return @@ -3052,15 +3061,12 @@ static inline bool arm_cpu_data_is_big_endian(CPUAR= MState *env) arm_sctlr_b(env) || #endif ((env->uncached_cpsr & CPSR_E) ? 1 : 0); + } else { + int cur_el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, cur_el); + + return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) !=3D 0; } - - cur_el =3D arm_current_el(env); - - if (cur_el =3D=3D 0) { - return (env->cp15.sctlr_el[1] & SCTLR_E0E) !=3D 0; - } - - return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) !=3D 0; } =20 #include "exec/cpu-all.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index fbaa801cea..8a71a80dfd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12877,12 +12877,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } =20 - if (current_el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr =3D env->cp15.sctlr_el[1]; - } else { - sctlr =3D env->cp15.sctlr_el[current_el]; - } + sctlr =3D arm_sctlr(env, current_el); + if (cpu_isar_feature(aa64_pauth, cpu)) { /* * In order to save space in flags, we record only whether --=20 2.17.2 From nobody Sun Nov 9 13:11:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551320778601646.1293350959663; Wed, 27 Feb 2019 18:26:18 -0800 (PST) Received: from localhost ([127.0.0.1]:55326 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzBOj-0004Mn-7z for importer@patchew.org; Wed, 27 Feb 2019 21:26:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43948) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzBN8-0003OJ-JV for qemu-devel@nongnu.org; Wed, 27 Feb 2019 21:24:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzBN0-00055X-KP for qemu-devel@nongnu.org; Wed, 27 Feb 2019 21:24:23 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:37197) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzBN0-00054M-Av for qemu-devel@nongnu.org; Wed, 27 Feb 2019 21:24:22 -0500 Received: by mail-pl1-x644.google.com with SMTP id q3so8959335pll.4 for ; Wed, 27 Feb 2019 18:24:22 -0800 (PST) Received: from cloudburst.dc.rr.com ([2605:e000:100e:478c:cfa2:eb27:db4f:e85]) by smtp.gmail.com with ESMTPSA id l28sm11928346pfi.186.2019.02.27.18.24.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Feb 2019 18:24:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LChsYdkE7QTme6BJYdMYtByCP2AoIgVkch18ulXBP7c=; b=e7/wSX0frBPLA0M/g7kFGgF0ngm8cs5fHzXxcUzaGt9pdg7w5jGf9PPoGB+r4fBiKd yNQKVgBDvf1nOH5NWXUPQRAfnY+RukL3w9ykNfixHXTSaRoz66J4vTgSnNMMkbRURhsG HaTwzaJtIIwBHW38yPoK57pJTS5tDs60z6u4NARojR57hx8VInBNMbrXubbYrH0qzhZz UeqCBQNYcV33lPBnny3f2WhVtEtLPOx6dZVcf4xS6MddcHhgXrACUbS/UzHm1N6B9yM2 6w7AIIbtQFuGBuiqxg7njXdZ8rTRBwvC301iX29I02KXSkLpq0fPHpv6TT71V/mKQl+x gkiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LChsYdkE7QTme6BJYdMYtByCP2AoIgVkch18ulXBP7c=; b=pGpYCe2CPdf5mxleetwiJAZRFnuZfAz/5ijUZJROdPbsHdPvXbiiOLjm5Dxdg9UrGK S1+7kZrFHezeZjjQ34tDaKDbkzq/1cgyqgOKaqVmDhXOMtVW/u2scRZsjgKB+ZmdxSex VObFBd2+WnzlFF1CZ1QB3xVZNa6TgTJVqERDZet2ForQ1ZM6+/+MkQXO+ckyVTmGD4Ju qKDAAgxfNVmwIrrqPi3BIVfO3vsx3/eiNaJa+lIuqcGuZG3p78N4ZFON7P6FmvBssiyB PgNYnjdIMG+f9aDfZ/H81LpyTatCat3Zt6YK64oJA1n3p77Lirkw/fFLa/kfxuan1Y15 CQKw== X-Gm-Message-State: AHQUAuac18BUEinAh6c+avqASckx8ibSi/SZ3P+y2fQAqM5Zbpi/WNAI km1mrZXDJHc/wmt9ybXlFjec9L+XnEA= X-Google-Smtp-Source: AHgI3IZPUdBb0rShPP+6vv0FWW0+zGARXeobEKB04Wwx5zaf8TZR7UNmM3wzB9j6he5qSMyb3dfTXg== X-Received: by 2002:a17:902:9683:: with SMTP id n3mr5526321plp.333.1551320660883; Wed, 27 Feb 2019 18:24:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Feb 2019 18:24:14 -0800 Message-Id: <20190228022415.27878-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190228022415.27878-1-richard.henderson@linaro.org> References: <20190228022415.27878-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 2/3] target/arm: Implement ARMv8.0-SB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++++++ linux-user/elfload.c | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ target/arm/translate-a64.c | 14 ++++++++++++++ target/arm/translate.c | 22 ++++++++++++++++++++++ 6 files changed, 50 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9a4c56826a..1a6ca35ea7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3289,6 +3289,11 @@ static inline bool isar_feature_aa32_dp(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) !=3D 0; } =20 +static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* @@ -3387,6 +3392,11 @@ static inline bool isar_feature_aa64_pauth(const ARM= ISARegisters *id) FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) !=3D 0; } =20 +static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 3a50d587ff..b7484f6d82 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -602,6 +602,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA); GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE); GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); + GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); =20 #undef GET_FEATURE_ID =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8ea6569088..7940d49c1d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2003,6 +2003,7 @@ static void arm_max_initfn(Object *obj) t =3D cpu->isar.id_isar6; t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); cpu->isar.id_isar6 =3D t; =20 t =3D cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 69e4134f79..168aa9e0f1 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -317,6 +317,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; @@ -347,6 +348,7 @@ static void aarch64_max_initfn(Object *obj) u =3D cpu->isar.id_isar6; u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); cpu->isar.id_isar6 =3D u; =20 /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c56e878787..7c00d084ce 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1637,7 +1637,21 @@ static void handle_sync(DisasContext *s, uint32_t in= sn, reset_btype(s); gen_goto_tb(s, 0, s->pc); return; + + case 7: /* SB */ + if (crm !=3D 0 || !dc_isar_feature(aa64_sb, s)) { + goto do_unallocated; + } + /* + * TODO: There is no speculation barrier opcode for TCG; + * MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc); + return; + default: + do_unallocated: unallocated_encoding(s); return; } diff --git a/target/arm/translate.c b/target/arm/translate.c index c1175798ac..b86086ada9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9208,6 +9208,17 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) */ gen_goto_tb(s, 0, s->pc & ~1); return; + case 7: /* sb */ + if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { + goto illegal_op; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc & ~1); + return; default: goto illegal_op; } @@ -11826,6 +11837,17 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) */ gen_goto_tb(s, 0, s->pc & ~1); break; + case 7: /* sb */ + if ((insn & 0xf) || !dc_isar_feature(aa32_sb, = s)) { + goto illegal_op; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc & ~1); + break; default: goto illegal_op; } --=20 2.17.2 From nobody Sun Nov 9 13:11:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 3/3] target/arm: Implement ARMv8.0-PredRes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is named "Execution and Data prediction restriction instructions" within the ARMv8.5 manual, and given the name "PredRes" by binutils. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 13 ++++++++++- target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ target/arm/helper.c | 55 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1a6ca35ea7..e1acc711cf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1060,7 +1060,8 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ #define SCTLR_F (1U << 10) /* up to v6 */ -#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ +#define SCTLR_SW (1U << 10) /* v7 */ +#define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ #define SCTLR_I (1U << 12) @@ -3294,6 +3295,11 @@ static inline bool isar_feature_aa32_sb(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; } =20 +static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* @@ -3397,6 +3403,11 @@ static inline bool isar_feature_aa64_sb(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; } =20 +static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) !=3D 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7940d49c1d..b78e1d610e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2004,6 +2004,7 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D t; =20 t =3D cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 168aa9e0f1..92c75cbfa6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -318,6 +318,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; @@ -349,6 +350,7 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D u; =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 8a71a80dfd..554f111ea8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5742,6 +5742,50 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { }; #endif =20 +static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 0) { + uint64_t sctlr =3D arm_sctlr(env, el); + if (!(sctlr & SCTLR_EnRCTX)) { + return CP_ACCESS_TRAP; + } + } else if (el =3D=3D 1) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_NV) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo predinv_reginfo[] =3D { + { .name =3D "CFP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "DVP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "CPP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + /* + * Note the AArch32 opcodes have a different OPC1. + */ + { .name =3D "CFPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "DVPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -6641,6 +6685,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, pauth_reginfo); } #endif + + /* + * While all v8.0 cpus support aarch64, QEMU does have configurations + * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max, + * which will set ID_ISAR6. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) + ? cpu_isar_feature(aa64_predinv, cpu) + : cpu_isar_feature(aa32_predinv, cpu)) { + define_arm_cp_regs(cpu, predinv_reginfo); + } } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) --=20 2.17.2