From nobody Sat Feb 7 08:27:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551181716400924.9162084253734; Tue, 26 Feb 2019 03:48:36 -0800 (PST) Received: from localhost ([127.0.0.1]:53495 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gybDt-0002Pg-AE for importer@patchew.org; Tue, 26 Feb 2019 06:48:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47384) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gyb5S-0004Zi-1k for qemu-devel@nongnu.org; Tue, 26 Feb 2019 06:39:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gyb5M-0006pd-Ks for qemu-devel@nongnu.org; Tue, 26 Feb 2019 06:39:47 -0500 Received: from mx1.redhat.com ([209.132.183.28]:47807) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gyb5M-0006it-9e; Tue, 26 Feb 2019 06:39:44 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id BB6B2306740A; Tue, 26 Feb 2019 11:39:26 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-93.ams2.redhat.com [10.36.117.93]) by smtp.corp.redhat.com (Postfix) with ESMTP id 68D42600C0; Tue, 26 Feb 2019 11:39:25 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Tue, 26 Feb 2019 12:38:45 +0100 Message-Id: <20190226113915.20150-4-david@redhat.com> In-Reply-To: <20190226113915.20150-1-david@redhat.com> References: <20190226113915.20150-1-david@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.45]); Tue, 26 Feb 2019 11:39:26 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v1 03/33] s390x: Add one temporary vector register in CPU state for TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , David Hildenbrand , Thomas Huth , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We sometimes want to work on a temporary vector register instead of the actual destination, because source and destination might overlap. An alternative would be loading the vector into two i64 variables, but than separate handling for accessing the vector elements would be needed. This is easier. Add one for now as that seems to be enough. Signed-off-by: David Hildenbrand Reviewed-by: Richard Henderson --- target/s390x/cpu.h | 11 +++++++++++ target/s390x/translate.c | 3 +++ 2 files changed, 14 insertions(+) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index cb6d77053a..a8dc0b2b83 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -67,6 +67,17 @@ struct CPUS390XState { * vregs[0][0] -> vregs[15][0] are 16 floating point registers */ CPU_DoubleU vregs[32][2]; /* vector registers */ +#ifdef CONFIG_TCG +#define TMP_VREG_0 33 + /* + * Temporary vector registers used while processing vector instructions + * in TCG. This is helpful e.g. when source and destination registers + * overlap for certain instructions in translate functions. Content va= lid + * only within execution of one translated block, therefore no migrati= on is + * needed. Resets don't mather, but has to be properly aligned. + */ + CPU_DoubleU tmp_vregs[1][2]; +#endif uint32_t aregs[16]; /* access registers */ uint8_t riccb[64]; /* runtime instrumentation control */ uint64_t gscb[4]; /* guarded storage control */ diff --git a/target/s390x/translate.c b/target/s390x/translate.c index d52c02c572..8733d19182 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -147,6 +147,9 @@ void s390x_translate_init(void) =20 static inline int vec_full_reg_offset(uint8_t reg) { + if (reg =3D=3D TMP_VREG_0) { + return offsetof(CPUS390XState, tmp_vregs[0][0].d); + } g_assert(reg < 32); return offsetof(CPUS390XState, vregs[reg][0].d); } --=20 2.17.2