From nobody Sun Nov 9 16:22:02 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551158333766904.6039975917671; Mon, 25 Feb 2019 21:18:53 -0800 (PST) Received: from localhost ([127.0.0.1]:49139 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gyV8j-00075j-Kj for importer@patchew.org; Tue, 26 Feb 2019 00:18:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57911) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gyUks-00052a-4x for qemu-devel@nongnu.org; Mon, 25 Feb 2019 23:54:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gyUko-0002TJ-H1 for qemu-devel@nongnu.org; Mon, 25 Feb 2019 23:54:10 -0500 Received: from ozlabs.org ([203.11.71.1]:43803) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gyUkn-0002Lt-O8; Mon, 25 Feb 2019 23:54:06 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 447mfL0TBqz9sNN; Tue, 26 Feb 2019 15:53:13 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1551156794; bh=EIwSN4CmxRyQFheW3wi4BM+LZSFXVJ0Ygc2iaSeXBsY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dhHMzG0BP0vznrtxU03RmFJEyaNk58wjJYIWMrMsP5E3lUkvHKNY9E2CTk4oUHtbl Ms9iZKk8Z8GOeV1We/hSZDGIvBZctSWWALqJYrbyIph7+tvA2nRyC05Ots+ed/XG/Z GEW+R4YoWrIUGGeSEhDo8pRVkHzhHPZ1f2Q02dBs= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 26 Feb 2019 15:52:40 +1100 Message-Id: <20190226045304.25618-27-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190226045304.25618-1-david@gibson.dropbear.id.au> References: <20190226045304.25618-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 26/50] target/ppc: Rename PATB/PATBE -> PATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, gkurz@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt That "b" means "base address" and thus shouldn't be in the name of actual entries and related constants. This patch keeps the synthetic patb_entry field of the spapr virtual hypervisor unchanged until I figure out if that has an impact on the migration stream. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20190215170029.15641-11-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/spapr.c | 24 +++++++++++++++--------- hw/ppc/spapr_hcall.c | 22 ++++++++++++---------- target/ppc/cpu.h | 6 +++++- target/ppc/mmu-book3s-v3.h | 11 ++++++++++- target/ppc/mmu-radix64.c | 18 ++++++++++-------- target/ppc/mmu-radix64.h | 4 ++-- 6 files changed, 54 insertions(+), 31 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index d2520bc662..00eb3b643c 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1420,11 +1420,13 @@ void spapr_set_all_lpcrs(target_ulong value, target= _ulong mask) } } =20 -static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) +static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entr= y) { sPAPRMachineState *spapr =3D SPAPR_MACHINE(vhyp); =20 - return spapr->patb_entry; + /* Copy PATE1:GR into PATE0:HR */ + entry->dw0 =3D spapr->patb_entry & PATE0_HR; + entry->dw1 =3D spapr->patb_entry; } =20 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) @@ -1667,17 +1669,21 @@ static void spapr_machine_reset(void) if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00,= 0, spapr->max_compat_pvr)) { - /* If using KVM with radix mode available, VCPUs can be started + /* + * If using KVM with radix mode available, VCPUs can be started * without a HPT because KVM will start them in radix mode. - * Set the GR bit in PATB so that we know there is no HPT. */ - spapr->patb_entry =3D PATBE1_GR; + * Set the GR bit in PATE so that we know there is no HPT. + */ + spapr->patb_entry =3D PATE1_GR; spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); } else { spapr_setup_hpt_and_vrma(spapr); } =20 - /* if this reset wasn't generated by CAS, we should reset our - * negotiated options and start from scratch */ + /* + * If this reset wasn't generated by CAS, we should reset our + * negotiated options and start from scratch + */ if (!spapr->cas_reboot) { spapr_ovec_cleanup(spapr->ov5_cas); spapr->ov5_cas =3D spapr_ovec_new(); @@ -1827,7 +1833,7 @@ static int spapr_post_load(void *opaque, int version_= id) =20 if (kvm_enabled() && spapr->patb_entry) { PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); - bool radix =3D !!(spapr->patb_entry & PATBE1_GR); + bool radix =3D !!(spapr->patb_entry & PATE1_GR); bool gtse =3D !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); =20 /* @@ -4118,7 +4124,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) vhc->map_hptes =3D spapr_map_hptes; vhc->unmap_hptes =3D spapr_unmap_hptes; vhc->store_hpte =3D spapr_store_hpte; - vhc->get_patbe =3D spapr_get_patbe; + vhc->get_pate =3D spapr_get_pate; vhc->encode_hpt_for_kvm_pr =3D spapr_encode_hpt_for_kvm_pr; xic->ics_get =3D spapr_ics_get; xic->ics_resend =3D spapr_ics_resend; diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index b47241ace6..476bad6271 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1311,12 +1311,12 @@ static void spapr_check_setup_free_hpt(sPAPRMachine= State *spapr, * later and so assumed radix and now it's called H_REG_PROC_TBL */ =20 - if ((patbe_old & PATBE1_GR) =3D=3D (patbe_new & PATBE1_GR)) { + if ((patbe_old & PATE1_GR) =3D=3D (patbe_new & PATE1_GR)) { /* We assume RADIX, so this catches all the "Do Nothing" cases */ - } else if (!(patbe_old & PATBE1_GR)) { + } else if (!(patbe_old & PATE1_GR)) { /* HASH->RADIX : Free HPT */ spapr_free_hpt(spapr); - } else if (!(patbe_new & PATBE1_GR)) { + } else if (!(patbe_new & PATE1_GR)) { /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ spapr_setup_hpt_and_vrma(spapr); } @@ -1354,7 +1354,7 @@ static target_ulong h_register_process_table(PowerPCC= PU *cpu, } else if (table_size > 24) { return H_P4; } - cproc =3D PATBE1_GR | proc_tbl | table_size; + cproc =3D PATE1_GR | proc_tbl | table_size; } else { /* Register new HPT process table */ if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tab= les */ /* TODO - Not Supported */ @@ -1373,13 +1373,15 @@ static target_ulong h_register_process_table(PowerP= CCPU *cpu, } =20 } else { /* Deregister current process table */ - /* Set to benign value: (current GR) | 0. This allows - * deregistration in KVM to succeed even if the radix bit in f= lags - * doesn't match the radix bit in the old PATB. */ - cproc =3D spapr->patb_entry & PATBE1_GR; + /* + * Set to benign value: (current GR) | 0. This allows + * deregistration in KVM to succeed even if the radix bit + * in flags doesn't match the radix bit in the old PATE. + */ + cproc =3D spapr->patb_entry & PATE1_GR; } } else { /* Maintain current registration */ - if (!(flags & FLAG_RADIX) !=3D !(spapr->patb_entry & PATBE1_GR)) { + if (!(flags & FLAG_RADIX) !=3D !(spapr->patb_entry & PATE1_GR)) { /* Technically caused by flag bits =3D> H_PARAMETER */ return H_PARAMETER; /* Existing Process Table Mismatch */ } @@ -1616,7 +1618,7 @@ static target_ulong h_client_architecture_support(Pow= erPCCPU *cpu, if (!spapr->cas_reboot) { /* If spapr_machine_reset() did not set up a HPT but one is necess= ary * (because the guest isn't going to use radix) then set it up her= e. */ - if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { + if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { /* legacy hash or new hash: */ spapr_setup_hpt_and_vrma(spapr); } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3f39a77750..26604ddf98 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -320,6 +320,10 @@ struct ppc_slb_t { #define SEGMENT_SHIFT_1T 40 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1)) =20 +typedef struct ppc_v3_pate_t { + uint64_t dw0; + uint64_t dw1; +} ppc_v3_pate_t; =20 /*************************************************************************= ****/ /* Machine state register bits definition = */ @@ -1248,7 +1252,7 @@ struct PPCVirtualHypervisorClass { hwaddr ptex, int n); void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte0, uint64_t pte1); - uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp); + void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry); target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp); }; =20 diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h index 12ec0054c2..d63ca6b1c7 100644 --- a/target/ppc/mmu-book3s-v3.h +++ b/target/ppc/mmu-book3s-v3.h @@ -29,7 +29,16 @@ #define PTCR_PATS 0x000000000000001FULL /* Partition Table S= ize */ =20 /* Partition Table Entry Fields */ -#define PATBE1_GR 0x8000000000000000 +#define PATE0_HR 0x8000000000000000 + +/* + * WARNING: This field doesn't actually exist in the final version of + * the architecture and is unused by hardware. However, qemu uses it + * as an indication of a radix guest in the pseudo-PATB entry that it + * maintains for SPAPR guests and in the migration stream, so we need + * to keep it around + */ +#define PATE1_GR 0x8000000000000000 =20 /* Process Table Entry */ struct prtb_entry { diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index ab76cbc835..a07d757063 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -194,8 +194,9 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr= eaddr, int rwx, PPCVirtualHypervisorClass *vhc =3D PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); hwaddr raddr, pte_addr; - uint64_t lpid =3D 0, pid =3D 0, offset, size, patbe, prtbe0, pte; + uint64_t lpid =3D 0, pid =3D 0, offset, size, prtbe0, pte; int page_size, prot, fault_cause =3D 0; + ppc_v3_pate_t pate; =20 assert((rwx =3D=3D 0) || (rwx =3D=3D 1) || (rwx =3D=3D 2)); assert(!msr_hv); /* For now there is no Radix PowerNV Support */ @@ -220,17 +221,17 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vad= dr eaddr, int rwx, } =20 /* Get Process Table */ - patbe =3D vhc->get_patbe(cpu->vhyp); + vhc->get_pate(cpu->vhyp, &pate); =20 /* Index Process Table by PID to Find Corresponding Process Table Entr= y */ offset =3D pid * sizeof(struct prtb_entry); - size =3D 1ULL << ((patbe & PATBE1_R_PRTS) + 12); + size =3D 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12); if (offset >=3D size) { /* offset exceeds size of the process table */ ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE); return 1; } - prtbe0 =3D ldq_phys(cs->as, (patbe & PATBE1_R_PRTB) + offset); + prtbe0 =3D ldq_phys(cs->as, (pate.dw1 & PATE1_R_PRTB) + offset); =20 /* Walk Radix Tree from Process Table Entry to Convert EA to RA */ page_size =3D PRTBE_R_GET_RTS(prtbe0); @@ -258,8 +259,9 @@ hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu,= target_ulong eaddr) PPCVirtualHypervisorClass *vhc =3D PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); hwaddr raddr, pte_addr; - uint64_t lpid =3D 0, pid =3D 0, offset, size, patbe, prtbe0, pte; + uint64_t lpid =3D 0, pid =3D 0, offset, size, prtbe0, pte; int page_size, fault_cause =3D 0; + ppc_v3_pate_t pate; =20 /* Handle Real Mode */ if (msr_dr =3D=3D 0) { @@ -273,16 +275,16 @@ hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cp= u, target_ulong eaddr) } =20 /* Get Process Table */ - patbe =3D vhc->get_patbe(cpu->vhyp); + vhc->get_pate(cpu->vhyp, &pate); =20 /* Index Process Table by PID to Find Corresponding Process Table Entr= y */ offset =3D pid * sizeof(struct prtb_entry); - size =3D 1ULL << ((patbe & PATBE1_R_PRTS) + 12); + size =3D 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12); if (offset >=3D size) { /* offset exceeds size of the process table */ return -1; } - prtbe0 =3D ldq_phys(cs->as, (patbe & PATBE1_R_PRTB) + offset); + prtbe0 =3D ldq_phys(cs->as, (pate.dw1 & PATE1_R_PRTB) + offset); =20 /* Walk Radix Tree from Process Table Entry to Convert EA to RA */ page_size =3D PRTBE_R_GET_RTS(prtbe0); diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h index 0ecf063a17..96228546aa 100644 --- a/target/ppc/mmu-radix64.h +++ b/target/ppc/mmu-radix64.h @@ -12,8 +12,8 @@ #define R_EADDR_QUADRANT3 0xC000000000000000 =20 /* Radix Partition Table Entry Fields */ -#define PATBE1_R_PRTB 0x0FFFFFFFFFFFF000 -#define PATBE1_R_PRTS 0x000000000000001F +#define PATE1_R_PRTB 0x0FFFFFFFFFFFF000 +#define PATE1_R_PRTS 0x000000000000001F =20 /* Radix Process Table Entry Fields */ #define PRTBE_R_GET_RTS(rts) \ --=20 2.20.1