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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id n1sm13214842pfi.123.2019.02.23.15.30.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 23 Feb 2019 15:30:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xHXkXT6lJgVBbNX0LyuxrSI32KVu1StCWGgAmzm2ig0=; b=J9P8VipOKoapixpi+J/A+XVBn5AGtVIvS8OnYfN1XWZdJMOCnhl+gOKtAlZKGuAu6O avYX+YM/ySvvp/D5SLBS5SjxXitGw6PpGA+I3dhyTSv+LrlWu67OqbGabxe5xKh2/C6A WBj68zBvAdlZfzHflSQWWUAR1R0lr8zpWebWIUmOsyFk+A1DmrexoqBBLwq6jLK591TN KINw20v6RvyEIFbjrF2afTV7EMQ7NB6/NufoddEuXEcO1+11m7RmKlNHojc+tGb6s8CC O3Rh6/oCBDOgc4EKxaEtS6eUDNnf4Hrihhoa8PDJ49nFmYgvO91vXeYgg1uixm+ryail hEvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xHXkXT6lJgVBbNX0LyuxrSI32KVu1StCWGgAmzm2ig0=; b=Rd5C9nfeyLwNrkBf9JKzbTI0sGJy0sCItovimrnaWye9lAPkLctVRVm9Um5JFAVggD mAAA1b/QfBcu6SV6yEIAUVWRQaUpPE51V0j4ZtPd+yV/pMARkYgDRgoKyjczU4i6K5kW 5SPKNHdwLDG5x811co3rNc8s9JuZupm1x8KKGhvhVqNcTq5eCwqad9+5ovzHLIJIxFKl 2pgE1pcvxfohfr+EnzoFl0BntfkTsRGdNWOmzsSF3pZUfcsVY5OnjefCJ0/mrjIPHBkV DKYPCMNbTCVfNy5yQkQB//V1RlWiIcsfNlBLop1eklYEGCIHN/yQScgzGSaJvyfhFjDm 2d/w== X-Gm-Message-State: AHQUAubw5TlM1u8QckKs3zzAKrx6zQR7hfh9ON9rcVCGWDYlZf0ZpAdY k39x1vRC1XSVgjPNHYEnpSTiceOJtlI= X-Google-Smtp-Source: AHgI3Ib+LP4w9Mgi5WftSw7Fq5nvweevfBwWTJM+uGsQio+jqcIVyYmf+4lCXsFv9zlCOX6kRJKwcg== X-Received: by 2002:a63:2c8a:: with SMTP id s132mr10778860pgs.440.1550964604063; Sat, 23 Feb 2019 15:30:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 23 Feb 2019 15:29:53 -0800 Message-Id: <20190223232954.7185-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223232954.7185-1-richard.henderson@linaro.org> References: <20190223232954.7185-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::534 Subject: [Qemu-devel] [RFC 6/7] target/hppa: Use pattern groups to decode OR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbastian@mail.uni-paderborn.de, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It seems clearer to decode specializations of OR within decodetree instead of by hand within the translation function. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 106 ++++++++++++++++++++------------------- target/hppa/insns.decode | 10 +++- 2 files changed, 64 insertions(+), 52 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b4fd307b77..8f5010b633 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2619,59 +2619,63 @@ static bool trans_and(DisasContext *ctx, arg_rrr_cf= *a) return do_log_reg(ctx, a, tcg_gen_and_reg); } =20 +static bool trans_copy(DisasContext *ctx, arg_copy *a) +{ + unsigned r =3D a->r; + unsigned t =3D a->t; + + if (r =3D=3D 0) { + TCGv_reg dest =3D dest_gpr(ctx, t); + tcg_gen_movi_reg(dest, 0); + save_gpr(ctx, t, dest); + } else { + save_gpr(ctx, t, cpu_gr[r]); + } + cond_free(&ctx->null_cond); + return true; +} + +static bool trans_pause(DisasContext *ctx, arg_pause *a) +{ +#ifndef CONFIG_USER_ONLY + /* + * These are QEMU extensions and are nops in the real architecture: + * + * or %r10,%r10,%r10 -- idle loop; wait for interrupt + * or %r31,%r31,%r31 -- death loop; offline cpu + * currently implemented as idle. + */ + TCGv_i32 tmp; + + /* + * No need to check for supervisor, as userland can only pause + * until the next timer interrupt. + */ + nullify_over(ctx); + + /* Advance the instruction queue. */ + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + nullify_set(ctx, 0); + + /* Tell the qemu main loop to halt until this cpu has work. */ + tmp =3D tcg_const_i32(1); + tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) + + offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp); + gen_excp_1(EXCP_HALTED); + ctx->base.is_jmp =3D DISAS_NORETURN; + + return nullify_end(ctx); +#else + /* For user-only, don't pause but treat as nop. */ + cond_free(&ctx->null_cond); + return true; +#endif +} + static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) { - if (a->cf =3D=3D 0) { - unsigned r2 =3D a->r2; - unsigned r1 =3D a->r1; - unsigned rt =3D a->t; - - if (rt =3D=3D 0) { /* NOP */ - cond_free(&ctx->null_cond); - return true; - } - if (r2 =3D=3D 0) { /* COPY */ - if (r1 =3D=3D 0) { - TCGv_reg dest =3D dest_gpr(ctx, rt); - tcg_gen_movi_reg(dest, 0); - save_gpr(ctx, rt, dest); - } else { - save_gpr(ctx, rt, cpu_gr[r1]); - } - cond_free(&ctx->null_cond); - return true; - } -#ifndef CONFIG_USER_ONLY - /* These are QEMU extensions and are nops in the real architecture: - * - * or %r10,%r10,%r10 -- idle loop; wait for interrupt - * or %r31,%r31,%r31 -- death loop; offline cpu - * currently implemented as idle. - */ - if ((rt =3D=3D 10 || rt =3D=3D 31) && r1 =3D=3D rt && r2 =3D=3D rt= ) { /* PAUSE */ - TCGv_i32 tmp; - - /* No need to check for supervisor, as userland can only pause - until the next timer interrupt. */ - nullify_over(ctx); - - /* Advance the instruction queue. */ - copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); - copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); - nullify_set(ctx, 0); - - /* Tell the qemu main loop to halt until this cpu has work. */ - tmp =3D tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) + - offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp); - gen_excp_1(EXCP_HALTED); - ctx->base.is_jmp =3D DISAS_NORETURN; - - return nullify_end(ctx); - } -#endif - } return do_log_reg(ctx, a, tcg_gen_or_reg); } =20 diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 55ff39dd05..46c64334d1 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -148,7 +148,15 @@ lci 000001 ----- ----- -- 01001100 0 t:5 =20 andcm 000010 ..... ..... .... 000000 0 ..... @rrr_cf and 000010 ..... ..... .... 001000 0 ..... @rrr_cf -or 000010 ..... ..... .... 001001 0 ..... @rrr_cf +{ + { + nop 000010 ----- ----- 0000 001001 0 00000 + copy 000010 00000 r:5 0000 001001 0 t:5 + pause 000010 01010 01010 0000 001001 0 01010 + pause 000010 11111 11111 0000 001001 0 11111 + } + or 000010 ..... ..... .... 001001 0 ..... @rrr_cf +} xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf --=20 2.17.2