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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sUYZ7XjtkLfBE/tI/sYkmY8y2UOkS0ZMT+YWEatnPQk=; b=zDNZ+mWxqdm9DRIwNu6zPIXlf0waum+c/srQ2HM4L2Ko3mz5Jcm8r7Of3/hKmIFnF2 DX+vZcx4vwCoD6p95ZWecmfsAWbTKMimJF3+cneu+iIU95inyz/FKVicWwyQxDkg1dYt rVjVwAlSYKLIBINCAMSvXQRgZV2xOd7k91101Actx6fImvg1bYnxsWOUxfCRUItA7PME kbtEAZiFVirlCvO/cri2boCWqwLOmvxuvDFvKgPdLB/+jBJOdaNF2v5ofYnM2S7Jr7Dd W+mY0UGGfebVYjTgL8HsAKhrtUdYYHVm4IImyJKFagwZo65sxGP5LeGvO9iRGohlYf6h Fudw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sUYZ7XjtkLfBE/tI/sYkmY8y2UOkS0ZMT+YWEatnPQk=; b=lxLJBF//tglsBcdHIJtgmPPa7DVb0mpexxruxoHdZ4FC6ga50iSwRJZ3ejwXt3CRT6 MrRmxjKq77GwnA/T8ENso90dAJjjRNjRSXLuo0sU9GITyIUdJH12fjCbagXbwJzls4r5 9Pj58nXM29JBRzkb/YwiRSbKFCOewzL3uhrc2GQsbw8N4nuqI2LZ86Tcjtx+Pj+bdUGy lJrUnH8JoMQ0ynoAu5uT7cO7k26FiVMihFURM1SRaD7fbqZxnptvUSiabh6XTCkB+89I hUOBTPh4BCR6/HoAXNxRziX1T8rNOuZkdBSeRtQfdukn8GfrfYs0IHgEaI+VcvoD6+7G 0BFA== X-Gm-Message-State: AHQUAubHDv3UTXyZ+YgE5KeVLiUCf+eTV3p1KgJaZTHcoTL5D8d++P5n V78tE7dz+TieLhQWKLAl1oZZWIvvi+k= X-Google-Smtp-Source: AHgI3Ia3es/Q/bRMj90yEgDQFFw2I8HMgX/5zJKwxMgiVQOOAtpn8YH8UT4qCBlkFWJFqWjQuS6OtA== X-Received: by 2002:a17:902:1102:: with SMTP id d2mr7428520pla.138.1550889605855; Fri, 22 Feb 2019 18:40:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:56 -0800 Message-Id: <20190223023957.18865-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [RFC 5/6] target/arm: Conditionalize DBGDIDR vs ID_AA64DFR0_EL1 assert X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Only perform the assert when both registers exist. Extract the variables from ID_AA64DFR0_EL1 for AArch64. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 58 +++++++++++++++++++++++++++++---------------- 1 file changed, 38 insertions(+), 20 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fbdca9324b..1d8c8998c4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5544,32 +5544,50 @@ static void define_debug_regs(ARMCPU *cpu) /* Define v7 and v8 architectural debug registers. * These are just dummy implementations for now. */ - int i; - int wrps, brps, ctx_cmps; - ARMCPRegInfo dbgdidr =3D { - .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->dbgdidr, - }; + int i, wrps, brps, ctx_cmps; + bool have_aa32; =20 - /* Note that all these register fields hold "number of Xs minus 1". */ - brps =3D extract32(cpu->dbgdidr, 24, 4); - wrps =3D extract32(cpu->dbgdidr, 28, 4); - ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); - - assert(ctx_cmps <=3D brps); - - /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties + /* + * The DBGDIDR and ID_AA64DFR0_EL1 define various properties * of the debug registers such as number of breakpoints; * check that if they both exist then they agree. + * + * Note that all these register fields hold "number of Xs minus 1". */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(extract32(cpu->id_aa64dfr0, 12, 4) =3D=3D brps); - assert(extract32(cpu->id_aa64dfr0, 20, 4) =3D=3D wrps); - assert(extract32(cpu->id_aa64dfr0, 28, 4) =3D=3D ctx_cmps); - } + brps =3D extract32(cpu->id_aa64dfr0, 12, 4); + wrps =3D extract32(cpu->id_aa64dfr0, 20, 4); + ctx_cmps =3D extract32(cpu->id_aa64dfr0, 28, 4); =20 - define_one_arm_cp_reg(cpu, &dbgdidr); + /* + * There are cpus with aarch32 only at EL0, and which do not + * have the 32-bit system registers. + */ + have_aa32 + =3D (FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D = 2 || + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL2) >=3D 2 = || + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3) >=3D 2); + if (have_aa32) { + assert(extract32(cpu->dbgdidr, 24, 4) =3D=3D brps); + assert(extract32(cpu->dbgdidr, 28, 4) =3D=3D wrps); + assert(extract32(cpu->dbgdidr, 20, 4) =3D=3D ctx_cmps); + } + } else { + have_aa32 =3D true; + brps =3D extract32(cpu->dbgdidr, 24, 4); + wrps =3D extract32(cpu->dbgdidr, 28, 4); + ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); + } + assert(ctx_cmps <=3D brps); + + if (have_aa32) { + ARMCPRegInfo dbgdidr =3D { + .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, + .opc1 =3D 0, .opc2 =3D 0, .access =3D PL0_R, .accessfn =3D acc= ess_tda, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->dbgdidr, + }; + define_one_arm_cp_reg(cpu, &dbgdidr); + } define_arm_cp_regs(cpu, debug_cp_reginfo); =20 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { --=20 2.17.2