From nobody Sun Nov 9 11:48:56 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 15508897465291015.0375731698239; Fri, 22 Feb 2019 18:42:26 -0800 (PST) Received: from localhost ([127.0.0.1]:60041 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNGT-00044X-Kr for importer@patchew.org; Fri, 22 Feb 2019 21:42:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55591) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNER-0002us-HR for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxNEQ-0002UM-OO for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:03 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:35919) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gxNEQ-0002TJ-Gz for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:02 -0500 Received: by mail-pg1-x543.google.com with SMTP id r124so1939050pgr.3 for ; Fri, 22 Feb 2019 18:40:02 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.39.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hO9tI0gl+7v0EEROptE0nDBUbXhf6NtyQAL92HWtEUU=; b=NIr/tER7mzZqZwnnkYCMxNMPtpOBmMKHL7ZIFR1IOIWMqJnj+2HZiVJa0/ngZO6ioU WNLz/nTFrxcakbARY/6jfLWhYkxFpJBoZMc/2VMfcjsGikWyrTbmJ/7os4oPgegH1jDd BlDs20+fDhL5GMBjmxnZQr2hslIZC55w0IvMgFwCEZPHRVeOicgxPV9hXjExIVn2mijB 5GhIoLau/S42K5PEzMMAMOMfyI5qHoPJC7xwex2g4ymKANwceoU6DXeaHs3S/Xx375wF myIAOwY4J20bxu8GCaMxEdia8g+tlDQI/EoFOUnFRwWKU834ZfcdN400bwkltn4HHFjC srMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hO9tI0gl+7v0EEROptE0nDBUbXhf6NtyQAL92HWtEUU=; b=PXv6RBTICtaJ8U6tJKxU9GZ1RERkcyHbuVWLescvqyij1yqgqIBGVMB3CXyEbQqoV1 3FvV7qc5coj3GyWDsrHdUvwPspqychjxVwe01qMrKBC9Gg9TXUHblIuvIfuFiSm6lEfW Oi2IPZwLxTUtKYtHg4fcZ/S81jBvo08tUUd3H+f65CkqksDGnwH0wUDSzp/EnYPPdDZm fMldboiSr9BLnfgsFp4VyiTOCfFxhSTrSZ/Sf3yQGF443LWxg0kj0qlSUkIhLXE0GUzZ VEwbHPsRlwZnhOOud4uSMu5CKIE54dm0QnQbwKP7C8rul0Sjj4Gulik+XwFF1OI3eq/y bfRQ== X-Gm-Message-State: AHQUAuZK+whCFePfBWhLO+AE+dNbAe2tZdFrBW/+PY05aM/OfRsrkPDG ikSUH71Xmn8k6tlN/gHeo0i1CljvKzs= X-Google-Smtp-Source: AHgI3IaXjxlZ6A8N7Rt62U+XuhzU409Z41H0NCYWlq1f0M/2YVMShxeiOoXruRrh3/nGqhqH8k97DQ== X-Received: by 2002:a63:f806:: with SMTP id n6mr6877471pgh.19.1550889601116; Fri, 22 Feb 2019 18:40:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:52 -0800 Message-Id: <20190223023957.18865-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 1/6] target/arm: Implement ID_PFR2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This was defined at some point before ARMv8.4, and will shortly be used by new processor descriptions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 84ae6849c2..c57f8e9ba8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -863,6 +863,7 @@ struct ARMCPU { uint32_t reset_sctlr; uint32_t id_pfr0; uint32_t id_pfr1; + uint32_t id_pfr2; uint32_t id_dfr0; uint64_t pmceid0; uint64_t pmceid1; diff --git a/target/arm/helper.c b/target/arm/helper.c index a018eb23fe..8903cc13d8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6092,10 +6092,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MVFR4_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + { .name =3D "ID_PFR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .resetvalue =3D cpu->id_pfr2 }, { .name =3D "MVFR5_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, --=20 2.17.2 From nobody Sun Nov 9 11:48:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550889872493608.5600337066877; Fri, 22 Feb 2019 18:44:32 -0800 (PST) Received: from localhost ([127.0.0.1]:60061 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNIj-0005ty-E1 for importer@patchew.org; Fri, 22 Feb 2019 21:44:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55614) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNET-0002v3-7Q for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxNER-0002WT-UQ for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:05 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:41976) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gxNER-0002V6-Nc for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:03 -0500 Received: by mail-pf1-x433.google.com with SMTP id d25so1919002pfn.8 for ; Fri, 22 Feb 2019 18:40:03 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G4evj0XBLDZtPvZuW0tTZFLLxSmrGZzJJB60I33Ox90=; b=Cei4nqcMlXReg0NZz6LP4eVjvgqqRPx3au3dW1dHUxJ4MsOuPa1MfcZVv43YDYkD2X dckgvsV0oeE7tvgiD912AWbjqWI9smJd4OnDj4VoTlFPygazdUiOt2seSdURF+gSF9QF f35kXzR663FoozOp6HgmpvMLzZkOLD0fPa5WX7QLKEqgVyx2IMoW3FfTVHt8UGXHqlgA ESHE2xFQzqa7lC44hW5ilPq5fwx4y4IKnkdoR7x/nGp5F2qF26H6r9j3hI4SHZ8i3Fsf /5Df8fAEubH3KTo/g3E94Lxie6JZDriTdDKuirmTMqAqrQrLCudjROR9xh13c1AP/sDF UUFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G4evj0XBLDZtPvZuW0tTZFLLxSmrGZzJJB60I33Ox90=; b=FDmXsQCIxae5lqIqrf8sKjbymiBU9IxjRdNvDDVeUK5z7iwtIUSb/M3j4bBA6WQGU8 M4CGg8pQTga45Dt0YNGemKoE96JomAiT12VDmBlNL0dpXyFtREGt4/pwjwdDbEizF5SD 8htr+zxwEQr8HEkWeiBamlehiPiGhQaEU4fB2LsKYPjRVD9if+6+utM87rrU9GkdIKBt MNbit4SXE2zaTijn5skLniAXaf4bPYj6ByZl/6jwtp3/8ODANE8aeHiuWKaGKjNGbvP4 WfHB7rAPH/cMGYtTPJ1TIIFVDuelKxAF9aq+bwbol1oRB1outKi8GhzRrcjE5ImOhWe+ lBQw== X-Gm-Message-State: AHQUAuZGOINTNM5uDPTSYNCqn7ZzCpWY7uMpqxLllgsfyTvlP2F6K0lZ HbXBCrFAGRliiR531o853lz0JiaFUaI= X-Google-Smtp-Source: AHgI3IbxCFimmsR9dh4/SlDfkXxtcrwA3fOP/kC9bxkszMj2H8cTq+uQgwRwjvyQ1nO6ZEQ/Fs9tyQ== X-Received: by 2002:a65:5301:: with SMTP id m1mr6739860pgq.90.1550889602261; Fri, 22 Feb 2019 18:40:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:53 -0800 Message-Id: <20190223023957.18865-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::433 Subject: [Qemu-devel] [PATCH 2/6] target/arm: Define cortex-a73 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are new field definitions, CSV2 and CSV3, that do not yet appear in the main ARM ARM. Define the ID_AA64PF0 versions, since we already define the rest of those bits. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 2 ++ hw/arm/virt.c | 1 + target/arm/cpu64.c | 63 +++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 62 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c57f8e9ba8..c2899f0bed 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1694,6 +1694,8 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR0, CSV2, 56, 4) +FIELD(ID_AA64PFR0, CSV3, 60, 4) =20 FIELD(ID_AA64PFR1, BT, 0, 4) FIELD(ID_AA64PFR1, SBSS, 4, 4) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99c2b6e60d..c69a734878 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -173,6 +173,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a73"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eff0f164dd..d34aa3af75 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -51,7 +51,8 @@ static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, con= st ARMCPRegInfo *ri) } #endif =20 -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { +/* These extra registers are used by (most of?) the cortex-a* series. */ +static const ARMCPRegInfo cortex_aXX_cp_reginfo[] =3D { #ifndef CONFIG_USER_ONLY { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, @@ -149,7 +150,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } =20 static void aarch64_a53_initfn(Object *obj) @@ -203,7 +204,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } =20 static void aarch64_a72_initfn(Object *obj) @@ -255,7 +256,60 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); +} + +static void aarch64_a73_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a73"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x411fd090; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034091; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x84448004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->id_pfr0 =3D 0x00010131; + cpu->id_pfr1 =3D 0x00011011; + cpu->id_pfr2 =3D 0x00000001; + cpu->id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x10201105; + cpu->id_mmfr1 =3D 0x40000000; + cpu->id_mmfr2 =3D 0x01260000; + cpu->id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_aa64pfr0 =3D 0x1100000000002222ull; + cpu->id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64isar0 =3D 0x00011120; + cpu->isar.id_aa64mmfr0 =3D 0x00101122; + cpu->dbgdidr =3D 0x3516d000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } =20 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, @@ -378,6 +432,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, + { .name =3D "cortex-a73", .initfn =3D aarch64_a73_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, { .name =3D NULL } }; --=20 2.17.2 From nobody Sun Nov 9 11:48:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550889745420857.4299564087574; Fri, 22 Feb 2019 18:42:25 -0800 (PST) Received: from localhost ([127.0.0.1]:60043 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNGY-00048g-Ck for importer@patchew.org; Fri, 22 Feb 2019 21:42:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55620) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNET-0002v4-P2 for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxNES-0002YC-Um for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:05 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:39500) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gxNES-0002Wz-Nc for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:04 -0500 Received: by mail-pg1-x543.google.com with SMTP id h8so1426284pgp.6 for ; Fri, 22 Feb 2019 18:40:04 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WvrXQEWeefZUb5cnHgporlJEbaVWKMTqlWlLaZjLad0=; b=EgVrDgDle+8q0p17oD5XeUjAYUJmYtNpbjNBi3efzTTU95WvQ9jwUXFc4bDrGaJLBa a4u4Vg5gQE+tSCapqPtMZnAHNouHIxEUBM5atmzuo3x2/xPPdgC591NiNyXQaNVPusw+ onE10Lm0rfpzC/1P8L6ZYnHb7ucO5ttczGaSKsVErs2CFOm6PciFtWTVGup6i/arDeQU OtdQ45KE7PGU/6EDbp/HW8Jo5yObO1cB9gGoHLKgv9VWjKTZL9rlNhwRsn0Wca5CHONH 0bCqMgboBFJ3rlBLdFylX9RPsReeuWF7AhdXCdaaNwpvMvVBjpn+/48ur8PUWpuIzjrN SkGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WvrXQEWeefZUb5cnHgporlJEbaVWKMTqlWlLaZjLad0=; b=Rz1c/ZO/WFwPgsCXB3uUbQx71Wwnxx+WmyWpcvIqUX66bZItNQqu/Jm6Oz5ClF4bkt 1xyestpTY/Wjd4k2l4mEeVmhWTd/2yQtuUdrQh/LNnZUCYlmVJxNQS8urebtMajpoa7d nSCNCN01f6Gn099mSsByRnLKUOamxXFrNFJm030d57P+MUnopb6YdnVwKmZVId6mHfjY Gbs2p44jpRjhpj2zKq8/P5pOAItSQBpVVRdffIhOvdfUtQVNfvMgNYEiCbkCRwTrRmon YnllJVsYilCujfMqeBZdlj5Mb32vTrib6u3PhFFhCLG+iic41Tk6oRHX8XHCo9RToSCy LBeA== X-Gm-Message-State: AHQUAuawSJq8WNFIJFKA94IOb6NgaoXFz3cG1xbT57h56Ykiipjsl3mg lrJq6p8OAzqM0pTkkhmHM14P7fkesOg= X-Google-Smtp-Source: AHgI3Iao3Di0wKTPOfwprCG54e4IljViFAksUbxe9uw39/esU6EQcHNIkMFEKrSNTSbO8EMRBaqccA== X-Received: by 2002:a63:ff60:: with SMTP id s32mr6829469pgk.266.1550889603427; Fri, 22 Feb 2019 18:40:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:54 -0800 Message-Id: <20190223023957.18865-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 3/6] target/arm: Implement ID_AA64MMFR2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This was res0 before ARMv8.2, but will shortly be used by new processor definitions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 15 +++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c2899f0bed..02642a7db3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -855,6 +855,7 @@ struct ARMCPU { uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; + uint64_t id_aa64mmfr2; } isar; uint32_t midr; uint32_t revidr; @@ -1724,6 +1725,20 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) =20 +FIELD(ID_AA64MMFR2, CNP, 0, 4) +FIELD(ID_AA64MMFR2, UAO, 4, 4) +FIELD(ID_AA64MMFR2, LSM, 8, 4) +FIELD(ID_AA64MMFR2, IESB, 12, 4) +FIELD(ID_AA64MMFR2, VARANGE, 16, 4) +FIELD(ID_AA64MMFR2, CCIDX, 20, 4) +FIELD(ID_AA64MMFR2, NV, 24, 4) +FIELD(ID_AA64MMFR2, ST, 28, 4) +FIELD(ID_AA64MMFR2, AT, 32, 4) +FIELD(ID_AA64MMFR2, IDS, 36, 4) +FIELD(ID_AA64MMFR2, FWB, 40, 4) +FIELD(ID_AA64MMFR2, TTL, 48, 4) +FIELD(ID_AA64MMFR2, BBM, 52, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8903cc13d8..fbdca9324b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6052,10 +6052,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.id_aa64mmfr1 }, - { .name =3D "ID_AA64MMFR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + { .name =3D "ID_AA64MMFR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .resetvalue =3D cpu->isar.id_aa64mmfr2 }, { .name =3D "ID_AA64MMFR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index e3ba149248..c3d421b53b 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -542,6 +542,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) ARM64_SYS_REG(3, 0, 0, 7, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); =20 /* * Note that if AArch32 support is not present in the host, --=20 2.17.2 From nobody Sun Nov 9 11:48:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550889747341803.22492055809; Fri, 22 Feb 2019 18:42:27 -0800 (PST) Received: from localhost ([127.0.0.1]:60047 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNGg-0004D6-8G for importer@patchew.org; Fri, 22 Feb 2019 21:42:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55649) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNEV-0002vk-C1 for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxNEU-0002aT-CG for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:07 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:34972) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gxNEU-0002ZG-2B for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:06 -0500 Received: by mail-pg1-x52a.google.com with SMTP id s198so1944194pgs.2 for ; Fri, 22 Feb 2019 18:40:05 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Xd+XJs977OpsIpeqRhkdr9DT8C+H7Lvg/r4UMKerwuM=; b=rPHAUNYMEOCTY1CU4TldS+/8uI7pUQW0GT1Gz5xifDNjtm1XT9YwWoqB4GH1KLQNIn Wc9EB619FqJwpxRj0K2oOr9Dv3swUYzyY514dgi88NZHeL2RwIarCzbrcNW9tnegXWcj HJOAjDmlsB6hftpBuvo6+bPg2JEbH2dTrfkFFf/bzjxSpq2tG1WquQkyUfVkTWiPWfW1 Vzp4FVQTKJtEYmQR3Jci0b0cDUNWg473seUBuAvZWw9WMX1zasyRh4BKBzcVCEShZdFu r7c91DqOe7Fh0mq+4Q/2IsUUCFBRR26ETkDtxmyUjbha1S/Juyo/z2vPBX1927kaOhRg Uixg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Xd+XJs977OpsIpeqRhkdr9DT8C+H7Lvg/r4UMKerwuM=; b=rCEW4GXb65YZYOpDyDuTWR6tfhUR/uvZMv7JM/952DKQvkawhs8irhO+O25bo8ZT+a TpKPvvOiTufSoeYPHen/EtaiDyXsi2mVck/Ir196zXiXN0la4QFrq7Ic9/XwR/QNX+GQ iPGzdr+nt0x+LZBPwwooD6bFIhsxXtyKm2rjHreJVlPNk6Rkeco1L0+TNU5md4Eom2Ll ZTHk1WlLcDN+vMXmhYryC0oSybAeRxSrpzlTdAwoPjKmnErex/OrbKD6EVmBRzaVFc3B BKOY7g+HdYZLQMauC+zFceJmTZrEgOplEPOGLgiCZn4Z3JnWSW+q1KHF8Byx77Efv6qH 2R3w== X-Gm-Message-State: AHQUAua6JOlHgWuaqayKdhRbGDNr/RKiDthQbjVlS3pRMTElm8wUkhqW ihTcrkhcwmsjrJH7RFCUceUlH58FIbw= X-Google-Smtp-Source: AHgI3Ia2eZpUTCb+k++OFXwbZ0ORNa0wn13m1N8s1Rz9bFiM2MIcOtmgx4iGPq1CvoCke+e+p0ddlg== X-Received: by 2002:a63:94:: with SMTP id 142mr6879792pga.74.1550889604684; Fri, 22 Feb 2019 18:40:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:55 -0800 Message-Id: <20190223023957.18865-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [RFC 4/6] target/arm: Define cortex-a75 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- hw/arm/virt.c | 1 + target/arm/cpu64.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c69a734878..06a155724c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -174,6 +174,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a73"), + ARM_CPU_TYPE_NAME("cortex-a75"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d34aa3af75..325e0ecf17 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -312,6 +312,63 @@ static void aarch64_a73_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } =20 +static void aarch64_a75_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a75"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x413fd0a1; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x410340a2; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x84448004; + cpu->reset_sctlr =3D 0x00c50838; /* ??? can't find it in a75 trm */ + cpu->id_pfr0 =3D 0x00010131; + cpu->id_pfr1 =3D 0x00011011; + cpu->id_pfr2 =3D 0x00000001; + cpu->id_dfr0 =3D 0x04010088; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x10201105; + cpu->id_mmfr1 =3D 0x40000000; + cpu->id_mmfr2 =3D 0x01260000; + cpu->id_mmfr3 =3D 0x02122211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_aa64pfr0 =3D 0x1100000010112222ull; + cpu->id_aa64dfr0 =3D 0x10305408; + cpu->isar.id_aa64isar0 =3D 0x10211120; + cpu->isar.id_aa64isar1 =3D 0x00100001; + cpu->isar.id_aa64mmfr0 =3D 0x00101124; + cpu->isar.id_aa64mmfr1 =3D 0x10212122; + cpu->isar.id_aa64mmfr2 =3D 0x00001011; + cpu->dbgdidr =3D 0x3518d000; + cpu->clidr =3D 0x08200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); +} + static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -433,6 +490,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a73", .initfn =3D aarch64_a73_initfn }, + { .name =3D "cortex-a75", .initfn =3D aarch64_a75_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, { .name =3D NULL } }; --=20 2.17.2 From nobody Sun Nov 9 11:48:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155088987544648.481923302739574; Fri, 22 Feb 2019 18:44:35 -0800 (PST) Received: from localhost ([127.0.0.1]:60063 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNIm-0005vq-Ev for importer@patchew.org; Fri, 22 Feb 2019 21:44:32 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55664) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNEW-0002we-8Z for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxNEV-0002bT-E7 for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:08 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:36707) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gxNEV-0002ag-6X for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:07 -0500 Received: by mail-pl1-x643.google.com with SMTP id k2so1913398plt.3 for ; Fri, 22 Feb 2019 18:40:07 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sUYZ7XjtkLfBE/tI/sYkmY8y2UOkS0ZMT+YWEatnPQk=; b=zDNZ+mWxqdm9DRIwNu6zPIXlf0waum+c/srQ2HM4L2Ko3mz5Jcm8r7Of3/hKmIFnF2 DX+vZcx4vwCoD6p95ZWecmfsAWbTKMimJF3+cneu+iIU95inyz/FKVicWwyQxDkg1dYt rVjVwAlSYKLIBINCAMSvXQRgZV2xOd7k91101Actx6fImvg1bYnxsWOUxfCRUItA7PME kbtEAZiFVirlCvO/cri2boCWqwLOmvxuvDFvKgPdLB/+jBJOdaNF2v5ofYnM2S7Jr7Dd W+mY0UGGfebVYjTgL8HsAKhrtUdYYHVm4IImyJKFagwZo65sxGP5LeGvO9iRGohlYf6h Fudw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sUYZ7XjtkLfBE/tI/sYkmY8y2UOkS0ZMT+YWEatnPQk=; b=lxLJBF//tglsBcdHIJtgmPPa7DVb0mpexxruxoHdZ4FC6ga50iSwRJZ3ejwXt3CRT6 MrRmxjKq77GwnA/T8ENso90dAJjjRNjRSXLuo0sU9GITyIUdJH12fjCbagXbwJzls4r5 9Pj58nXM29JBRzkb/YwiRSbKFCOewzL3uhrc2GQsbw8N4nuqI2LZ86Tcjtx+Pj+bdUGy lJrUnH8JoMQ0ynoAu5uT7cO7k26FiVMihFURM1SRaD7fbqZxnptvUSiabh6XTCkB+89I hUOBTPh4BCR6/HoAXNxRziX1T8rNOuZkdBSeRtQfdukn8GfrfYs0IHgEaI+VcvoD6+7G 0BFA== X-Gm-Message-State: AHQUAubHDv3UTXyZ+YgE5KeVLiUCf+eTV3p1KgJaZTHcoTL5D8d++P5n V78tE7dz+TieLhQWKLAl1oZZWIvvi+k= X-Google-Smtp-Source: AHgI3Ia3es/Q/bRMj90yEgDQFFw2I8HMgX/5zJKwxMgiVQOOAtpn8YH8UT4qCBlkFWJFqWjQuS6OtA== X-Received: by 2002:a17:902:1102:: with SMTP id d2mr7428520pla.138.1550889605855; Fri, 22 Feb 2019 18:40:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:56 -0800 Message-Id: <20190223023957.18865-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [RFC 5/6] target/arm: Conditionalize DBGDIDR vs ID_AA64DFR0_EL1 assert X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Only perform the assert when both registers exist. Extract the variables from ID_AA64DFR0_EL1 for AArch64. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 58 +++++++++++++++++++++++++++++---------------- 1 file changed, 38 insertions(+), 20 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fbdca9324b..1d8c8998c4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5544,32 +5544,50 @@ static void define_debug_regs(ARMCPU *cpu) /* Define v7 and v8 architectural debug registers. * These are just dummy implementations for now. */ - int i; - int wrps, brps, ctx_cmps; - ARMCPRegInfo dbgdidr =3D { - .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->dbgdidr, - }; + int i, wrps, brps, ctx_cmps; + bool have_aa32; =20 - /* Note that all these register fields hold "number of Xs minus 1". */ - brps =3D extract32(cpu->dbgdidr, 24, 4); - wrps =3D extract32(cpu->dbgdidr, 28, 4); - ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); - - assert(ctx_cmps <=3D brps); - - /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties + /* + * The DBGDIDR and ID_AA64DFR0_EL1 define various properties * of the debug registers such as number of breakpoints; * check that if they both exist then they agree. + * + * Note that all these register fields hold "number of Xs minus 1". */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(extract32(cpu->id_aa64dfr0, 12, 4) =3D=3D brps); - assert(extract32(cpu->id_aa64dfr0, 20, 4) =3D=3D wrps); - assert(extract32(cpu->id_aa64dfr0, 28, 4) =3D=3D ctx_cmps); - } + brps =3D extract32(cpu->id_aa64dfr0, 12, 4); + wrps =3D extract32(cpu->id_aa64dfr0, 20, 4); + ctx_cmps =3D extract32(cpu->id_aa64dfr0, 28, 4); =20 - define_one_arm_cp_reg(cpu, &dbgdidr); + /* + * There are cpus with aarch32 only at EL0, and which do not + * have the 32-bit system registers. + */ + have_aa32 + =3D (FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D = 2 || + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL2) >=3D 2 = || + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3) >=3D 2); + if (have_aa32) { + assert(extract32(cpu->dbgdidr, 24, 4) =3D=3D brps); + assert(extract32(cpu->dbgdidr, 28, 4) =3D=3D wrps); + assert(extract32(cpu->dbgdidr, 20, 4) =3D=3D ctx_cmps); + } + } else { + have_aa32 =3D true; + brps =3D extract32(cpu->dbgdidr, 24, 4); + wrps =3D extract32(cpu->dbgdidr, 28, 4); + ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); + } + assert(ctx_cmps <=3D brps); + + if (have_aa32) { + ARMCPRegInfo dbgdidr =3D { + .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, + .opc1 =3D 0, .opc2 =3D 0, .access =3D PL0_R, .accessfn =3D acc= ess_tda, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->dbgdidr, + }; + define_one_arm_cp_reg(cpu, &dbgdidr); + } define_arm_cp_regs(cpu, debug_cp_reginfo); =20 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { --=20 2.17.2 From nobody Sun Nov 9 11:48:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550889962329830.9031448807523; Fri, 22 Feb 2019 18:46:02 -0800 (PST) Received: from localhost ([127.0.0.1]:60108 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNKB-0006wU-EO for importer@patchew.org; Fri, 22 Feb 2019 21:45:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55689) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNEX-0002yZ-Lv for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxNEW-0002cW-PQ for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:09 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:46200) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gxNEW-0002bo-GX for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:08 -0500 Received: by mail-pl1-x62b.google.com with SMTP id o6so1875497pls.13 for ; Fri, 22 Feb 2019 18:40:08 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ApecW2tzZdNPkYdCnWki8u37VxQldFNP8bVX7A4sOco=; b=fD6mpQYRUpHEbQao/t0NyJWkVgHsJllueeFZ3rmYf9wN562nS0SxmbAmbNA1hpsoVV n9kTCdpzbT98GOwgsta0Dx8SdzHgIvGukykLsAuE6FCN6I3TctkMZd3wPsYDUxQsQxnV 6ow8x/K/PyXp1wMGQd9b01Bb8zvui88Jnl32U94WsWPHI55AHFaiFbVyb1rcynp4QdJc Ce+JZ7esrCgaca3+REznuup0V/M6ozyAyWW2EY1CfCzIj1LeTEvxbPRsOcrUaEHstYbl U3Uj48Sh4Zd1kMZ/uvcWtHMbquRtQa2b+w6paqxdn6I+g499L7j+kz5Q82wnq4jg8ts0 HbXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ApecW2tzZdNPkYdCnWki8u37VxQldFNP8bVX7A4sOco=; b=lKxLOk5DwslTQ8C9z7SnwSfmvgRR+0Irl8gsepl6/fJGRlrDlfKv/v6XjFM4y4zFTZ afN8Ana8PndTpdaVZUn3jaJrEkXp3Yb9B7BlkofHVgARdaBevnyxkbOliAXx5CWfdMpm 4lZFCsobngxiX9LNdiXW3CL6najDAflQb6DvavMyBAW9RcGaQdyhqQ39915oS4rHNDc7 SAItnhdIc2v8yu/2DRV09Mkj82xvWiqnWmj2GQuVoNQDNIn0GxA1WO9MO6yP0hX6MGRl DaxT98uwFL3shjMqYNp8/TCzekxHlwWNySX4heGPAq3Km9PSEW5LbEHR//2ewzrzd8Es t1hg== X-Gm-Message-State: AHQUAuZ+hH+BDS+Jh0wD4hq8Bgh64s3oXU5cQTcfrGK+YcfriEWe4Gnp VUcA/JAg3sRivUQaFYY53xaTY4rzfT4= X-Google-Smtp-Source: AHgI3IYgW2NQbZ0+fsY0DmLofgLIbSPrXBIAZmc83ClaszV8wY6GG1QpW7H74Yi6XMOtydd8bEWLdA== X-Received: by 2002:a17:902:ea06:: with SMTP id cu6mr7299924plb.187.1550889607074; Fri, 22 Feb 2019 18:40:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:57 -0800 Message-Id: <20190223023957.18865-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62b Subject: [Qemu-devel] [RFC 6/6] target/arm: Define cortex-a76 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- hw/arm/virt.c | 1 + target/arm/cpu64.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 06a155724c..4495ce8918 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -175,6 +175,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a73"), ARM_CPU_TYPE_NAME("cortex-a75"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 325e0ecf17..4a92d7656a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -369,6 +369,63 @@ static void aarch64_a75_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } =20 +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* + * Note that the A76 only supports AA32 at EL0, so the + * AA32-only EL1 id registers do not exist. + */ + cpu->midr =3D 0x413fd0b1; + cpu->revidr =3D 0x00000000; + cpu->ctr =3D 0x8444C004; + cpu->reset_sctlr =3D 0x30d50838; + cpu->id_pfr0 =3D 0x10010131; + cpu->id_pfr1 =3D 0x10010000; + cpu->id_pfr2 =3D 0x00000011; + cpu->id_dfr0 =3D 0x04010088; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x10201105; + cpu->id_mmfr1 =3D 0x40000000; + cpu->id_mmfr2 =3D 0x01260000; + cpu->id_mmfr3 =3D 0x02122211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; + cpu->id_aa64dfr0 =3D 0x10305408; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x00100001; + cpu->isar.id_aa64mmfr0 =3D 0x00101122; + cpu->isar.id_aa64mmfr1 =3D 0x10212122; + cpu->isar.id_aa64mmfr2 =3D 0x00001011; + cpu->clidr =3D 0x08200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); +} + static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -491,6 +548,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a73", .initfn =3D aarch64_a73_initfn }, { .name =3D "cortex-a75", .initfn =3D aarch64_a75_initfn }, + { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, { .name =3D NULL } }; --=20 2.17.2