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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id f6sm2829077wrt.87.2019.02.22.09.09.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 Feb 2019 09:09:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9Y2fmsp12Tf3NP9yxnPACBVe0lEx7m4Aj9FlcnxqqZc=; b=nzheUzVfNUNTDRN0YH+G8dhIGCNgoIKpfelurAPUhwjMNPZdEu5ZApQNQ31hOxBYEC V5NTpjgs06DR0gSZ9ddxsUVSClyl6SFg7JpP7P5y3QBjJKVVgjwdVsx5WilCcwixUej/ 5160cXhPCcz/crPGc0CHexaZE9w9oEKxF7CHiTq3z1Zpx6K9Kykp1yhLIRVQ31JPj2jv t2eTOcQrWm1bJIQbtFLcEHIsn6N4G8rtpro7WLBVHEvqXlAjUBW/v+lWHNvCIfUJnKXc K72nDZsbJxyy6ANVTauad3TzCNZZIABJySkRSwcLw0FzQmt6NVAoLN38/tgBrO5HP9Mc 8RAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Y2fmsp12Tf3NP9yxnPACBVe0lEx7m4Aj9FlcnxqqZc=; b=ob5CHogUCg+khahe6+fXLVHleGJlutvLdyz5UyD5ijOpPNH3eiPbfn69p+Gn8vFenY 2BKqqJFHhcTYmqk8yQqYgHE+gIJmk4UogwOi3yNSOUaOz5s/wO2AcLx8DaTHy3BX1DeG RdPDWZ0cx9uUjpyu3gdHc6TFZK3rnwvyfe3Pw4+ezybnLnOAwiOmTM6JeN1ZXJKkSOUN l67gpHBY5jJaeXJCn0g2KPM/r0Cvgt9DPlA/uNKJ+m0Pp4NNZIVYPaY7f0YWriPS0m78 iBDWE78J6tZuEUYO6hpkn7V+6697K4M5YjhGKzxYdyLr7cfsaUlwGd76bPg1lDuxLT6x 1D6w== X-Gm-Message-State: AHQUAubfyhIRn4SkN+nYNCQeu1cRmlTmYsbPMx3LY6pLKaBka/kMAaFp 8Bp0X4wmw5EWEIASAGZJHSbD0A== X-Google-Smtp-Source: AHgI3IaMR6dx1bXL5yQ5qtovi7+QBCgon+quRZJWFvAJ6Q/cA3o2SCoKnisL42V3r2+fhBld1BdpVA== X-Received: by 2002:adf:f70c:: with SMTP id r12mr3946648wrp.54.1550855381548; Fri, 22 Feb 2019 09:09:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 17:09:36 +0000 Message-Id: <20190222170936.13268-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190222170936.13268-1-peter.maydell@linaro.org> References: <20190222170936.13268-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 2/2] target/arm: Gate "miscellaneous FP" insns by ID register field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" There is a set of VFP instructions which we implement in disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit. These were all first introduced in v8 for A-profile, but in M-profile they appeared in v7M. Gate them on the MVFR2 FPMisc field instead, and rename the function appropriately. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 20 ++++++++++++++++++++ target/arm/translate.c | 21 +++++++++++++-------- 2 files changed, 33 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 36ea3b58567..ff9ba387b42 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3328,6 +3328,26 @@ static inline bool isar_feature_aa32_fp16_dpconv(con= st ARMISARegisters *id) return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; } =20 +static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 1; +} + +static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 2; +} + +static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 3; +} + +static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 4; +} + /* * 64-bit feature tests via id registers. */ diff --git a/target/arm/translate.c b/target/arm/translate.c index b7702fb49f7..af8f9e669b8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3357,7 +3357,7 @@ static const uint8_t fp_decode_rm[] =3D { FPROUNDING_NEGINF, }; =20 -static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn) +static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn) { uint32_t rd, rn, rm, dp =3D extract32(insn, 8, 1); =20 @@ -3375,15 +3375,18 @@ static int disas_vfp_v8_insn(DisasContext *s, uint3= 2_t insn) rm =3D VFP_SREG_M(insn); } =20 - if ((insn & 0x0f800e50) =3D=3D 0x0e000a00) { + if ((insn & 0x0f800e50) =3D=3D 0x0e000a00 && dc_isar_feature(aa32_vsel= , s)) { return handle_vsel(insn, rd, rn, rm, dp); - } else if ((insn & 0x0fb00e10) =3D=3D 0x0e800a00) { + } else if ((insn & 0x0fb00e10) =3D=3D 0x0e800a00 && + dc_isar_feature(aa32_vminmaxnm, s)) { return handle_vminmaxnm(insn, rd, rn, rm, dp); - } else if ((insn & 0x0fbc0ed0) =3D=3D 0x0eb80a40) { + } else if ((insn & 0x0fbc0ed0) =3D=3D 0x0eb80a40 && + dc_isar_feature(aa32_vrint, s)) { /* VRINTA, VRINTN, VRINTP, VRINTM */ int rounding =3D fp_decode_rm[extract32(insn, 16, 2)]; return handle_vrint(insn, rd, rm, dp, rounding); - } else if ((insn & 0x0fbc0e50) =3D=3D 0x0ebc0a40) { + } else if ((insn & 0x0fbc0e50) =3D=3D 0x0ebc0a40 && + dc_isar_feature(aa32_vcvt_dr, s)) { /* VCVTA, VCVTN, VCVTP, VCVTM */ int rounding =3D fp_decode_rm[extract32(insn, 16, 2)]; return handle_vcvt(insn, rd, rm, dp, rounding); @@ -3427,10 +3430,12 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) } =20 if (extract32(insn, 28, 4) =3D=3D 0xf) { - /* Encodings with T=3D1 (Thumb) or unconditional (ARM): - * only used in v8 and above. + /* + * Encodings with T=3D1 (Thumb) or unconditional (ARM): + * only used for the "miscellaneous VFP features" added in v8A + * and v7M (and gated on the MVFR2.FPMisc field). */ - return disas_vfp_v8_insn(s, insn); + return disas_vfp_misc_insn(s, insn); } =20 dp =3D ((insn & 0xf00) =3D=3D 0xb00); --=20 2.20.1