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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id f6sm2829077wrt.87.2019.02.22.09.09.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 Feb 2019 09:09:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LSf6wMGuBH8QT8k3geTNSuEE3goVFyvjOV9Q7bW9yHI=; b=k184oxEWXLgCRcouKw1Lqn1DHxWsY05ADQddz7TJ3+1xbcpRCRNckRImt6XjYy4tx+ AeOaguTvR0hfZd/BogybMzoifqpySOp3u7kGlImkT/SK2wwz7Npq9Phen8L2KeuQrVUU k0A3IlKZTVO6xbR4pLneq0+FkERPbXJTKVTvIBT/mBw/hm9V4rNU9spzeYeKW9G1pbTx AJiimFzTFU4RhrymdQ42Li913FirwtYK0O8+sPsodzs8I0WCgjhowBep5nA0/dOtIqL0 zOnw3KzuEwrGre0zsnV+cQ9YWWoJ54vJdDdQL/lNUWuxMaMgqOn4i682gYrATleIfmUF zbOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LSf6wMGuBH8QT8k3geTNSuEE3goVFyvjOV9Q7bW9yHI=; b=DcSPYNRsHVgm2XVseuDIvQwEEfC3QuDV+mID1EvACmBRhP1vYisaFAVS1apvRsFEVB wlI5SCQpqxdPpjyBlLFATzxJo6whWiQyGkd6W924asi2uPIuCRGzlEjcalL8kpCYk2wT NvpAK0dZXUpVwHWSdUBvfCmT4rIp5pTaC40lgAiulLrPZl2O3nvJ7XvNlU59p65T6VXC dgDrYdnDOPAUo5F2ue+AQWlFRD23OkSWxAZtAOKb1dmY4gHe7ghjQhqzAqLvahI69E3s U2NQDfYmAiHWRJFsZTh5LfM0Sm5XM5sM9GtQ15BiqQQpS49t1fj+DLt/BgOKaRvKZ/C9 8vtw== X-Gm-Message-State: AHQUAuYReVNbBSWL8r+QUj8HZD+zvqwN5U03Xy6jpQFYnb5tVYgX3LVs NL8NwWCv7S90jy21sItyBkkCWUzdSeo= X-Google-Smtp-Source: AHgI3IbHOTTjs5XClHs0PRDzcyz8bkpTyRGNU4NQ8QhJPAs1P4WL1EHh/YRVlN4EYrgfIWshNiyqKA== X-Received: by 2002:a05:6000:92:: with SMTP id m18mr3668638wrx.258.1550855380089; Fri, 22 Feb 2019 09:09:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 17:09:35 +0000 Message-Id: <20190222170936.13268-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190222170936.13268-1-peter.maydell@linaro.org> References: <20190222170936.13268-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 1/2] target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Instead of gating the A32/T32 FP16 conversion instructions on the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of looking at ID register bits. In this case MVFR1 fields FPHP and SIMDHP indicate the presence of these insns. This change doesn't alter behaviour for any of our CPUs. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 37 ++++++++++++++++++++++++++++++++++++- target/arm/cpu.c | 2 -- target/arm/kvm32.c | 3 --- target/arm/translate.c | 26 ++++++++++++++++++-------- 4 files changed, 54 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1eea1a408b8..36ea3b58567 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1730,6 +1730,27 @@ FIELD(ID_DFR0, MPROFDBG, 20, 4) FIELD(ID_DFR0, PERFMON, 24, 4) FIELD(ID_DFR0, TRACEFILT, 28, 4) =20 +FIELD(MVFR0, SIMDREG, 0, 4) +FIELD(MVFR0, FPSP, 4, 4) +FIELD(MVFR0, FPDP, 8, 4) +FIELD(MVFR0, FPTRAP, 12, 4) +FIELD(MVFR0, FPDIVIDE, 16, 4) +FIELD(MVFR0, FPSQRT, 20, 4) +FIELD(MVFR0, FPSHVEC, 24, 4) +FIELD(MVFR0, FPROUND, 28, 4) + +FIELD(MVFR1, FPFTZ, 0, 4) +FIELD(MVFR1, FPDNAN, 4, 4) +FIELD(MVFR1, SIMDLS, 8, 4) +FIELD(MVFR1, SIMDINT, 12, 4) +FIELD(MVFR1, SIMDSP, 16, 4) +FIELD(MVFR1, SIMDHP, 20, 4) +FIELD(MVFR1, FPHP, 24, 4) +FIELD(MVFR1, SIMDFMAC, 28, 4) + +FIELD(MVFR2, SIMDMISC, 0, 4) +FIELD(MVFR2, FPMISC, 4, 4) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF @@ -1747,7 +1768,6 @@ enum arm_features { ARM_FEATURE_THUMB2, ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ ARM_FEATURE_VFP3, - ARM_FEATURE_VFP_FP16, ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ @@ -3293,6 +3313,21 @@ static inline bool isar_feature_aa32_fp16_arith(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; } =20 +/* + * We always set the FP and SIMD FP16 fields to indicate identical + * levels of support (assuming SIMD is implemented at all), so + * we only need one set of accessors. + */ +static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; +} + +static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; +} + /* * 64-bit feature tests via id registers. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4d7f6a3bc0c..a3baf4eeed1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1014,7 +1014,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } if (arm_feature(env, ARM_FEATURE_VFP4)) { set_feature(env, ARM_FEATURE_VFP3); - set_feature(env, ARM_FEATURE_VFP_FP16); } if (arm_feature(env, ARM_FEATURE_VFP3)) { set_feature(env, ARM_FEATURE_VFP); @@ -1675,7 +1674,6 @@ static void cortex_a9_initfn(Object *obj) cpu->dtb_compatible =3D "arm,cortex-a9"; set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_VFP3); - set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index a75e04cc8f3..327375f6252 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -125,9 +125,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) if (extract32(id_pfr0, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_THUMB2EE); } - if (extract32(ahcf->isar.mvfr1, 20, 4) =3D=3D 1) { - set_feature(&features, ARM_FEATURE_VFP_FP16); - } if (extract32(ahcf->isar.mvfr1, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_NEON); } diff --git a/target/arm/translate.c b/target/arm/translate.c index c1175798ac9..b7702fb49f7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3663,17 +3663,27 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) * UNPREDICTABLE if bit 8 is set prior to ARMv8 * (we choose to UNDEF) */ - if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) || - !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) { - return 1; + if (dp) { + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { + return 1; + } + } else { + if (!dc_isar_feature(aa32_fp16_spconv, s)) { + return 1; + } } rm_is_dp =3D false; break; case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */ case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */ - if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) || - !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) { - return 1; + if (dp) { + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { + return 1; + } + } else { + if (!dc_isar_feature(aa32_fp16_spconv, s)) { + return 1; + } } rd_is_dp =3D false; break; @@ -7876,7 +7886,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) TCGv_ptr fpst; TCGv_i32 ahp; =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) || + if (!dc_isar_feature(aa32_fp16_spconv, s) || q || (rm & 1)) { return 1; } @@ -7908,7 +7918,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) { TCGv_ptr fpst; TCGv_i32 ahp; - if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) || + if (!dc_isar_feature(aa32_fp16_spconv, s) || q || (rd & 1)) { return 1; } --=20 2.20.1