From nobody Sat Jun 29 02:17:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550846478987202.6731562029521; Fri, 22 Feb 2019 06:41:18 -0800 (PST) Received: from localhost ([127.0.0.1]:51868 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxC0p-0003EF-RJ for importer@patchew.org; Fri, 22 Feb 2019 09:41:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxBZ8-0005qZ-D0 for qemu-devel@nongnu.org; Fri, 22 Feb 2019 09:12:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxBZ6-0008H7-Ey for qemu-devel@nongnu.org; Fri, 22 Feb 2019 09:12:38 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:56056) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gxBYt-00073M-1b; Fri, 22 Feb 2019 09:12:26 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 spheron) id 1gxBYJ-0001kc-Hz; Fri, 22 Feb 2019 15:11:47 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3137451-4; Fri, 22 Feb 2019 14:11:46 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Fri, 22 Feb 2019 15:10:15 +0100 Message-Id: <20190222141024.22217-26-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> References: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.2.22.135717, AntiVirus-Engine: 5.58.0, AntiVirus-Data: 2019.2.22.5580002 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v8 25/34] target/riscv: Remove shift and slt insn manual decoding X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 93 +++++++++++++++++-------- target/riscv/translate.c | 59 +++++----------- 2 files changed, 81 insertions(+), 71 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index 8879f2da35..88ef0003ec 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -220,30 +220,25 @@ static bool trans_addi(DisasContext *ctx, arg_addi *a) return gen_arith_imm(ctx, a, &tcg_gen_add_tl); } =20 -static bool trans_slti(DisasContext *ctx, arg_slti *a) +static void gen_slt(TCGv ret, TCGv s1, TCGv s2) { - TCGv source1; - source1 =3D tcg_temp_new(); - gen_get_gpr(source1, a->rs1); + tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2); +} + +static void gen_sltu(TCGv ret, TCGv s1, TCGv s2) +{ + tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2); +} =20 - tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm); =20 - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - return true; +static bool trans_slti(DisasContext *ctx, arg_slti *a) +{ + return gen_arith_imm(ctx, a, &gen_slt); } =20 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) { - TCGv source1; - source1 =3D tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - - tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm); - - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - return true; + return gen_arith_imm(ctx, a, &gen_sltu); } =20 static bool trans_xori(DisasContext *ctx, arg_xori *a) @@ -322,20 +317,17 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a) =20 static bool trans_sll(DisasContext *ctx, arg_sll *a) { - gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2); - return true; + return gen_shift(ctx, a, &tcg_gen_shl_tl); } =20 static bool trans_slt(DisasContext *ctx, arg_slt *a) { - gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_slt); } =20 static bool trans_sltu(DisasContext *ctx, arg_sltu *a) { - gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_sltu); } =20 static bool trans_xor(DisasContext *ctx, arg_xor *a) @@ -345,14 +337,12 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a) =20 static bool trans_srl(DisasContext *ctx, arg_srl *a) { - gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2); - return true; + return gen_shift(ctx, a, &tcg_gen_shr_tl); } =20 static bool trans_sra(DisasContext *ctx, arg_sra *a) { - gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2); - return true; + return gen_shift(ctx, a, &tcg_gen_sar_tl); } =20 static bool trans_or(DisasContext *ctx, arg_or *a) @@ -419,19 +409,62 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a) =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { - gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2); + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_andi_tl(source2, source2, 0x1F); + tcg_gen_shl_tl(source1, source1, source2); + + tcg_gen_ext32s_tl(source1, source1); + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); return true; } =20 static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { - gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2); + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + /* clear upper 32 */ + tcg_gen_ext32u_tl(source1, source1); + tcg_gen_andi_tl(source2, source2, 0x1F); + tcg_gen_shr_tl(source1, source1, source2); + + tcg_gen_ext32s_tl(source1, source1); + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); return true; } =20 static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { - gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2); + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + /* + * first, trick to get it to act like working on 32 bits (get rid of + * upper 32, sign extend to fill space) + */ + tcg_gen_ext32s_tl(source1, source1); + tcg_gen_andi_tl(source2, source2, 0x1F); + tcg_gen_sar_tl(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; } #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8eb8834633..9ae40f6509 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -198,47 +198,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,= int rd, int rs1, gen_get_gpr(source2, rs2); =20 switch (opc) { -#if defined(TARGET_RISCV64) - case OPC_RISC_SLLW: - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shl_tl(source1, source1, source2); - break; -#endif - case OPC_RISC_SLL: - tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); - tcg_gen_shl_tl(source1, source1, source2); - break; - case OPC_RISC_SLT: - tcg_gen_setcond_tl(TCG_COND_LT, source1, source1, source2); - break; - case OPC_RISC_SLTU: - tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_SRLW: - /* clear upper 32 */ - tcg_gen_ext32u_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shr_tl(source1, source1, source2); - break; -#endif - case OPC_RISC_SRL: - tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); - tcg_gen_shr_tl(source1, source1, source2); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_SRAW: - /* first, trick to get it to act like working on 32 bits (get rid = of - upper 32, sign extend to fill space) */ - tcg_gen_ext32s_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_sar_tl(source1, source1, source2); - break; -#endif - case OPC_RISC_SRA: - tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); - tcg_gen_sar_tl(source1, source1, source2); - break; CASE_OP_32_64(OPC_RISC_MUL): if (!has_ext(ctx, RVM)) { goto do_illegal; @@ -742,6 +701,24 @@ static bool trans_arith(DisasContext *ctx, arg_r *a, return true; } =20 +static bool gen_shift(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); + (*func)(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.inc.c" #include "insn_trans/trans_rvm.inc.c" --=20 2.20.1