From nobody Sat Sep 28 22:07:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15508477088981006.9265782055377; Fri, 22 Feb 2019 07:01:48 -0800 (PST) Received: from localhost ([127.0.0.1]:52228 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxCKe-0003Kt-C4 for importer@patchew.org; Fri, 22 Feb 2019 10:01:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41899) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxBaT-00077b-2B for qemu-devel@nongnu.org; Fri, 22 Feb 2019 09:14:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxBaR-00023Z-2s for qemu-devel@nongnu.org; Fri, 22 Feb 2019 09:14:00 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:41766) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gxBaN-00071k-QM; Fri, 22 Feb 2019 09:13:58 -0500 Received: from pova.uni-paderborn.de ([131.234.189.23] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 telepax) id 1gxBYI-0001xH-3T; Fri, 22 Feb 2019 15:11:46 +0100 Received: from mail.uni-paderborn.de by pova with queue id 3166477-2; Fri, 22 Feb 2019 14:11:44 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Fri, 22 Feb 2019 15:10:14 +0100 Message-Id: <20190222141024.22217-25-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> References: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.2.22.140315, AntiVirus-Engine: 5.58.0, AntiVirus-Data: 2019.2.22.5580002 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v8 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvi.inc.c | 21 +++++-------- target/riscv/translate.c | 40 +++++++++++++++---------- 3 files changed, 34 insertions(+), 30 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d6b4197841..6f3ab7aa52 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -36,11 +36,12 @@ # Argument sets: &b imm rs2 rs1 &i imm rs1 rd +&r rd rs1 rs2 &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd =20 # Formats 32: -@r ....... ..... ..... ... ..... ....... %rs2 %r= s1 %rd +@r ....... ..... ..... ... ..... ....... &r %rs2 %r= s1 %rd @i ............ ..... ... ..... ....... &i imm=3D%imm_i = %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=3D%imm_b %rs2= %rs1 @s ....... ..... ..... ... ..... ....... imm=3D%imm_s %rs2= %rs1 diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index 0265740bdb..8879f2da35 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -312,14 +312,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a) =20 static bool trans_add(DisasContext *ctx, arg_add *a) { - gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_add_tl); } =20 static bool trans_sub(DisasContext *ctx, arg_sub *a) { - gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_sub_tl); } =20 static bool trans_sll(DisasContext *ctx, arg_sll *a) @@ -342,8 +340,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a) =20 static bool trans_xor(DisasContext *ctx, arg_xor *a) { - gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_xor_tl); } =20 static bool trans_srl(DisasContext *ctx, arg_srl *a) @@ -360,14 +357,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a) =20 static bool trans_or(DisasContext *ctx, arg_or *a) { - gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_or_tl); } =20 static bool trans_and(DisasContext *ctx, arg_and *a) { - gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_and_tl); } =20 #ifdef TARGET_RISCV64 @@ -414,14 +409,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw = *a) =20 static bool trans_addw(DisasContext *ctx, arg_addw *a) { - gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_addw); } =20 static bool trans_subw(DisasContext *ctx, arg_subw *a) { - gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_subw); } =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0157758a16..8eb8834633 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -198,12 +198,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,= int rd, int rs1, gen_get_gpr(source2, rs2); =20 switch (opc) { - CASE_OP_32_64(OPC_RISC_ADD): - tcg_gen_add_tl(source1, source1, source2); - break; - CASE_OP_32_64(OPC_RISC_SUB): - tcg_gen_sub_tl(source1, source1, source2); - break; #if defined(TARGET_RISCV64) case OPC_RISC_SLLW: tcg_gen_andi_tl(source2, source2, 0x1F); @@ -220,9 +214,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, = int rd, int rs1, case OPC_RISC_SLTU: tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2); break; - case OPC_RISC_XOR: - tcg_gen_xor_tl(source1, source1, source2); - break; #if defined(TARGET_RISCV64) case OPC_RISC_SRLW: /* clear upper 32 */ @@ -248,12 +239,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,= int rd, int rs1, tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); tcg_gen_sar_tl(source1, source1, source2); break; - case OPC_RISC_OR: - tcg_gen_or_tl(source1, source1, source2); - break; - case OPC_RISC_AND: - tcg_gen_and_tl(source1, source1, source2); - break; CASE_OP_32_64(OPC_RISC_MUL): if (!has_ext(ctx, RVM)) { goto do_illegal; @@ -730,8 +715,33 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_add_tl(ret, arg1, arg2); tcg_gen_ext32s_tl(ret, ret); } + +static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_sub_tl(ret, arg1, arg2); + tcg_gen_ext32s_tl(ret, ret); +} + #endif =20 +static bool trans_arith(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1, source2; + source1 =3D tcg_temp_new(); + source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + (*func)(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.inc.c" #include "insn_trans/trans_rvm.inc.c" --=20 2.20.1