From nobody Sat Jun 29 02:09:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550846667027401.8014473486178; Fri, 22 Feb 2019 06:44:27 -0800 (PST) Received: from localhost ([127.0.0.1]:51898 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxC3o-0005Yb-SZ for importer@patchew.org; Fri, 22 Feb 2019 09:44:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxBZL-00062c-Oy for qemu-devel@nongnu.org; Fri, 22 Feb 2019 09:12:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxBZ9-0008Qe-2F for qemu-devel@nongnu.org; Fri, 22 Feb 2019 09:12:41 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:53778) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gxBYs-0006c2-MX; Fri, 22 Feb 2019 09:12:23 -0500 Received: from magmaria.uni-paderborn.de ([131.234.189.24] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 amazonia) id 1gxBY9-00015l-8O; Fri, 22 Feb 2019 15:11:37 +0100 Received: from mail.uni-paderborn.de by magmaria with queue id 3163438-3; Fri, 22 Feb 2019 14:11:36 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Fri, 22 Feb 2019 15:10:08 +0100 Message-Id: <20190222141024.22217-19-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> References: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.2.22.140315, AntiVirus-Engine: 5.58.0, AntiVirus-Data: 2019.2.19.5580002 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v8 18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- v7 -> v8: - fixed wrongly inserted #ifdef TARGET_RISCV64 that lead to a compile e= rror target/riscv/insn16.decode | 31 ++++++++ target/riscv/insn_trans/trans_rvc.inc.c | 101 ++++++++++++++++++++++++ target/riscv/translate.c | 83 +------------------ 3 files changed, 134 insertions(+), 81 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 29dade0fa1..0829e3bc59 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -20,6 +20,7 @@ %rd 7:5 %rs1_3 7:3 !function=3Dex_rvc_register %rs2_3 2:3 !function=3Dex_rvc_register +%rs2_5 2:5 =20 # Immediates: %imm_ci 12:s1 2:5 @@ -30,6 +31,10 @@ %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=3Dex_shift_1 =20 %nzuimm_6bit 12:1 2:5 +%uimm_6bit_ld 2:3 12:1 5:2 !function=3Dex_shift_3 +%uimm_6bit_lw 2:2 12:1 4:3 !function=3Dex_shift_2 +%uimm_6bit_sd 7:3 10:3 !function=3Dex_shift_3 +%uimm_6bit_sw 7:2 9:4 !function=3Dex_shift_2 =20 %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=3Dex_shift_4 %imm_lui 12:s1 2:5 !function=3Dex_shift_12 @@ -48,10 +53,15 @@ &c_j imm &c_shift shamt rd =20 +&c_ld uimm rd +&c_sd uimm rs2 =20 &c_addi16sp_lui imm_lui imm_addi16sp rd +&c_flwsp_ldsp uimm_flwsp uimm_ldsp rd +&c_fswsp_sdsp uimm_fswsp uimm_sdsp rs2 =20 # Formats 16: +@cr .... ..... ..... .. &cr rs2=3D%rs2_5 %rd @ci ... . ..... ..... .. &ci imm=3D%imm_ci %rd @ciw ... ........ ... .. &ciw nzuimm=3D%nzuimm_ciw rd= =3D%rs2_3 @cl_d ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 @@ -64,9 +74,19 @@ @cb ... ... ... .. ... .. &cb imm=3D%imm_cb rs1=3D%rs1_3 @cj ... ........... .. &c_j imm=3D%imm_cj =20 +@c_ld ... . ..... ..... .. &c_ld uimm=3D%uimm_6bit_ld %rd +@c_lw ... . ..... ..... .. &c_ld uimm=3D%uimm_6bit_lw %rd +@c_sd ... . ..... ..... .. &c_sd uimm=3D%uimm_6bit_sd rs2=3D%rs= 2_5 +@c_sw ... . ..... ..... .. &c_sd uimm=3D%uimm_6bit_sw rs2=3D%rs= 2_5 + @c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16= sp %rd +@c_flwsp_ldsp ... . ..... ..... .. &c_flwsp_ldsp uimm_flwsp=3D%uimm_6bi= t_lw \ + uimm_ldsp=3D%uimm_6bit_ld %rd +@c_fswsp_sdsp ... . ..... ..... .. &c_fswsp_sdsp uimm_fswsp=3D%uimm_6bi= t_sw \ + uimm_sdsp=3D%uimm_6bit_sd rs2=3D%rs2_5 =20 @c_shift ... . .. ... ..... .. &c_shift rd=3D%rs1_3 shamt=3D%nzuimm= _6bit +@c_shift2 ... . .. ... ..... .. &c_shift rd=3D%rd shamt=3D%nzuimm= _6bit =20 @c_andi ... . .. ... ..... .. &ci imm=3D%imm_ci rd=3D%rs1_3 =20 @@ -96,3 +116,14 @@ c_addw 100 1 11 ... 01 ... 01 @cs_2 c_j 101 ........... 01 @cj c_beqz 110 ... ... ..... 01 @cb c_bnez 111 ... ... ..... 01 @cb + +# *** RV64C Standard Extension (Quadrant 2) *** +c_slli 000 . ..... ..... 10 @c_shift2 +c_fldsp 001 . ..... ..... 10 @c_ld +c_lwsp 010 . ..... ..... 10 @c_lw +c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWS= P:RV32 +c_jr_mv 100 0 ..... ..... 10 @cr +c_ebreak_jalr_add 100 1 ..... ..... 10 @cr +c_fsdsp 101 ...... ..... 10 @c_sd +c_swsp 110 . ..... ..... 10 @c_sw +c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWS= P:RV32 diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index b06c435c98..bcdf64d3b7 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -224,3 +224,104 @@ static bool trans_c_bnez(DisasContext *ctx, arg_c_bne= z *a) arg_bne arg =3D { .rs1 =3D a->rs1, .rs2 =3D 0, .imm =3D a->imm }; return trans_bne(ctx, &arg); } + +static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a) +{ + int shamt =3D a->shamt; + if (shamt =3D=3D 0) { + /* For RV128 a shamt of 0 means a shift by 64 */ + shamt =3D 64; + } + /* Ensure, that shamt[5] is zero for RV32 */ + if (shamt >=3D TARGET_LONG_BITS) { + return false; + } + + arg_slli arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .shamt =3D a->shamt = }; + return trans_slli(ctx, &arg); +} + +static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a) +{ + arg_fld arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm }; + return trans_fld(ctx, &arg); +} + +static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a) +{ + arg_lw arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm }; + return trans_lw(ctx, &arg); +} + +static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) +{ +#ifdef TARGET_RISCV32 + /* C.FLWSP */ + arg_flw arg_flw =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm_flws= p }; + return trans_flw(ctx, &arg_flw); +#else + /* C.LDSP */ + arg_ld arg_ld =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm_ldsp }; + return trans_ld(ctx, &arg_ld); +#endif + return false; +} + +static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a) +{ + if (a->rd !=3D 0 && a->rs2 =3D=3D 0) { + /* C.JR */ + arg_jalr arg =3D { .rd =3D 0, .rs1 =3D a->rd, .imm =3D 0 }; + return trans_jalr(ctx, &arg); + } else if (a->rd !=3D 0 && a->rs2 !=3D 0) { + /* C.MV */ + arg_add arg =3D { .rd =3D a->rd, .rs1 =3D 0, .rs2 =3D a->rs2 }; + return trans_add(ctx, &arg); + } + return false; +} + +static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_a= dd *a) +{ + if (a->rd =3D=3D 0 && a->rs2 =3D=3D 0) { + /* C.EBREAK */ + arg_ebreak arg =3D { }; + return trans_ebreak(ctx, &arg); + } else if (a->rd !=3D 0) { + if (a->rs2 =3D=3D 0) { + /* C.JALR */ + arg_jalr arg =3D { .rd =3D 1, .rs1 =3D a->rd, .imm =3D 0 }; + return trans_jalr(ctx, &arg); + } else { + /* C.ADD */ + arg_add arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->r= s2 }; + return trans_add(ctx, &arg); + } + } + return false; +} + +static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a) +{ + arg_fsd arg =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm }; + return trans_fsd(ctx, &arg); +} + +static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a) +{ + arg_sw arg =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm }; + return trans_sw(ctx, &arg); +} + +static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) +{ +#ifdef TARGET_RISCV32 + /* C.FSWSP */ + arg_fsw a_fsw =3D { .rs1 =3D a->rs2, .rs2 =3D 2, .imm =3D a->uimm_fsws= p }; + return trans_fsw(ctx, &a_fsw); +#else + /* C.SDSP */ + arg_sd a_sd =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm_sdsp }; + return trans_sd(ctx, &a_sd); +#endif +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a584c24fbf..80afa2c1e6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -681,6 +681,7 @@ static void mark_fs_dirty(DisasContext *ctx) static inline void mark_fs_dirty(DisasContext *ctx) { } #endif =20 +#if !defined(TARGET_RISCV64) static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) { @@ -755,6 +756,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t op= c, int rs1, =20 tcg_temp_free(t0); } +#endif =20 static void gen_set_rm(DisasContext *ctx, int rm) { @@ -828,84 +830,6 @@ static void decode_RV32_64C0(DisasContext *ctx) } } =20 -static void decode_RV32_64C2(DisasContext *ctx) -{ - uint8_t rd, rs2; - uint8_t funct3 =3D extract32(ctx->opcode, 13, 3); - - - rd =3D GET_RD(ctx->opcode); - - switch (funct3) { - case 0: /* C.SLLI -> slli rd, rd, shamt[5:0] - C.SLLI64 -> */ - gen_arith_imm(ctx, OPC_RISC_SLLI, rd, rd, GET_C_ZIMM(ctx->opcode)); - break; - case 1: /* C.FLDSP(RV32/64DC) -> fld rd, offset[8:3](x2) */ - gen_fp_load(ctx, OPC_RISC_FLD, rd, 2, GET_C_LDSP_IMM(ctx->opcode)); - break; - case 2: /* C.LWSP -> lw rd, offset[7:2](x2) */ - gen_load(ctx, OPC_RISC_LW, rd, 2, GET_C_LWSP_IMM(ctx->opcode)); - break; - case 3: -#if defined(TARGET_RISCV64) - /* C.LDSP(RVC64) -> ld rd, offset[8:3](x2) */ - gen_load(ctx, OPC_RISC_LD, rd, 2, GET_C_LDSP_IMM(ctx->opcode)); -#else - /* C.FLWSP(RV32FC) -> flw rd, offset[7:2](x2) */ - gen_fp_load(ctx, OPC_RISC_FLW, rd, 2, GET_C_LWSP_IMM(ctx->opcode)); -#endif - break; - case 4: - rs2 =3D GET_C_RS2(ctx->opcode); - - if (extract32(ctx->opcode, 12, 1) =3D=3D 0) { - if (rs2 =3D=3D 0) { - /* C.JR -> jalr x0, rs1, 0*/ - gen_jalr(ctx, OPC_RISC_JALR, 0, rd, 0); - } else { - /* C.MV -> add rd, x0, rs2 */ - gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2); - } - } else { - if (rd =3D=3D 0) { - /* C.EBREAK -> ebreak*/ - gen_system(ctx, OPC_RISC_ECALL, 0, 0, 0x1); - } else { - if (rs2 =3D=3D 0) { - /* C.JALR -> jalr x1, rs1, 0*/ - gen_jalr(ctx, OPC_RISC_JALR, 1, rd, 0); - } else { - /* C.ADD -> add rd, rd, rs2 */ - gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2); - } - } - } - break; - case 5: - /* C.FSDSP -> fsd rs2, offset[8:3](x2)*/ - gen_fp_store(ctx, OPC_RISC_FSD, 2, GET_C_RS2(ctx->opcode), - GET_C_SDSP_IMM(ctx->opcode)); - /* C.SQSP */ - break; - case 6: /* C.SWSP -> sw rs2, offset[7:2](x2)*/ - gen_store(ctx, OPC_RISC_SW, 2, GET_C_RS2(ctx->opcode), - GET_C_SWSP_IMM(ctx->opcode)); - break; - case 7: -#if defined(TARGET_RISCV64) - /* C.SDSP(Rv64/128) -> sd rs2, offset[8:3](x2)*/ - gen_store(ctx, OPC_RISC_SD, 2, GET_C_RS2(ctx->opcode), - GET_C_SDSP_IMM(ctx->opcode)); -#else - /* C.FSWSP(RV32) -> fsw rs2, offset[7:2](x2) */ - gen_fp_store(ctx, OPC_RISC_FSW, 2, GET_C_RS2(ctx->opcode), - GET_C_SWSP_IMM(ctx->opcode)); -#endif - break; - } -} - static void decode_RV32_64C(DisasContext *ctx) { uint8_t op =3D extract32(ctx->opcode, 0, 2); @@ -914,9 +838,6 @@ static void decode_RV32_64C(DisasContext *ctx) case 0: decode_RV32_64C0(ctx); break; - case 2: - decode_RV32_64C2(ctx); - break; } } =20 --=20 2.20.1